CN114336531A

CN114336531A - Leakage protection circuit and electronic device

Info

Publication number: CN114336531A
Application number: CN202210221015.5A
Authority: CN
Inventors: 曹雷; 朱辰; 黄停; 周海滨
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-03-09
Filing date: 2022-03-09
Publication date: 2022-04-12
Anticipated expiration: 2042-03-09
Also published as: CN114336531B

Abstract

The application provides a leakage protection circuit and electronic equipment, electronic equipment includes battery and power consumption circuit, the power consumption circuit includes: a first circuit including a first terminal for receiving a voltage signal and a second terminal, the second terminal being grounded through a low resistance circuit, the leakage protection circuit comprising: the first end of the switch is used for being connected with the negative pole ear of the battery, and the second end of the switch is used for being connected with the second end of the first circuit; the output end of the control circuit is connected with the control end of the switch; the control circuit is used for: when the voltage of the battery is lower than a preset first voltage threshold value, the switch is controlled to be turned off, and when the voltage of the battery is not lower than the preset first voltage threshold value, the switch is controlled to be turned on. The problem of battery leakage after electronic equipment shuts down can be solved to this application, prolongs battery life.

Description

Leakage protection circuit and electronic device

Technical Field

The application relates to the technical field of charging and discharging, in particular to a leakage protection circuit and electronic equipment.

Background

When an electronic device (such as a mobile phone) is turned off, a power utilization circuit in the electronic device still exists as impedance, so that the battery leaks. If the leakage time is long enough, it may result in over-discharge (abbreviated as over-discharge) or even damage to the battery.

Disclosure of Invention

The application provides a leakage protection circuit and electronic equipment, can solve the problem of electronic equipment shutdown back battery leakage, extension battery life.

In a first aspect, an embodiment of the present application provides a leakage protection circuit, which is applied to an electronic device, where the electronic device includes a battery and a power utilization circuit, and the power utilization circuit includes: a first circuit including a first terminal for receiving a voltage signal and a second terminal, the second terminal being grounded through a low resistance circuit, the leakage protection circuit comprising: the first end of the switch is used for being connected with the negative pole ear of the battery, and the second end of the switch is used for being connected with the second end of the first circuit; the output end of the control circuit is connected with the control end of the switch; the control circuit is used for: when the voltage of the battery is lower than a preset first voltage threshold value, the switch is controlled to be turned off, and when the voltage of the battery is not lower than the preset first voltage threshold value, the switch is controlled to be turned on. When the voltage of the battery is lower than the first voltage threshold value, the control circuit controls the switch to be switched off, so that the battery is prevented from leaking electricity, the earth leakage protection of the battery is realized, the battery damage caused by the over-discharge of the battery can be prevented, and the service life of the battery is prolonged.

In a possible implementation manner, to realize that the first switch is controlled to be turned off when the voltage of the battery is lower than a preset first voltage threshold, and the first switch is controlled to be turned on when the voltage of the battery is not lower than the preset first voltage threshold, the control circuit is specifically configured to: when the electronic equipment is in a power-on state, the control switch conducts a path between the first end and the second end of the switch, and when the electronic equipment is in a power-off state, the control switch disconnects the path between the first end and the second end of the switch.

In one possible implementation, the switch includes: an NMOS tube and a PMOS tube; the source electrode of the NMOS tube is used as the first end of the switch, the drain electrode is used as the second end of the switch, and the grid electrode is connected with the drain electrode of the PMOS tube; the grid electrode of the PMOS tube is grounded, and the source electrode of the PMOS tube is connected with the output end of the control circuit.

In one possible implementation, the control circuit is specifically configured to: when the electronic equipment is in a power-on state, the electronic equipment outputs a high-level voltage signal, and when the electronic equipment is in a power-off state, the electronic equipment outputs a low-level voltage signal.

In one possible implementation, the control circuit includes: an LDO and a processor; wherein, the output end of the LDO is used as the output end of the control circuit; the enable end of the LDO is connected with the processor; the input end of the LDO is used for receiving a high-level voltage signal; the processor is configured to: when the electronic equipment is in a starting state, the LDO is controlled to work, and when the electronic equipment is in a shutdown state, the LDO is controlled to stop working.

In one possible implementation, a first terminal of the switch is used for connecting a negative tab of a battery, and the switch includes: the first end of the switch is connected with the negative pole ear of the battery through the battery protection board.

In a possible implementation manner, the gate of the NMOS transistor is connected to the drain of the PMOS transistor, and the method includes: the grid electrode of the NMOS tube is connected with the drain electrode of the PMOS tube through a first resistor.

In one possible implementation, the leakage protection circuit further includes: and the grid electrode of the NMOS tube is connected with the source electrode of the NMOS tube through a second resistor.

In one possible implementation, the leakage protection circuit further includes: the grid electrode of the NMOS tube is connected with the source electrode of the NMOS tube through a bidirectional voltage stabilizing diode.

In one possible implementation, the leakage protection circuit further includes: the grid electrode of the PMOS tube is connected with the source electrode of the PMOS tube through the bidirectional voltage stabilizing diode.

In one possible implementation, the switch includes: NMOS transistor, PMOS transistor or switch chip.

In one possible implementation, the first circuit is a battery power acquisition circuit, and the battery power acquisition circuit is configured to sample power of the battery through a first end and a second end of the battery power acquisition circuit.

In one possible implementation, the low resistance circuit includes: a zener diode, or a low resistance resistor.

In a second aspect, an embodiment of the present application provides an electronic device, including: the electronic equipment includes battery and power consumption circuit, and the power consumption circuit includes: the first circuit comprises a first end and a second end for receiving a voltage signal, and the second end is grounded through a low-resistance circuit; the electronic device further includes: a leakage protection circuit according to any of claims 1 to 3.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1A is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 1B is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a principle of battery leakage in an electronic device according to an embodiment of the present disclosure;

fig. 3A is a schematic structural diagram of an over-discharge protection circuit according to an embodiment of the present disclosure;

FIG. 3B is a schematic diagram illustrating an over-discharge protection principle of the over-discharge protection circuit shown in FIG. 3A according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an implementation of an over-discharge protection circuit according to an embodiment of the present application;

fig. 5 is another schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 6 is another schematic diagram of battery leakage in an electronic device according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a leakage protection circuit according to an embodiment of the present disclosure;

fig. 8A and 8B are schematic diagrams illustrating the operation of the leakage protection circuit shown in fig. 7 according to the present application;

fig. 9 is a schematic structural diagram of another leakage protection circuit according to an embodiment of the present application.

FIG. 10 is a schematic diagram illustrating the NMOS transistor of the earth leakage protection circuit shown in FIG. 9 of the present application being completely turned off;

fig. 11 is a schematic structural diagram of a leakage protection circuit according to an embodiment of the present application.

Detailed Description

The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

The electronic device referred to in the embodiments of the present application may be a mobile terminal, a terminal device, a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a User terminal, a wireless communication device, a User agent, or a User Equipment. The electronic device may be a Station (ST) in a WLAN, and may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA) device, a handheld device with Wireless communication capability, a computing device or other processing device connected to a Wireless modem, a vehicle-mounted device, a vehicle networking terminal, a computer, a laptop, a handheld communication device, a handheld computing device, a satellite Wireless device, a Wireless modem card, a Set Top Box (STB), a Customer Premises Equipment (CPE), and/or other devices for communicating over a Wireless system, as well as a next generation communication system, such as a Mobile terminal in a 5G Network or a future evolved Public Land Mobile Network (Public Land Mobile Network, PLMN) mobile terminals in the network, etc. The electronic device 10 may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is the general term of applying wearable technique to carry out intelligent design, develop the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch, dress and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable intelligent device has the advantages that the generalized wearable intelligent device is complete in function and large in size, can realize complete or partial functions without depending on a smart phone, such as a smart watch or smart glasses, and only is concentrated on a certain application function, and needs to be matched with other devices such as the smart phone for use, such as various smart bracelets for monitoring physical signs, smart jewelry and the like.

As shown in fig. 1A, a schematic structural diagram of an electronic device provided in an embodiment of the present application includes: a processor 110, a memory 120, a Universal Serial Bus (USB) interface 130, a charge management module 131, a power management module 140, a battery 150, and the like.

Optionally, in order to further improve the functions of the electronic device, the electronic device may further include: the antenna, the mobile communication module, the wireless communication module, the audio module, the speaker, the receiver, the microphone, earphone interface etc. this application embodiment does not limit.

Processor 110 may include one or more processing units, such as: the processor 110 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate devices or may be integrated into one or more processors.

The controller can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of instruction fetching and instruction execution.

A memory may also be provided in processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 110. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Avoiding repeated accesses reduces the latency of the processor 110, thereby increasing the efficiency of the system.

The memory 120 may be used to store computer-executable program code, which includes instructions. The memory 120 may include a program storage area and a data storage area. The storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required by at least one function, and the like. The storage data area may store data (such as audio data, phone book, etc.) created during use of the electronic device 100, and the like. Further, the memory 120 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (UFS), and the like. The processor 110 executes various functional applications of the electronic device 100 and data processing by executing instructions stored in the memory 120 and/or instructions stored in a memory provided in the processor.

The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge the electronic device 100, and may also be used to transmit data between the electronic device 100 and a peripheral device. And the earphone can also be used for connecting an earphone and playing audio through the earphone. The interface may also be used to connect other electronic devices, such as AR devices and the like.

The charging management module 131 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 131 may receive charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 131 may receive a wireless charging input through a wireless charging coil of the electronic device 100. The charging management module 131 may charge the battery 150 and supply power to the electronic device through the power management module 140.

The power management module 140 is used to connect the battery 150, the charging management module 131 and the processor 110. The power management module 140 receives input from the battery 150 and/or the charge management module 131 to power the processor 110, the memory 120, and the like. The power management module 140 may also be used to monitor parameters such as battery capacity, battery cycle count, battery state of health (leakage, impedance), etc. In some other embodiments, the power management module 140 may also be disposed in the processor 110. In other embodiments, the power management module 140 and the charging management module 131 may be disposed in the same device.

In an electronic apparatus such as that shown in fig. 1A, a battery protection plate is generally provided for a battery in the electronic apparatus in order to protect the battery. As shown in fig. 1B, taking the battery as an example including two tabs, namely a positive tab B + and a negative tab B-, the N + pin and the N-pin of the battery protection plate are respectively and correspondingly connected to the positive tab B + and the negative tab B-; the P + pin and the P-pin of the battery protection board are respectively used as the positive pole and the negative pole of the battery protection board and connected with an electric circuit of the electronic equipment, so that the battery can provide electric energy for the electric circuit through the P + pin and the P-pin of the battery protection board. The power utilization circuit herein includes circuits that require power utilization in the electronic device, such as the processor 110, the memory 120, the charging management module 131, the power management module 140, and the like shown in fig. 1A.

After the electronic device is turned off, the power circuit in the electronic device still exists as an impedance, which may be equivalent to a ground resistor R as shown in fig. 2, so that a power path as shown in fig. 2 is formed between the positive and negative electrode ears of the battery, resulting in leakage of the battery. If the leakage time is long enough, it may cause over-discharge of the battery, which may easily cause damage to the battery.

In order to solve the problem of over-discharge of the battery caused by electric leakage after the electronic equipment is shut down, an over-discharge protection circuit aiming at the battery can be arranged in the battery protection board.

As shown in fig. 3A, the over-discharge protection circuit includes: a switch K1 is provided between the N-pin of the battery protection board and the P-pin of the battery protection board, and a control circuit 1 is provided for the switch K1 in the battery protection board; the control circuit 1 is configured to: after the electronic device is turned off, when the voltage of the battery is not less than the preset over-discharge voltage threshold (e.g., 2.4V), the switch K1 is controlled to be turned on, and when the voltage of the battery is less than the preset over-discharge voltage threshold (e.g., 2.4V), the switch K1 is controlled to be turned off. Therefore, as shown in fig. 3B, when the electronic device is turned off, after the voltage of the battery decreases to the over-discharge voltage threshold, the switch K1 is turned off, so as to disconnect the path between the battery and the power utilization circuit, so as to achieve the purpose of preventing the battery from continuing to supply power to the power utilization circuit through the path, that is, to achieve the purpose of preventing the battery from continuing to leak power, thereby achieving the over-discharge protection of the battery.

In one embodiment, as shown in fig. 4, the connection relationship of the over-discharge protection circuit is as follows:

the S1 pin of the switch K1 is connected with the N-pin of the battery protection board through a resistor R14, the S2 pin is connected with the P-pin of the battery protection board, the G1 pin is connected with the DO pin of the control chip 51, and the G2 pin is connected with the CO pin of the control chip 51;

the VDD pin of the control chip 51 is connected with the N + pin of the battery protection board through a resistor R11 and is grounded through a capacitor C1; the VSS pin is grounded; the CS pin is grounded through a capacitor C2 and is also connected with the ungrounded end of the resistor R14 through a resistor R12; the V-pin is connected with the S2 pin of the switch K1 through a resistor R13, and a capacitor C3 is connected between the S1 pin and the S2 pin in series.

The resistor R11 in the circuit plays a buffering role, and the capacitors C1-C3 play a filtering role.

The operation principle of the over-discharge protection circuit shown in fig. 5 is described as follows, taking the circuit conduction between the S1 pin and the S2 pin when the switch K1 receives a voltage signal with a high level at both the G1 pin and the G2 pin as an example:

when the battery normally operates (i.e. various protection functions in the battery protection board are not triggered, for example, the battery normally supplies power, or charges and discharges, etc.), the DO pin and the CO pin of the control chip 51 may output high-level voltage signals, respectively, to control the circuit conduction between the S1 pin and the S2 pin in the switch K1, so that the battery may normally supply power to the power utilization circuit through the battery protection board;

the VDD pin is connected with an N + pin of the battery protection board through a resistor R11, the N + pin of the battery protection board is connected with a positive electrode ear B + of the battery, so that the voltage received by the VDD pin can reflect the voltage of the positive electrode ear B + of the battery, when the voltage received by the VDD pin is lower than a preset over-discharge voltage threshold (for example, 2.4V), the DO pin is converted from a voltage signal which outputs a high level to a voltage signal which outputs a low level to a G1 pin, so that a circuit between the S1 pin and the S2 pin in the switch K1 is disconnected, a path between the battery and a power utilization circuit is disconnected, the battery stops supplying power for the power utilization circuit, and over-discharge protection of the battery is realized; when the voltage received by the VDD pin is not lower than the over-discharge voltage threshold (for example, 2.4V), the DO pin is converted from outputting a low-level voltage signal to outputting a high-level voltage signal to the G1 pin, so that the circuit between the S1 pin and the S2 pin in the switch K1 is conducted, the battery supplies power to the power utilization circuit, and the over-discharge protection of the battery is released.

It should be noted that, the over-discharge protection circuit can also implement over-current/short-circuit protection and over-temperature protection, specifically:

the V-pin is connected with the S2 pin of the switch K1 through a resistor R13, so that a branch formed by the resistor R14 and the switch K1 between the N-pin and the P-pin in the battery circuit board can be subjected to current detection, when the detected current exceeds a preset current threshold value, the DO pin is converted into a voltage signal of a low level to be output to the G1 pin, a circuit between the S1 pin and the S2 pin in the switch K1 is disconnected, and the battery stops supplying power for an electric circuit, so that overcurrent/short-circuit protection is realized; when the detected current does not exceed the preset current threshold, the DO pin is converted into a voltage signal of high level to be output to the G1 pin, so that the circuit between the S1 pin and the S2 pin in the switch K1 is conducted, the battery supplies power to the electric circuit, and the overcurrent/short circuit protection is released.

The CS pin is connected with the ungrounded end of the resistor R4 through a resistor R12, the resistor R14 can be a positive temperature coefficient thermistor, the CS pin samples the voltage at two ends of the resistor R14 in a current detection mode, and when the current is detected to exceed a preset current threshold value, the DO pin is converted into a voltage signal which outputs a low level to the G1 pin, so that a circuit between the S1 pin and the S2 pin in the switch K1 is disconnected, the battery stops supplying power for an electric circuit, and overheating protection is realized; when the detected current does not exceed the preset current threshold, the DO pin is converted into a high-level voltage signal to be output to the G1 pin, so that a circuit between the S1 pin and the S2 pin in the switch K1 is conducted, the battery supplies power to the electric circuit, and the overheat protection is released.

In the above case, the pin outputting the low-level voltage signal may be replaced with a CO pin, and the protection against the leakage, overcurrent/short circuit, overheat, and the like may be similarly implemented.

Although the battery protection board provides the above-mentioned overdischarge protection circuit, the electronic device may still have a problem in that the battery leaks electricity, and the battery is damaged due to overdischarge of the battery.

Through analysis, as shown in fig. 5, a Current-sense input signal (SNS) _ P1 pin and an SNS _ N1 pin are further disposed on the battery protection board, the SNS _ P1 pin may be connected to the N + pin of the battery protection board through a resistor Ra, and the SNS _ N1 pin may be connected to the N-pin of the battery protection board through a resistor Rb. Resistors Ra and Rb act as buffers to reduce the current in the circuit.

As shown in fig. 5, the SNS _ P1 pin and the SNS _ N1 pin disposed on the battery protection board may be correspondingly connected to the first end a1 and the second end a2 of the battery power acquisition circuit outside the battery protection board to support the battery power acquisition circuit to acquire the battery power, the power information acquired by the battery power acquisition circuit may be sent to a processor of the electronic device, and the processor may prompt the battery power to a user according to the power information, control the charging and discharging of the battery, and so on. In the battery power collecting circuit, a low-resistance circuit connected to ground is disposed at the second end a2, for example, in fig. 5, the low-resistance circuit includes a zener diode D, and the zener diode D is used for performing voltage stabilization processing on the battery power collecting circuit. The low-resistance circuit refers to a circuit in which the equivalent resistance of the circuit is smaller than a preset resistance threshold, and includes, for example, a zener diode, or a low-resistance resistor, and the like. The specific value of the resistance threshold is not limited in the embodiments of the present application, and may be, for example, 1M ohm. The voltage stabilizing diode is also called a voltage stabilizing tube, and the voltage stabilizing diode and the low-resistance resistor are not limited in types under the condition that the required functions of the circuit of the embodiment of the application are met.

Based on the foregoing description, the power utilization circuit of the electronic device can still be equivalent to the resistor R connected to the ground, and in this case, the equivalent circuit of the circuit shown in fig. 5 is shown in fig. 6, for example. For convenience of illustration, the battery power acquisition circuit in the power utilization circuit is retained in fig. 6.

Referring to fig. 6, the electronic device has a path from the positive tab B + of the battery, through the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power utilization circuit, the zener diode D, the SNS _ N1 pin of the battery protection board, the resistor Rb to the N-pin of the battery protection board, and then to the negative tab B-of the battery, which discharges the battery when the electronic device is turned off, and even if the switch K1 of the battery protection board is turned off, the path still exists and discharges the battery, so that the battery protection board has the over-discharge protection function shown in the above embodiment, the battery leakage still occurs, and the battery is damaged due to the over-discharge of the battery.

Therefore, the embodiment of the present application further provides a leakage protection circuit, which can solve the problem of battery leakage caused under the conditions shown in fig. 5 and fig. 6, prevent the battery from being damaged due to over-discharge of the battery, and prolong the service life of the battery.

Fig. 7 is a schematic structural diagram of an embodiment of the leakage protection circuit of the present application. An earth leakage protection circuit is added to the circuit configuration of the electronic device shown in fig. 5, and the earth leakage protection circuit includes: a switch K2, and a control circuit 2, wherein,

the first end of the switch K2 is connected with the SNS _ N1 pin of the battery protection board, and the second end is connected with the second end A2 of the battery power acquisition circuit;

the output end of the control circuit 2 is connected with the control end of the switch K2, and the control circuit 2 is used for: when the voltage of the battery is lower than the first voltage threshold, the switch K2 is controlled to be turned off, and when the voltage of the battery is not lower than the preset first voltage threshold, the switch K2 is controlled to be turned on.

Alternatively, the first voltage threshold may be the same as the overdischarge voltage threshold in the aforementioned overdischarge protection circuit.

The operating principle of the circuit shown in fig. 7 is explained below:

based on the foregoing description, the power utilization circuit of the electronic device in fig. 7 is still equivalent to the resistance R connected to ground, and at this time, the equivalent circuit of the circuit shown in fig. 7 is shown in fig. 8A and 8B, for example. It should be noted that, for convenience of description, the equivalent circuit shown in fig. 8A and 8B retains the battery charge amount acquisition circuit, the switch K2 and the control circuit 2. At this time, the process of the present invention,

referring to fig. 8A, when the voltage of the battery is not lower than the preset first voltage threshold, the control circuit 2 controls the switch K2 to be turned on, so that the SNS _ P1 pin and the SNS _ N1 pin of the battery protection board are correspondingly connected to the first end a1 and the second end a2 of the battery power collecting circuit, and the battery power collecting circuit can normally complete battery power collection.

Referring to fig. 8B, when the voltage of the battery is lower than the first voltage threshold, the control circuit 2 controls the switch K2 to turn off, and a path from the positive tab B + of the battery, the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power utilization circuit, the zener diode D, the SNS _ N1 pin of the battery protection board, and the resistor Rb to the N-pin of the battery protection board, and then to the negative tab B-of the battery is disconnected, so as to prevent the battery from continuing to supply power to the power utilization circuit through the path after the electronic device is turned off, that is, prevent the battery from leaking electricity, achieve the leakage protection of the battery, reduce the power consumption of the battery, prevent the battery from being damaged due to the excessive discharge of the battery, and prolong the service life of the battery.

In another embodiment provided by the present application, in order to prevent the battery from leaking electricity due to the aforementioned path from the positive tab B + of the battery, through the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power utilization circuit, the zener diode D, the SNS _ N1 pin of the battery protection board, the resistor Rb to the N-pin of the battery protection board, and then to the negative tab B-of the battery after the electronic device is turned off, the control circuit 2 in the circuit shown in fig. 7 may be specifically configured to: when the electronic device is in the on state, the control switch K2 is turned on, and when the electronic device is in the off state, the control switch K2 is turned off.

The operation principle of this embodiment will be described with reference to the equivalent circuits shown in fig. 8A and 8B as an example:

referring to fig. 8A, when the electronic device is in the power-on state, the control circuit 2 controls the switch K2 to be turned on, so that the SNS _ P1 pin and the SNS _ N1 pin of the battery protection board are correspondingly connected to the first end a1 and the second end a2 of the battery power collecting circuit, and the battery power collecting circuit can normally complete battery power collection.

Referring to fig. 8B, when the electronic device is in the shutdown state, the control circuit 2 controls the switch K2 to turn off, and the path from the positive tab B + of the battery, the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power utilization circuit, the zener diode D, the SNS _ N1 pin of the battery protection board, the resistor Rb to the N-pin of the battery protection board, and then to the negative tab B-of the battery is disconnected, so as to prevent the battery from continuing to supply power to the power utilization circuit through the path after the electronic device is shutdown, that is, prevent the battery from leaking electricity, achieve the leakage protection of the battery, reduce the power consumption of the battery, prevent the battery from being damaged due to the excessive discharge of the battery, and prolong the service life of the battery.

A specific circuit implementation structure of the switch K2 and the control circuit 2 of the leakage protection circuit according to this embodiment is exemplarily illustrated in fig. 9.

As shown in fig. 9, the switch K2 may include: an N-channel metal oxide semiconductor (NMOS) transistor Q1 and a P-channel metal oxide semiconductor (PMOS) transistor Q2, wherein,

a source S1 of the NMOS transistor Q1 is used as a first end of a switch K2 and is used for connecting an SNS _ N1 pin of a battery protection board, and a drain D1 is used as a second end of a switch K2 and is used for connecting a second end A2 of the battery power acquisition circuit;

the gate G1 of the NMOS transistor Q1 is connected with the drain D2 of the PMOS transistor Q2, the gate G2 of the PMOS transistor Q2 is grounded, and the source S2 is used as the control end of the switch K2 and is connected with the control circuit 2.

Optionally, in order to prevent the insulating layer between the gate and the source of the NMOS transistor Q1 from being broken down by voltage, as shown in fig. 9, the switch K2 may further include: the gate and source of the NMOS transistor Q1 are connected through a diac D12.

Optionally, in order to prevent the insulating layer between the gate and the source of the PMOS transistor Q2 from being broken down by voltage, as shown in fig. 9, the switch K2 may further include: the gate and source of the PMOS transistor Q2 are connected through a diac D22.

In the circuit shown in fig. 9, the diode D11 connected between the source and the drain of the NMOS transistor Q1 is a body diode of the NMOS transistor Q1.

In the circuit shown in fig. 9, the diode D21 connected between the source and the drain of the PMOS transistor Q2 is a body diode of the PMOS transistor Q2.

Optionally, as shown in fig. 9, a first resistor R1 may be connected in series between the drain of the PMOS transistor Q2 and the gate of the NMOS transistor Q1, and the first resistor R1 plays a role of buffering to reduce the current of the circuit in which the first resistor R1 is located, so as to protect the NMOS transistor Q1.

Alternatively, as shown in fig. 9, a second resistor R2 may be connected in series between the gate and the source of the NMOS transistor Q1, and the second resistor R2 is used to prevent the NMOS transistor Q1 from being turned on by mistake, so as to achieve reliable turn-off of the NMOS transistor Q1 when the NMOS transistor Q1 is turned off.

As shown in fig. 9, the control circuit 2 may include: a low dropout regulator (LDO) and a processor, wherein,

the first end of the LDO is used for being connected with a first voltage end. The first voltage terminal may be a P + pin of the battery protection board, or may be any circuit node of the electronic device where the voltage is a system voltage.

The output end of the LDO is connected with the control end of the switch K2. In the circuit shown in fig. 9, the output terminal of the LDO may be specifically connected to the source of the PMOS transistor Q2.

And the enable end EN of the LDO is connected with the processor.

The processor is used for outputting a first enabling signal to the LDO when the electronic equipment is in a starting state, the first enabling signal is used for controlling the LDO to work, and when the electronic equipment is in a shutdown state, the processor outputs a second enabling signal to the LDO, and the second enabling signal is used for controlling the LDO not to work.

When the LDO works, the output end of the LDO outputs a high-level voltage signal; when the LDO does not work, a low-level voltage signal is output.

It should be noted that the LDO may be a newly added device, or may be any LDO that meets the above conditions and is already in a circuit of an electronic device, and the embodiment of the present application is not limited.

The operation of the circuit is described below with reference to table 1 below:

demand scenarios	VG2	VS2	Q2	VG1	Q1
						The NMOS transistor Q1 is turned on in the power-on state	Low level-main board gnd	High level	Conduction of	High level	Conduction of
In the power-off state, the NMOS tube Q1 is turned off	Low level-main board gnd	Low level-main board gnd	Switch off	High resistance	Switch off

TABLE 1

When the electronic device is in a power-on state, the processor controls the LDO to work, the LDO outputs a high-level voltage signal, the source S2 of the PMOS tube Q2 is at a high level, the grid G2 is at a low level, and the PMOS tube Q2 is switched on; the voltage of the drain D2 of the PMOS transistor Q2 is similar to the voltage of the source S2, so the drain D2 of the PMOS transistor Q2 is at a high level, i.e., the gate S1 of the NMOS transistor Q1 is at a high level; the source S1 of the NMOS tube Q1 is at a low level, and the NMOS tube Q1 is conducted, so that the SNS _ P1 pin and SNS _ N1 of the battery protection board are correspondingly connected with the first end A1 and the second end A2 of the battery electric quantity acquisition circuit, and the battery electric quantity acquisition circuit can normally finish battery electric quantity acquisition;

when the electronic device is in a shutdown state, the processor controls the LDO to be out of operation, the LDO outputs a low-level voltage signal, the source S2 of the PMOS transistor Q2 is at a low level, the gate G2 is at a low level, and the PMOS transistor Q2 is turned off; the PMOS transistor Q2 is in a high impedance state, and therefore, the drain D2 of the PMOS transistor Q2 is low, i.e., the gate S1 of the NMOS transistor Q1 is low; the source S1 of the NMOS tube Q1 is at a low level, the NMOS tube Q1 is turned off, so that the SNS _ N1 of the battery protection board is disconnected from the second end A2 of the battery electric quantity acquisition circuit, and a path from the positive lug B + of the battery, the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power utilization circuit, the voltage stabilizing diode D, the SNS _ N1 pin of the battery protection board, the resistor Rb to the N-pin of the battery protection board and then to the negative lug B-of the battery is disconnected, so that the battery is prevented from continuously supplying power to the power utilization circuit through the path after the electronic equipment is turned off, the battery leakage is also prevented, the electric leakage protection of the battery is realized, the electric quantity consumption of the battery is reduced, the battery damage caused by the over-discharge of the battery can be prevented, and the service life of the battery is prolonged.

It should be noted that, in the embodiment shown in fig. 9, the NMOS transistor Q1 is completely turned off in the shutdown state of the electronic device, so as to ensure the leakage protection effect of the leakage protection circuit. The specific principle that the NMOS transistor Q1 is completely turned off in the power-off state of the electronic device is described as follows:

as shown in fig. 10, since other power consuming circuits besides the switch K2 are also included in the electronic device, the other power consuming circuits may be equivalent to: the P + pin of the battery protection board is grounded through a third resistor R3, and the control end of the switch K2 is grounded through a fourth resistor R4; based on the circuit configuration shown in fig. 10, when the electronic device is in the power-off state, the processor controls the LDO to be not operated, the LDO outputs a low-level voltage signal, and the source S2 of the PMOS transistor Q2 is at a low level, and the gate G2 is at a low level, but due to the presence of the third resistor R3 and the fourth resistor R4, the potential of the source S2 of the PMOS transistor Q2 is lower than the potential of the gate G2, and the gate G2 of the PMOS transistor Q2 is grounded to GND, so the potential of the source S2 of the PMOS transistor Q2 is lower than the potential of GND; further, the potential of the drain D2 of the PMOS transistor Q2 is lower than the potential of GND, that is, the potential of the gate G1 of the NMOS transistor Q1 is lower than the potential of GND, so that the voltage between the gate G1 and the source S1 of the NMOS transistor Q1 is negative, and the NMOS transistor Q1 is completely turned off.

Under the condition that the NMOS tube Q1 is completely turned off, the circuit from the positive lug B + of the battery, the N + pin and the P + pin of the battery protection board, the equivalent resistor R of the power circuit, the voltage stabilizing diode D, the SNS _ N1 pin of the battery protection board, the resistor Rb to the N-pin of the battery protection board and then to the negative lug B-of the battery can be completely disconnected, so that the battery can be well prevented from electric leakage, the battery is prevented from being damaged due to over-discharge of the battery, and the service life of the battery is prolonged.

The control circuit 2 functions as: when the electronic device is in the power-on state, the high-level voltage signal is output to control the PMOS transistor Q2 to turn on, and then control the NMOS transistor Q1 to turn on, and when the electronic device is in the power-off state, the low-level voltage signal is output to control the PMOS transistor Q2 to turn off, and then control the NMOS transistor Q1 to turn off, so that, in another embodiment provided by the present application, the control circuit 2 may include: any device pin in the electronic equipment that meets the above conditions.

In another embodiment provided by the present application, the switch K2 in the circuit shown in fig. 7 may be implemented by an NMOS transistor, a PMOS transistor, or a switch chip, and the control circuit 2 may multiplex the control circuit 1 to implement control over the switch K2. For example, as shown in fig. 11, taking the switch K2 including the NMOS transistor Q3 as an example, at this time, the connection relationship of the NMOS transistor Q3 may refer to the connection relationship of the NMOS transistor Q1 in fig. 9, and only the gate of the NMOS transistor Q3 is connected to the voltage output terminal OUT of the control circuit 1. For example, if the control circuit 1 is implemented by the circuit configuration shown in fig. 4, the gate of the NMOS transistor Q3 may be connected to the DO pin or the CO pin of the control chip 51.

Because the voltage of the voltage signal output by the control circuit 1 is the voltage of the battery cathode ear when the voltage signal is at low level, the voltage difference between the grid electrode and the source electrode of the NMOS pipe Q3 is 0, so that the NMOS pipe Q3 can be ensured to be completely turned off, the battery leakage can be well prevented, the battery damage caused by the over discharge of the battery can be further prevented, and the service life of the battery can be prolonged.

It should be noted that the battery power level acquiring circuit in the embodiment of the present application may be extended to any circuit that is connected to the SNS _ P1 pin and the SNS _ N1 pin disposed on the battery protection board through the first terminal and the second terminal and acquires a voltage signal from the SNS _ P1 pin and the SNS _ N1 pin disposed on the battery protection board, and the embodiment of the present application is not limited thereto.

It should be noted that, the above-mentioned division rule of the high level and the low level of the voltage signal is not specifically limited in this embodiment, and in a possible implementation manner, the amplitude of the voltage signal is the high level when the amplitude is greater than or equal to 2.4V, and is the low level when the amplitude is less than 2.4V.

The application also provides an electronic device, including battery, battery protection shield and with the electric circuit, include with the electric circuit: the battery electric quantity acquisition circuit further comprises the leakage protection circuit shown in any one of the embodiments.

The above description is only for the specific embodiments of the present application, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A leakage protection circuit is applied to an electronic device, the electronic device comprises a battery and a power utilization circuit, and the power utilization circuit comprises: a first circuit including a first terminal for receiving a voltage signal and a second terminal, the second terminal being coupled to ground through a low resistance circuit, the leakage protection circuit comprising: a switch and a control circuit, wherein,

the first end of the switch is used for being connected with the negative pole ear of the battery, and the second end of the switch is used for being connected with the second end of the first circuit;

the output end of the control circuit is connected with the control end of the switch;

the control circuit is configured to: and when the voltage of the battery is not lower than the preset first voltage threshold, controlling the switch to be switched on.

2. The circuit according to claim 1, wherein to control the switch to turn off when the voltage of the battery is lower than a preset first voltage threshold, and to control the switch to turn on when the voltage of the battery is not lower than the preset first voltage threshold, the control circuit is specifically configured to:

when the electronic equipment is in a power-on state, the switch is controlled to conduct a path between the first end and the second end of the switch, and when the electronic equipment is in a power-off state, the switch is controlled to disconnect the path between the first end and the second end of the switch.

3. The circuit of claim 2, wherein the switch comprises: an NMOS tube and a PMOS tube; wherein the content of the first and second substances,

the source electrode of the NMOS tube is used as the first end of the switch, the drain electrode of the NMOS tube is used as the second end of the switch, and the grid electrode of the NMOS tube is connected with the drain electrode of the PMOS tube;

and the grid electrode of the PMOS tube is grounded, and the source electrode of the PMOS tube is connected with the output end of the control circuit.

4. The circuit of claim 3, wherein the control circuit is specifically configured to: when the electronic equipment is in a power-on state, the electronic equipment outputs a high-level voltage signal, and when the electronic equipment is in a power-off state, the electronic equipment outputs a low-level voltage signal.

5. The circuit of claim 4, wherein the control circuit comprises: an LDO and a processor; wherein the content of the first and second substances,

the output end of the LDO is used as the output end of the control circuit; the enable end of the LDO is connected with the processor; the input end of the LDO is used for receiving a high-level voltage signal;

the processor is configured to: when the electronic equipment is in a starting state, the LDO is controlled to work, and when the electronic equipment is in a shutdown state, the LDO is controlled to stop working.

6. The circuit of any of claims 1 to 5, wherein the first terminal of the switch is configured to connect to a negative terminal of the battery, comprising:

the first end of the switch is connected with the negative pole lug of the battery through a battery protection plate.

7. The circuit of any one of claims 3 to 5, wherein the gate of the NMOS transistor is connected to the drain of the PMOS transistor, and the NMOS transistor comprises:

and the grid electrode of the NMOS tube is connected with the drain electrode of the PMOS tube through a first resistor.

8. The circuit of any of claims 3 to 5, wherein the leakage protection circuit further comprises:

and the grid electrode of the NMOS tube is connected with the source electrode of the NMOS tube through a second resistor.

9. The circuit of any of claims 3 to 5, wherein the leakage protection circuit further comprises:

and the grid electrode of the NMOS tube is connected with the source electrode of the NMOS tube through a bidirectional voltage stabilizing diode.

10. The circuit of any of claims 3 to 5, wherein the leakage protection circuit further comprises:

and the grid electrode of the PMOS tube is connected with the source electrode of the PMOS tube through a bidirectional voltage stabilizing diode.

11. The circuit of claim 1, wherein the switch comprises: NMOS transistor, PMOS transistor or switch chip.

12. The circuit of any one of claims 1 to 5, wherein the first circuit is a battery charge collection circuit configured to sample the charge of the battery via first and second terminals of the battery charge collection circuit.

13. The circuit according to any of claims 1 to 5, wherein the low resistance circuit comprises: a zener diode, or a low resistance resistor.

14. An electronic device, comprising a battery and a power consuming circuit, the power consuming circuit comprising: a first circuit comprising a first terminal for receiving a voltage signal and a second terminal, the second terminal being connected to ground through a low resistance circuit; the electronic device further includes: a leakage protection circuit as claimed in any one of claims 1 to 13.