CN114335109A - Display panel and preparation method thereof - Google Patents
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- CN114335109A CN114335109A CN202111637489.XA CN202111637489A CN114335109A CN 114335109 A CN114335109 A CN 114335109A CN 202111637489 A CN202111637489 A CN 202111637489A CN 114335109 A CN114335109 A CN 114335109A
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Abstract
The application discloses display panel and preparation method thereof, and the display panel comprises: an array substrate; the anode is arranged on the array substrate; the auxiliary cathode is arranged on the same layer as the anode, and a gap is formed between the auxiliary cathode and the anode; a pixel defining layer disposed on the anode and the auxiliary cathode; the pixel defining layer is provided with a first opening at a position corresponding to the anode for exposing the anode; the pixel defining layer is provided with a second opening at the position corresponding to the auxiliary cathode for exposing the auxiliary cathode; a light emitting device disposed in the first opening; and a face cathode disposed on the light emitting device and connected to the auxiliary cathode through the second opening. This application auxiliary cathode and positive pole are with layer setting, and the face negative pole is connected to auxiliary cathode through the second opening, need not trompil on the flat layer to optimize auxiliary cathode hole's position, avoid the bad phenomenon of face negative pole and auxiliary cathode overlap joint, and then reduce the pressure drop effect.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
Organic light-emitting diode (OLED) display panels have the advantages of self-luminescence, high contrast, thin thickness, wide viewing angle, fast response speed, etc., and are representative of a new generation of flat panel display technology and are increasingly popular in the industry. Due to the self-resistance voltage division effect of the metal connecting wires inside the OLED display panel, power supply voltage Drop is generated when current passes through the internal power supply connecting wires, so that the current distribution of signals from the source end and the tail end is uneven, and the brightness of the panel is uneven, and the phenomenon is called as static resistance voltage Drop (IR Drop). In order to improve the defects, an auxiliary cathode is added during the design of the back plate so as to make the voltage distribution of the whole cathode uniform and achieve the display effect of uniform brightness.
As shown in fig. 1, the OLED display panel includes a substrate 11, a light-shielding layer 12, a buffer layer 13, a semiconductor layer 14, a gate insulating layer 15, a gate layer 16, a dielectric layer 17, a source-drain layer 18, a passivation layer 19, a PAD layer 20(PAD layer), a planarization layer 21, an anode 22, a pixel defining layer 23, and a surface cathode 25. The surface cathode 25 is prepared in the evaporation process, and the surface cathode 25 needs to be sequentially connected with the lower metal layer through the auxiliary cathode hole 10, i.e., the surface cathode 25 → the adapting layer 20 → the source/drain layer 18 → the light shielding layer 12, so as to realize the signal transmission of the cathode 25. Since the surface cathode 25 is electrically connected to the via layer 20, the source/drain electrode layer 18, and the light shielding layer 12 in sequence, it is equivalent to the same layer design of the surface cathode 25 and the via layer 20, the source/drain electrode layer 18, and the light shielding layer 12.
Referring to fig. 1, the light-shielding layer 12 is a trace uniformly distributed over the entire surface, and the auxiliary cathode holes 10 are uniformly formed in the panel, so as to ensure that the IR Drop (voltage Drop) phenomenon of the cathode 25 signal is improved to the greatest extent. However, in view of the actual manufacturing effect of the prior art, since the auxiliary cathode hole 10 needs to penetrate through the relatively thick planarization layer 21 and the pixel defining layer 23(bank), the pixel defining layer 23 is often left in the hole during the exposure and development processes, and thus the conduction between the via layer 20 and the cathode 25 is not allowed, and the IR Drop cannot be effectively improved.
Disclosure of Invention
The present invention is directed to a display panel and a method for manufacturing the same, so as to solve the technical problems that the via layer cannot be conducted with a cathode due to the position of an auxiliary cathode hole, and the voltage drop cannot be improved.
To achieve the above object, the present invention provides a display panel including: an array substrate; the anode is arranged on the array substrate; the auxiliary cathode is arranged on the same layer as the anode, and a gap is formed between the auxiliary cathode and the anode; a pixel defining layer disposed on the anode and the auxiliary cathode; the pixel defining layer is provided with a first opening at a position corresponding to the anode for exposing the anode; the pixel defining layer is provided with a second opening at a position corresponding to the auxiliary cathode for exposing the auxiliary cathode; the light-emitting device is arranged in the first opening; and a surface cathode disposed on the light emitting device and connected to the auxiliary cathode through the second opening.
Further, the first opening includes a red sub-pixel opening, a green sub-pixel opening, and a blue sub-pixel opening, the light emitting device includes a red light emitting device, a green light emitting device, and a blue light emitting device, and the red light emitting device, the green light emitting device, and the blue light emitting device are respectively disposed corresponding to the red sub-pixel opening, the green sub-pixel opening, and the blue sub-pixel opening.
Further, a gap width between the auxiliary cathode and the anode is 5 μm or more.
Further, the auxiliary cathode is circular, elliptical or polygonal in shape.
Further, the auxiliary cathode and the anode are made of at least one material selected from aluminum, molybdenum, copper, hafnium and tantalum.
Further, the array substrate includes: a substrate; a light shielding layer disposed on the substrate; the buffer layer covers the shading layer and extends to the surface of the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode layer disposed on the gate insulating layer; a dielectric layer covering the gate layer and the semiconductor layer and extending to the surface of the buffer layer; the source drain layer is arranged on the dielectric layer and comprises a drain electrode and a source electrode; the drain electrode is connected to one side of the semiconductor layer, and the source electrode is connected to the other side of the semiconductor layer and the light shielding layer at the same time; the passivation layer covers the source drain layer and extends to the surface of the dielectric layer; the switching layer is arranged on the passivation layer and connected to the source electrode; and the flat layer covers the switching layer and extends to the surface of the passivation layer.
Furthermore, the flat layer is provided with a third opening for exposing the switching layer; the anode is arranged on the flat layer and is connected to the switching layer through the third opening.
In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, including the steps of: forming an array substrate; forming a conductive layer on the array substrate; patterning the conductive layer to form an anode and an auxiliary cathode which are arranged on the same layer, wherein a gap exists between the auxiliary cathode and the anode; forming a pixel defining layer on the anode and the auxiliary cathode; a first opening and a second opening are formed in the pixel defining layer, and the first opening is used for exposing the anode; the second opening is used for exposing the auxiliary cathode; a light emitting device formed in the pixel defining layer, the light emitting device being located within the first opening; and forming a face cathode on the light emitting device, the face cathode filling the second opening and being connected to the auxiliary cathode.
Further, the forming of the array substrate includes: forming a light shielding layer on a substrate; forming a buffer layer on the light-shielding layer and extending to the upper surface of the substrate; forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer; forming a gate electrode layer on the gate insulating layer; forming a dielectric layer on the gate layer, wherein first via holes and second via holes are formed in the dielectric layer, the two first via holes are used for exposing two side positions of the semiconductor layer, and the second via holes are used for exposing part of the light shielding layer; forming a source drain layer on the dielectric layer and filling the first via hole and the second via hole, wherein the source drain layer comprises a drain electrode and a source electrode, the drain electrode is connected to the semiconductor layer through the first via hole, the source electrode is connected to the semiconductor layer through the first via hole, and the source electrode is connected to the light shielding layer through the second via hole; forming a passivation layer on the source drain layer and extending to the surface of the dielectric layer, wherein a third through hole is formed in the passivation layer and used for exposing the source electrode; forming a transfer layer in the third via hole and partially extending to the passivation layer; and forming a flat layer on the switching layer and extending to the surface of the passivation layer, wherein a third opening is formed in the flat layer and used for exposing the switching layer.
Further, the anode is formed on the flat layer and connected to the adapting layer through the third opening.
The invention has the technical effects that the auxiliary cathode and the anode are arranged at the same layer, the surface cathode is connected to the auxiliary cathode through the second opening, and holes do not need to be formed in the flat layer to optimize the position of the auxiliary cathode hole, so that the problem that a pixel definition layer is remained in the hole due to the fact that the hole in the flat layer is deeper can be avoided, the phenomenon that the surface cathode and the auxiliary cathode are not in good lap joint is avoided, and the voltage drop effect is further reduced.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional display panel.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 3 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.
Fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of the auxiliary cathode and the anode disposed on the same layer according to the embodiment of the present disclosure.
The components of the drawings are identified as follows:
11. a substrate; 12. A light-shielding layer;
13. a buffer layer; 14. A semiconductor layer;
15. a gate insulating layer; 16. A gate layer;
17. a dielectric layer; 18. A source drain layer;
18a, a source electrode; 18b, a drain electrode;
19. a passivation layer; 20. A transfer layer;
21. a planarization layer; 22. An anode;
22a, an auxiliary cathode; 23. A pixel defining layer;
24. a light emitting device; 25. A cathode;
10. an auxiliary cathode hole; 31. A first via hole;
32. a second via hole; 33. A third via hole;
41. a first opening; 42. A second opening;
43. a third opening.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In the description of the present application, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be considered as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
As shown in fig. 2, the present embodiment provides a display panel including an array substrate 11, an anode 22, an auxiliary cathode 22a, a pixel defining layer 23, a light emitting device 24, and a surface cathode 25.
The array substrate 11 includes a substrate 11, a light-shielding layer 12, a buffer layer 13, a semiconductor layer 14, a gate insulating layer 15, a gate layer 16, a dielectric layer 17, a source/drain layer 18, a passivation layer 19, an interposer layer 20, and a planarization layer 21.
The substrate 11 is glass, functional glass (sensor glass), or a flexible substrate. The functional glass is obtained by sputtering a transparent metal oxide conductive film coating on the ultrathin glass and carrying out high-temperature annealing treatment. The transparent metal oxide may be any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The flexible substrate is made of a polymer material, and specifically, the flexible substrate may be made of Polyimide (PI), Polyethylene (PE), Polypropylene (PP), Polystyrene (PS), Polyethylene terephthalate (PET), or Polyethylene naphthalate (PEN). The polymer material has good flexibility, light weight and impact resistance, and is suitable for flexible display panels. Among them, polyimide can also achieve good heat resistance and stability.
The light shielding layer 12 is disposed on the substrate 11, the light shielding layer 12 is made of a metal material, and the metal material includes one or more of copper, molybdenum, aluminum, silver, nickel, and the like, so that the conductivity and the bending performance of the light shielding layer 12 are improved, and the risk of dynamic bending and wire breakage is reduced.
The buffer layer 13 covers the light-shielding layer 12 and extends to the surface of the substrate 11, and the material used for the buffer layer 13 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and amorphous silicon, and is mainly used for blocking water and oxygen and preventing the water and oxygen from eroding the array substrate 11.
The semiconductor layer 14 is provided on the buffer layer 13, and the semiconductor layer 14 may be made of indium tin oxide (IGZO). Semiconductor layer 14 may also include a carrier channel, which may be comprised of polysilicon, that is primarily used to improve fill factor, short circuit current, and open circuit voltage.
The gate insulating layer 15 is disposed on the semiconductor layer 14, and the material used for the gate insulating layer 15 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon.
The gate layer 16 is disposed on the gate insulating layer 15, and the gate layer 16 is made of a metal material including one or more of copper, molybdenum, aluminum, silver, and nickel, so that the conductivity and bending performance of the gate layer 16 are improved, and the risk of dynamic bending and wire breaking is reduced.
The dielectric layer 17 completely covers the gate layer 16 and the semiconductor layer 14, and extends to the upper surface of the buffer layer 13. The material used for the dielectric layer 17 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon. The dielectric layer 17 is formed with a first via hole 31 and a second via hole 32, the two first via holes 31 are used for exposing two side positions of the semiconductor layer 14, and the second via hole 32 is used for exposing a part of the light shielding layer 12.
The landing layer 20 is disposed on the passivation layer 19 and connected to the source electrode 18a through the third via 33. The material that switching layer 20 adopted is the metal material, and this metal material includes one or several kinds in copper, molybdenum, aluminium, silver etc. has promoted switching layer 20's conductivity and bending performance, has reduced the dynamic risk of buckling the broken string.
The planarization layer 21 covers the landing layer 20 and extends to the surface of the passivation layer 19. The material used for the planarization layer 21 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon. The planarization layer 21 has a third opening 43 for exposing the interposer 20.
The anode 22 is disposed on the planarization layer 21 and connected to the landing layer 20 through the third opening 43. The anode 22 extends from the sidewall of the third opening 43 to the bottom wall (i.e. the upper surface of the transition layer 20), and then extends from the bottom wall of the third opening 43 to the surface of the flat layer 21.
The auxiliary cathode 22a is disposed on the same layer as the anode 22, and a gap exists between the auxiliary cathode 22a and the anode 22.
The auxiliary cathode 22a and the anode 22 are a transparent metal oxide, a stack of a metal layer and a transparent metal oxide. The transparent metal oxide is made of any one of indium gallium zinc oxide, indium zinc tin oxide, indium gallium zinc tin oxide, indium zinc oxide, indium aluminum zinc oxide, indium gallium tin oxide or antimony tin oxide. The materials have good conductivity and transparency, and are small in thickness, so that the whole thickness of the display panel cannot be influenced. Meanwhile, the electronic radiation and ultraviolet and infrared light which are harmful to human bodies can be reduced. The metal layer is made of any one of silver (Ag), aluminum (Al) or copper (Cu). The metal such as silver, aluminum, copper and the like has good conductivity and low cost, and the production cost can be reduced while the conductivity of the auxiliary cathode 22a and the anode 22 is ensured.
Further, the gap width between the auxiliary cathode 22a and the anode 22 is 5 μm or more. Specifically, the gap width between the auxiliary cathode 22a and the anode 22 is 5 μm, 6 μm, and 7 μm. The gap width between the auxiliary cathode 22a and the anode 22 is set to 5 μm or more mainly for ensuring insulation between the anode 22 and the auxiliary cathode 22 a. The gap is provided to ensure the insulation between the anode 22 and the auxiliary cathode 22a, so that an additional insulating layer is not required, thereby saving materials and reducing cost. The specific gap width can be determined according to the requirements of the pixel aperture ratio and the size of the display panel. The shape of the plane of the auxiliary cathode 22a as viewed from above is circular, elliptical, or polygonal, and the polygon may be triangular, rectangular, square, pentagonal, hexagonal, or the like.
The pixel defining layer 23 is provided on the anode 22 and the auxiliary cathode 22 a. The pixel defining layer 23 has a first opening 41 formed at a position corresponding to the anode 22 for exposing the anode 22. The pixel defining layer 23 has a second opening 42 formed at a position corresponding to the auxiliary cathode 22a for exposing the auxiliary cathode 22 a. The material of the pixel defining layer 23 is selected from one or more of polyimide, polyethylene naphthalate, polyethylene terephthalate, Polycarbonate (PC), Polyetherimide (PEI), and Polyethersulfone (PES).
In this embodiment, the pixel defining layer 23 is used to isolate the auxiliary cathode 22a from the anode 22, so that the gap between the auxiliary cathode 22a and the anode 22 can be reduced under the condition of ensuring the insulation effect, the laying area of the anode 22 is larger, and the light emitting effect of the auxiliary cathode 22a on the light emitting device 24 is reduced.
The light emitting device 24 is disposed in the first opening 41, and the light emitting device 24 includes a hole injection layer, a light emitting layer, an electron transport layer, an electron injection layer, and other film layers. Wherein the first opening 41 comprises a red sub-pixel opening, a green sub-pixel opening and a blue sub-pixel opening, the light emitting device 24 comprises a red light emitting device 24, a green light emitting device 24 and a blue light emitting device 24, and the red light emitting device 24, the green light emitting device 24 and the blue light emitting device 24 are respectively arranged corresponding to the red sub-pixel opening, the green sub-pixel opening and the blue sub-pixel opening.
The face cathode 25 is provided on the light emitting device 24 and is connected to the auxiliary cathode 22a through the second opening 42. The surface cathode 25 may be made of any one or more of magnesium (Mg), silver, magnesium alloy, silver alloy, and transparent metal oxide, and the specific material is determined according to the requirements of the display panel. The material of the surface cathode 25 needs to be matched with the material of the auxiliary cathode 22a, so that the contact resistance between the surface cathode 25 and the auxiliary cathode 22a is appropriate.
Compared with the prior art, in the embodiment, the auxiliary cathode 22a and the anode 22 are disposed on the same layer, and the surface cathode 25 is connected to the auxiliary cathode 22a through the second opening 42, so that holes do not need to be formed in the flat layer 21, and the position of the hole (i.e., the second opening 42) of the auxiliary cathode 22a is optimized, thereby avoiding the problem that the pixel definition layer 23 remains in the hole due to the deeper hole formed in the flat layer 21, avoiding the phenomenon of poor overlapping of the surface cathode 25 and the auxiliary cathode 22a, and further reducing the voltage Drop (IR Drop) effect. In addition, the auxiliary cathode 22a and the anode 22 are disposed on the same layer, and the auxiliary cathode 22a and other signal traces are not on the same film layer, so as to reduce the risk of short circuit between metal lines. Other signal traces may be gate traces of the gate layer 16, data lines of the source-drain layer 18, VDD traces, and sensing (Sense) traces, and gaps (spaces) between other signal traces may also be reduced appropriately, so as to implement a higher resolution design.
The display panel provided in this embodiment further includes an encapsulation structure (not shown), which is formed by alternately stacking inorganic encapsulation layers, organic encapsulation layers, or both of them. The inorganic encapsulation layer may be selected from inorganic materials of alumina, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, zinc oxide, and the like. The organic encapsulation layer is an organic material selected from epoxy resin, polyimide, polyethylene terephthalate, Polycarbonate (PC), polyethylene, Polyacrylate (PEA), and the like.
As shown in fig. 3, the present embodiment further provides a method for manufacturing a display panel, including the following steps S1) -S6).
S1) to form an array substrate 11. The formation of the array substrate 11 includes S11) -S20), refer to fig. 4.
S11) forming the light-shielding layer 12 on a substrate 11, see fig. 5.
Specifically, a metal material is deposited on the substrate 11 to form the light-shielding layer 12. The metal material comprises one or more of copper, molybdenum, aluminum, silver, nickel and the like, so that the conductivity and the bending performance of the shading layer 12 are improved, and the risk of dynamic bending and wire breaking is reduced.
S12) forming a buffer layer 13 on the light-shielding layer 12 and extending to the upper surface of the substrate 11, as shown in fig. 5.
S13) forming a semiconductor layer 14 on the buffer layer 13, see fig. 5.
S14) forming a gate insulating layer 15 on the semiconductor layer 14, referring to fig. 5.
S15) forming a gate electrode layer 16 on the gate insulating layer 15, referring to fig. 5.
S16), forming a dielectric layer 17 on the gate layer 16, wherein the dielectric layer 17 is formed with first via holes 31 and second via holes 32, the two first via holes 31 are used to expose two side positions of the semiconductor layer 14, and the second via holes 32 are used to expose a portion of the light-shielding layer 12, as shown in fig. 5.
S17) forming a source drain layer 18 on the dielectric layer 17 and filling the first via hole 31 and the second via hole 32, where the source drain layer 18 includes a drain 18b and a source 18a, the drain 18b is connected to the semiconductor layer 14 through the first via hole 31, the source 18a is connected to the semiconductor layer 14 through the first via hole 31, and the source 18a is connected to the light shielding layer 12 through the second via hole 32, as shown in fig. 5.
S18), forming a passivation layer 19 on the source/drain layer 18 and extending to the surface of the dielectric layer 17, wherein the passivation layer 19 is formed with a third via hole 33 for exposing the source 18a, as shown in fig. 5.
S19) forming a transit layer 20 within the third via 33 and extending partially onto the passivation layer 19, see fig. 5.
S20) forming a planarization layer 21 on the landing layer 20 and extending to the surface of the passivation layer 19, wherein the planarization layer 21 is formed with a third opening 43 for exposing the landing layer 20, as shown in fig. 5.
S2) forming a conductive layer on the array substrate 11.
Specifically, a metal material is deposited on the planarization layer 21 to form a conductive layer.
S3) patterning the conductive layer to form an anode 22 and an auxiliary cathode 22a disposed in the same layer, wherein a gap exists between the auxiliary cathode 22a and the anode 22. Wherein the anode 22 is connected to the adapting layer 20 through the third opening 43, see fig. 6.
S4) forming a pixel defining layer 23 on the anode 22 and the auxiliary cathode 22 a; a first opening 41 and a second opening 42 are formed in the pixel defining layer 23, wherein the first opening 41 is used for exposing the anode 22; the second opening 42 is used to expose the auxiliary cathode 22a, see fig. 6.
S5) forming a light emitting device 24 in the pixel defining layer 23, the light emitting device 24 being located within the first opening 41, refer to fig. 2.
Specifically, the light emitting device 24 is disposed in the first opening 41, and the light emitting device 24 includes a hole injection layer, a light emitting layer, an electron transport layer, an electron injection layer, and other film layers. Wherein the first opening 41 comprises a red sub-pixel opening, a green sub-pixel opening and a blue sub-pixel opening, the light emitting device 24 comprises a red light emitting device 24, a green light emitting device 24 and a blue light emitting device 24, and the red light emitting device 24, the green light emitting device 24 and the blue light emitting device 24 are respectively arranged corresponding to the red sub-pixel opening, the green sub-pixel opening and the blue sub-pixel opening.
S6) forming a planar cathode 25 on the light emitting device 24, the planar cathode 25 filling the second opening 42 and being connected to the auxiliary cathode 22a, refer to fig. 2.
Compared with the prior art, in the embodiment, the auxiliary cathode 22a and the anode 22 are disposed on the same layer, and the surface cathode 25 is connected to the auxiliary cathode 22a through the second opening 42, so that holes do not need to be formed in the flat layer 21, and the position of the hole (i.e., the second opening 42) of the auxiliary cathode 22a is optimized, thereby avoiding the problem that the pixel definition layer 23 remains in the hole due to the deeper hole formed in the flat layer 21, avoiding the phenomenon of poor overlapping of the surface cathode 25 and the auxiliary cathode 22a, and further reducing the voltage Drop (IR Drop) effect. In addition, the auxiliary cathode 22a and the anode 22 are disposed on the same layer, and the auxiliary cathode 22a and other signal traces are not on the same film layer, so as to reduce the risk of short circuit between metal lines. Other signal traces may be gate traces of the gate layer 16, data lines of the source-drain layer 18, VDD traces, and sensing (Sense) traces, and gaps (spaces) between other signal traces may also be reduced appropriately, so as to implement a higher resolution design.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained by applying specific examples herein, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel, comprising:
an array substrate;
the anode is arranged on the array substrate;
the auxiliary cathode is arranged on the same layer as the anode, and a gap is formed between the auxiliary cathode and the anode;
a pixel defining layer disposed on the anode and the auxiliary cathode; the pixel defining layer is provided with a first opening at a position corresponding to the anode for exposing the anode; the pixel defining layer is provided with a second opening at a position corresponding to the auxiliary cathode for exposing the auxiliary cathode;
the light-emitting device is arranged in the first opening; and
and the surface cathode is arranged on the light-emitting device and is connected to the auxiliary cathode through the second opening.
2. The display panel according to claim 1,
the first opening comprises a red sub-pixel opening, a green sub-pixel opening and a blue sub-pixel opening, the light emitting device comprises a red light emitting device, a green light emitting device and a blue light emitting device, and the red light emitting device, the green light emitting device and the blue light emitting device are respectively arranged corresponding to the red sub-pixel opening, the green sub-pixel opening and the blue sub-pixel opening.
3. The display panel according to claim 1,
the gap width between the auxiliary cathode and the anode is 5 μm or more.
4. The display panel according to claim 1,
the auxiliary cathode is circular, elliptical or polygonal in shape.
5. The display panel according to claim 1,
the auxiliary cathode and the anode are made of at least one of aluminum, molybdenum, copper, hafnium and tantalum.
6. The display panel according to claim 1, wherein the array substrate comprises:
a substrate;
a light shielding layer disposed on the substrate;
the buffer layer covers the shading layer and extends to the surface of the substrate;
a semiconductor layer disposed on the buffer layer;
a gate insulating layer disposed on the semiconductor layer;
a gate electrode layer disposed on the gate insulating layer;
a dielectric layer covering the gate layer and the semiconductor layer and extending to the surface of the buffer layer;
the source drain layer is arranged on the dielectric layer and comprises a drain electrode and a source electrode; the drain electrode is connected to one side of the semiconductor layer, and the source electrode is connected to the other side of the semiconductor layer and the light shielding layer at the same time;
the passivation layer covers the source drain layer and extends to the surface of the dielectric layer;
the switching layer is arranged on the passivation layer and connected to the source electrode; and
and the flat layer covers the switching layer and extends to the surface of the passivation layer.
7. The display panel according to claim 6,
the flat layer is provided with a third opening for exposing the switching layer;
the anode is arranged on the flat layer and is connected to the switching layer through the third opening.
8. A preparation method of a display panel is characterized by comprising the following steps:
forming an array substrate;
forming a conductive layer on the array substrate;
patterning the conductive layer to form an anode and an auxiliary cathode which are arranged on the same layer, wherein a gap exists between the auxiliary cathode and the anode;
forming a pixel defining layer on the anode and the auxiliary cathode; a first opening and a second opening are formed in the pixel defining layer, and the first opening is used for exposing the anode; the second opening is used for exposing the auxiliary cathode;
a light emitting device formed in the pixel defining layer, the light emitting device being located within the first opening; and
forming a planar cathode on the light emitting device, the planar cathode filling the second opening and being connected to the auxiliary cathode.
9. The method for manufacturing a display panel according to claim 8, wherein the forming of the array substrate includes:
forming a light shielding layer on a substrate;
forming a buffer layer on the light-shielding layer and extending to the upper surface of the substrate;
forming a semiconductor layer on the buffer layer;
forming a gate insulating layer on the semiconductor layer;
forming a gate electrode layer on the gate insulating layer;
forming a dielectric layer on the gate layer, wherein first via holes and second via holes are formed in the dielectric layer, the two first via holes are used for exposing two side positions of the semiconductor layer, and the second via holes are used for exposing part of the light shielding layer;
forming a source drain layer on the dielectric layer and filling the first via hole and the second via hole, wherein the source drain layer comprises a drain electrode and a source electrode, the drain electrode is connected to the semiconductor layer through the first via hole, the source electrode is connected to the semiconductor layer through the first via hole, and the source electrode is connected to the light shielding layer through the second via hole;
forming a passivation layer on the source drain layer and extending to the surface of the dielectric layer, wherein a third through hole is formed in the passivation layer and used for exposing the source electrode;
forming a transfer layer in the third via hole and partially extending to the passivation layer;
and forming a flat layer on the switching layer and extending to the surface of the passivation layer, wherein a third opening is formed in the flat layer and used for exposing the switching layer.
10. The method for manufacturing a display panel according to claim 9,
the anode is formed on the flat layer and connected to the transition layer through the third opening.
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| CN202111637489.XA CN114335109A (en) | 2021-12-29 | 2021-12-29 | Display panel and preparation method thereof |
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| CN202111637489.XA CN114335109A (en) | 2021-12-29 | 2021-12-29 | Display panel and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115411216A (en) * | 2022-09-15 | 2022-11-29 | 惠科股份有限公司 | Display panel and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115411216A (en) * | 2022-09-15 | 2022-11-29 | 惠科股份有限公司 | Display panel and manufacturing method thereof |
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