CN114334994A - Three-dimensional memory, preparation method thereof, storage system and electronic equipment - Google Patents

Abstract

The application provides a three-dimensional memory, a preparation method of the three-dimensional memory, a storage system and electronic equipment. The preparation method of the three-dimensional memory comprises the following steps: alternately stacking barrier layers and stop layers to form a composite structure, wherein the stop layers comprise a first stop layer; alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a stacked structure; forming a first channel hole extending in a lamination direction of the laminated structure and a second channel hole penetrating the laminated structure and extending to the first stop layer; and etching the first channel hole to extend the first channel hole to the first stop layer.

Description

Three-dimensional memory, preparation method thereof, storage system and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory, a method for manufacturing the same, a memory system, and an electronic device.

Background

With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. However, in recent years, the development of planar flash memories has met various challenges, such as physical limitations and storage electron density limitations. Under the background, in order to solve the difficulties encountered by the flat flash memory, a three-dimensional memory developed in the longitudinal direction is developed. However, limited by practical fabrication processes, significant challenges are presented to the formation of channel structures such as different radial dimensions in three-dimensional memories.

Disclosure of Invention

The application provides a preparation method of a three-dimensional memory, which comprises the following steps: alternately stacking barrier layers and stop layers to form a composite structure, wherein the stop layers comprise a first stop layer; alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a stacked structure; forming a first channel hole extending in a lamination direction of the laminated structure and a second channel hole penetrating the laminated structure and extending to the first stop layer; and etching the first channel hole to extend the first channel hole to the first stop layer.

In one embodiment, the first channel hole has a pore diameter in the range of 95 to 120 angstroms; and the aperture of the second channel hole is in the range of 150-200 angstroms.

In one embodiment, etching the first channel hole to extend the first channel hole to the first stop layer includes: and covering the second channel hole, and etching the first channel hole to enable the first channel hole to extend to the first stop layer.

In one embodiment, the first stop layer is the stop layer furthest from the stack.

In one embodiment, the material of the barrier layer includes an oxide; and the stop layer comprises polysilicon.

In one embodiment, the material of the insulating layer includes an oxide; and the material of the sacrificial layer comprises nitride.

In one embodiment, the method further comprises: filling the first and second channel holes to form first and second channel structures, respectively.

In one embodiment, the method further comprises: and forming a grid line gap, and replacing the sacrificial layer into a grid layer through the grid line gap.

In one embodiment, the material of the gate layer includes metal tungsten.

Another aspect of the present application provides a three-dimensional memory, including: a composite structure comprising barrier layers and stop layers alternately stacked, wherein the stop layers comprise a first stop layer; a stacked structure on the composite structure and including alternately stacked insulating layers and gate layers; a first channel structure penetrating the stacked structure and extending to the first stop layer; and a second channel structure penetrating the stacked structure and extending to the first stop layer, wherein a radial dimension of the second channel structure is larger than a radial dimension of the first channel structure.

In one embodiment, the first channel structure has a radial dimension in the range of 95 to 120 angstroms; and the radial dimension of the second channel structure is in the range of 150-200 angstroms.

In one embodiment, the first stop layer is the stop layer furthest from the stack.

Another aspect of the present application provides a storage system. The storage system comprises a controller and the three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

Another aspect of the present application provides an electronic device including the above storage system.

In one embodiment, the electronic device includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

The three-dimensional memory and the preparation method thereof provided according to one or more embodiments of the present application may have at least one of the following advantages:

1) the composite structure formed by alternately stacking the barrier layers and the stop layers is arranged, so that the first channel holes and the second channel holes formed subsequently can be stopped to the stop layers; and

2) the second channel hole penetrating through the laminated structure and extending to the first stop layer and the first channel hole penetrating through the laminated structure and extending to the first stop layer are formed successively, so that the channel holes with different apertures can have approximately the same channel depth.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings. Wherein:

fig. 1 is a flowchart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application; and

fig. 2 to 6 are process step diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;

FIG. 7 is a schematic structural diagram of a storage system according to an embodiment of the present application; and

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first channel hole discussed in this application may also be referred to as a second channel hole, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a height. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 1, a method 1000 for manufacturing a three-dimensional memory provided by the present application may include: s1, alternately stacking barrier layers and stop layers to form a composite structure, wherein the stop layers include a first stop layer; s2, alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a laminated structure; s3, forming a first channel hole extending in the stacking direction of the stacked structure and a second channel hole penetrating the stacked structure and extending to the first stopper layer; and S4, etching the first channel hole to extend the first channel hole to the first stop layer. The steps S1 to S4 will be described in detail below.

As shown in fig. 2, barrier layers 110 and stop layers 120 may be alternately stacked to form a composite structure 100. Illustratively, the barrier layer 110 may include a first barrier layer 111 and a second barrier layer 112. The stop layer 120 may include a first stop layer 121 and a second stop layer 122. Illustratively, the first barrier layer 111, the first stop layer 121, the second barrier layer 112, and the second stop layer 122 may be alternately stacked on one side of the substrate 200 to form the composite structure 100. Illustratively, the barrier layer 110 and the stop layer 120 may be two dielectric layers having different materials. The materials of the barrier layer 110 and the stop layer 120 may have different etching selectivity ratios so as to sequentially remove the barrier layer 110 and the stop layer 120 in a subsequent process. For example, the material of the barrier layer 110 may include an oxide (e.g., silicon oxide), and the material of the stop layer 120 may include polysilicon. In other words, the material of the first barrier layer 111 and the second barrier layer 112 may include silicon oxide, and the material of the first stop layer 121 and the second stop layer 122 may include polysilicon.

In an exemplary embodiment of the present application, the substrate 200 may be, for example, a silicon substrate. Illustratively, the first barrier layer 111 may be grown by oxidation on the silicon substrate 200. The first barrier layer 111 may effectively reduce stress of the first stop layer 121 formed in a subsequent process to the substrate 200. Illustratively, the first stop layer 121 may be formed on the first barrier layer 111 by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The first stop layer 121 has a higher etching selectivity with respect to the first barrier layer 111, and can serve as an etching stop layer of the first barrier layer 111.

It is understood that the number and thickness of the barrier layer 110 and the stop layer 120 are not limited to those shown in fig. 2, and those skilled in the art can arrange any number and thickness of the barrier layer 110 and the stop layer 120 as needed without departing from the concept of the present application.

As shown in fig. 2, insulating layers 310 and sacrificial layers 320 may be alternately stacked on the composite structure 100 to form a stacked structure 300. Illustratively, forming the laminate structure 300 on the composite structure 100 may be accomplished by one or more deposition processes. The deposition process to form the stacked structure 300 includes, but is not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof. It is to be understood that the number and thickness of the insulating layer 310 and the sacrificial layer 320 are not limited to those shown in fig. 2, and those skilled in the art may arrange the insulating layer 310 and the sacrificial layer 320 in any number and thickness as needed without departing from the concept of the present application. In addition, the materials of the insulating layer 310 and the sacrificial layer 320 may be selected from suitable materials known in the art. Illustratively, the insulating layer 310 and the sacrificial layer 320 may be two dielectric layers having different materials. The materials of the insulating layer 310 and the sacrificial layer 320 may have different etching selectivity ratios to facilitate the removal of the sacrificial layer 320 in subsequent processes. Illustratively, the material of the sacrificial layer 320 may include nitride, and the material of the insulating layer 310 may include oxide. For example, the insulating layer 310 may be, for example, silicon oxide, and the sacrificial layer 320 may be, for example, silicon nitride.

As shown in fig. 3, a first channel hole 400 extending in the lamination direction Z of the stacked structure 300 and a second channel hole 500 penetrating the stacked structure 300 and extending to the first stopper layer 121 may be formed. Illustratively, the first channel hole 400 may have a pore diameter ranging from 95 to 120 angstroms, and the second channel hole 500 may have a pore diameter ranging from 150 to 200 angstroms. As shown in fig. 3, the first stop layer 121 may be the stop layer 120 farthest from the stacked structure 300.

In the exemplary embodiment of the present application, the first channel hole 400 and the second channel hole 500 may be formed by, for example, an etching process. Illustratively, an etch mask layer (not shown) that may be patterned is the masking etch stack 300. Since the first channel hole 400 and the second channel hole 500 have different diameters, the first channel hole 400 has a smaller diameter than the second channel hole 500. In an actual etching process, the etching depth of the first channel hole 400 with a smaller aperture may be smaller than the etching depth of the second channel hole 500 with a larger aperture, that is, the first channel hole 400 may extend into the stacked structure 300, and the second channel hole 500 may extend through the stacked structure 300 and extend to the first stop layer 121. It should be understood that in the actual etching process, the larger the aperture of the channel hole, the higher the etching rate of the underlying stack layer, so that the larger the aperture, the larger the etching depth of the channel hole. In other words, in the actual etching process, the etching depth of the channel hole increases as the aperture increases. The plurality of first channel holes 400 may have different etching depths according to the size of the apertures.

In an exemplary embodiment of the present application, the first channel hole 400 may be etched such that the first channel hole 400 extends to the first stop layer 121. Illustratively, as shown in fig. 5, the first channel hole 400 may be etched again by, for example, an etching process such that the first channel hole 400 extends to the first stop layer 121. Specifically, first, the second channel hole 500 (fig. 4) may be covered by a mask 600; then, the first channel hole 400 may be etched such that the first channel hole 400 extends to the first stop layer 121 (fig. 5). Illustratively, the mask 600 may comprise a photoresist or a carbon-based polymer material, and may be formed using a patterning process such as photolithography.

Illustratively, after forming the first channel hole 400 penetrating the stacked structure 300 and extending to the first stop layer 121, a process such as using O may be used₂Or CF₄Dry etching with plasma or resist/polymer photoresist remover(s) ((E.g., solvent-based chemistry) removes the mask 600.

In an exemplary embodiment of the present application, the first and second channel holes 400 and 500 may be filled to form the first and second channel structures 410 and 510, respectively (fig. 6). The radial dimension of the first channel structure 410 is in the range of 95-120 angstroms, and the radial dimension of the second channel structure 510 is in the range of 150-200 angstroms. Illustratively, the first channel structure 410 may be used as a memory cell. The second channel structure 510 may have the same structure as the first channel structure 410, and the second channel structure 510 may be used to balance the overall stress of the three-dimensional memory and reduce the stress concentration phenomenon. In addition, the second channel structure 510 may also have a supporting function to prevent the three-dimensional memory portion region from collapsing.

Specifically, the first and second channel structures 410 and 510 including a functional layer (not shown) and a channel layer (not shown) may be sequentially formed in the first and second channel holes 400 and 500, wherein the functional layer includes a blocking layer (not shown), a charge trapping layer (not shown), and a tunneling layer (not shown) sequentially disposed in the channel holes. For example, a blocking layer, a charge trapping layer, and a tunneling layer may be sequentially formed on the inner walls of the first and second channel holes 400 and 500, and a channel layer may be formed on the surface of the tunneling layer. The functional layer and the channel layer may be formed in the first channel hole 400 and the second channel hole 500 through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

In particular, the functional layer may include a blocking layer blocking outflow of charges, a charge trapping layer formed on a surface of the blocking layer to store charges during operation of the three-dimensional memory, and a tunneling layer formed on a surface of the charge trapping layer. The barrier layer may include one or more layers, which may include one or more materials. Materials for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like. The charge trapping layer may include one or more layers, which may include one or more materials. Materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide band gap material, and the like. The tunneling layer may include one or more layers, which may include one or more materials. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, and the like. In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer may have a structure different from the ONO configuration. For example, the functional layer may comprise a silicon oxide layer, a silicon nitride layer and a further silicon oxide layer.

The channel layer can be used to transport desired charges (electrons or holes). According to an example embodiment of the present application, a channel layer may be formed on a surface of a tunneling layer through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The material of the channel layer includes, but is not limited to, P-type doped polysilicon.

In an exemplary embodiment of the present application, as shown in fig. 6, a gate line gap 700 may be formed to penetrate the stack structure 300 and extend to the first stop layer 121. Illustratively, the gate line gap 700 may be formed through the stack structure 300 and extended to the first stop layer 121 by a photolithography and etching process. Illustratively, the sacrificial layer 320 is replaced with the gate layer 330 through the gate line gap 700. Specifically, first, the sacrificial layer 320 may be removed through the gate line gap 700; then, the removed space may be filled with a conductive material to form the gate layer 330. For example, the removed space may be filled with metal tungsten to form the gate layer 330. Illustratively, in replacing the sacrificial layer 320 with the gate layer 330, the gate line gap 700 may serve as a path for providing an etchant and a chemical precursor, and a process such as wet etching is used to remove all of the sacrificial layer 320 in the stacked-layer structure 300.

Another aspect of the present application provides a three-dimensional memory. Fig. 6 illustrates a schematic structural diagram of a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 6, the three-dimensional memory may include a composite structure 100, a stacked structure (including alternately stacked insulating layers 310 and gate layers 330), a first channel structure 410, and a second channel structure 510.

In an exemplary embodiment of the present application, the composite structure 100 may include barrier layers 110 and stop layers 120 that are alternately stacked. Illustratively, the barrier layer 110 may include a first barrier layer 111 and a second barrier layer 112. The stop layer 120 may include a first stop layer 121 and a second stop layer 122. Illustratively, the three-dimensional memory may further include a substrate 200. The first barrier layer 111, the first stop layer 121, the second barrier layer 112, and the second stop layer 122 may be sequentially located at one side of the substrate 200. Illustratively, the substrate 200 may be, for example, a silicon substrate, and the barrier layer 110 and the stop layer 120 may be two dielectric layers having different materials. The materials of the barrier layer 110 and the stop layer 120 may have different etching selectivity ratios so as to sequentially remove the barrier layer 110 and the stop layer 120 in a subsequent process. For example, the material of the barrier layer 110 may include an oxide (e.g., silicon oxide), and the material of the stop layer 120 may include polysilicon. In other words, the material of the first barrier layer 111 and the second barrier layer 112 may include silicon oxide, and the material of the first stop layer 121 and the second stop layer 122 may include polysilicon.

In an exemplary embodiment of the present application, the first stop layer 121 may be the stop layer 120 farthest from the stacked structure 300. The first barrier layer 111 may effectively reduce stress of the first stop layer 121 formed in a subsequent process to the substrate 200. Illustratively, the first stop layer 121 may be formed on the first barrier layer 111 by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. The first stop layer 121 has a higher etching selectivity with respect to the first barrier layer 111, and can serve as an etching stop layer of the first barrier layer 111. It is understood that the number and thickness of the barrier layer 110 and the stop layer 120 are not limited to those shown in fig. 2, and those skilled in the art can arrange any number and thickness of the barrier layer 110 and the stop layer 120 as needed without departing from the concept of the present application.

In exemplary embodiments of the present application, a laminate structure may be located on the composite structure 100. The number and thickness of the insulating layer 310 and the gate layer 330 are not limited to those shown in fig. 6, and those skilled in the art may dispose the insulating layer 310 and the gate layer 330 in any number and thickness as needed without departing from the concept of the present application. In addition, materials of the insulating layer 310 and the gate layer 330 may be selected from suitable materials known in the art. Illustratively, the material of the gate layer 330 may include a conductive material, and the material of the insulating layer 310 may include an oxide. For example, the insulating layer 310 may be, for example, silicon oxide, and the gate layer 330 may be, for example, metal tungsten.

In an exemplary embodiment of the present application, the first channel structure 410 may penetrate the stack structure and extend to the first stop layer 121. The second channel structure 510 may penetrate the stack structure and extend to the first stop layer 121. Illustratively, the radial dimension of the second channel structure 510 may be greater than the radial dimension of the first channel structure 410. Illustratively, the radial dimension of the first channel structure 410 is in the range of 95-120 angstroms, and the radial dimension of the second channel structure 510 is in the range of 150-200 angstroms. Illustratively, the first channel structure 410 may be used as a memory cell. The second channel structure 510 may have the same structure as the first channel structure 410, and the second channel structure 510 may be used to balance the overall stress of the three-dimensional memory and reduce the stress concentration phenomenon. In addition, the second channel structure 510 may also have a supporting function to prevent the three-dimensional memory portion region from collapsing.

Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described herein again.

Although exemplary methods and structures for fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. In addition, the illustrated layers and materials thereof are merely exemplary.

FIG. 7 is a schematic diagram of a memory system 2000 according to an embodiment of the present application.

As shown in fig. 7, at least one embodiment of the present application further provides a storage system 2000. The memory system 2000 may include a memory 2100 and a controller 2200. The memory 2100 may be the same as described for any of the embodiments above and will not be described in detail herein. The storage system 2000 may be a two-dimensional storage system or a three-dimensional storage system, and the three-dimensional storage system is described as an example below.

The three-dimensional storage system 2000 may include a three-dimensional memory 2100, a controller 2200, and a host 2300. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the above embodiments, and is not described in detail in this application. The controller 2200 may control the three-dimensional memory 2100 through a channel CH, and the three-dimensional memory 2100 may perform an operation based on the control of the controller 2200 in response to a request from the host 2300. The three-dimensional memory 2100 may receive a command CMD and an address ADDR from the controller 2300 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 2100 may perform an internal operation corresponding to a command on a region selected by an address.

In some embodiments, the three-dimensional storage system may be implemented as a device such as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multi-media card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth.

Fig. 8 is a schematic structural diagram of an electronic device 3000 according to an embodiment of the present application.

As shown in fig. 8, at least one embodiment of the present application further provides an electronic device 3000. The electronic device 3000 includes a memory 3100. The memory 3100 may be the same as the memory described in any of the embodiments above, and will not be described in detail herein. The electronic device 3000 may be a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, or other devices with a storage function. Thus, other modules of the electronic device 3000, such as a controller, may be determined based on the particular device type of the electronic device 3000. The other modules may control the three-dimensional memory 3100 through, for example, a channel, and the three-dimensional memory 3100 may receive a command CMD and an address ADDR from the other modules through, for example, a channel, and access a region selected from the memory cell array in response to the address. This is not limited in this application.

The application provides a peripheral circuit, a memory, a storage system and an electronic device, and the metal interconnection structure provided by the application is arranged, so that the peripheral circuit, the memory, the storage system and the electronic device have the same beneficial effects as the metal interconnection structure, and the details are not repeated herein.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (15)

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

alternately stacking barrier layers and stop layers to form a composite structure, wherein the stop layers comprise a first stop layer;

alternately stacking an insulating layer and a sacrificial layer on the composite structure to form a stacked structure;

forming a first channel hole extending in a lamination direction of the laminated structure and a second channel hole penetrating the laminated structure and extending to the first stop layer; and

and etching the first channel hole to extend the first channel hole to the first stop layer.

2. The production method according to claim 1,

the aperture of the first channel hole is within the range of 95-120 angstroms; and

the aperture of the second channel hole is in the range of 150-200 angstroms.

3. The method of claim 2, wherein etching the first channel hole to extend the first channel hole to the first stop layer comprises:

and covering the second channel hole, and etching the first channel hole to enable the first channel hole to extend to the first stop layer.

4. The method of manufacturing according to claim 1, wherein the first stop layer is the stop layer farthest from the laminated structure.

5. The production method according to any one of claims 1 to 4,

the material of the barrier layer comprises oxide; and

the stop layer comprises polysilicon.

6. The production method according to any one of claims 1 to 4,

the insulating layer is made of oxide; and

the material of the sacrificial layer comprises nitride.

7. The method of any one of claims 1-4, further comprising:

filling the first and second channel holes to form first and second channel structures, respectively.

8. The method of manufacturing according to claim 7, further comprising:

and forming a grid line gap, and replacing the sacrificial layer into a grid layer through the grid line gap.

9. The method of claim 8, wherein the gate layer comprises tungsten.

10. A three-dimensional memory, comprising:

a composite structure comprising barrier layers and stop layers alternately stacked, wherein the stop layers comprise a first stop layer;

a stacked structure on the composite structure and including alternately stacked insulating layers and gate layers;

a first channel structure penetrating the stacked structure and extending to the first stop layer; and

a second channel structure extending through the stack structure and to the first stop layer, wherein a radial dimension of the second channel structure is greater than a radial dimension of the first channel structure.

11. The three-dimensional memory according to claim 10,

the radial dimension of the first channel structure is within the range of 95-120 angstroms; and

the radial dimension of the second channel structure is in the range of 150-200 angstroms.

12. The three-dimensional memory according to claim 10, wherein the first stop layer is the stop layer farthest from the stacked structure.

13. A storage system comprising a controller and the three-dimensional memory of any one of claims 10-12, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data.

14. An electronic device, comprising: the storage system of claim 13.

15. The electronic device of claim 14, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.

Images