CN114334987A - Three-dimensional memory and preparation method thereof - Google Patents

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The preparation method of the three-dimensional memory comprises the following steps: forming a protective layer with an etching stop structure on the doped layer; forming a stacked structure including a plurality of step steps on the protective layer, and forming a buffer layer on a top surface of each of the step steps; and forming a gate gap penetrating through the step and extending to the etch stop structure, wherein the gate gap extends in a direction perpendicular to the sidewall of the step.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory and a method for fabricating the same.

Background

In general, a three-dimensional memory includes a stacked structure formed by alternately stacking gate layers and insulating layers, wherein an electrical connection of an external circuit to a gate is achieved through a contact structure located at a stepped region of the stacked structure. In the actual manufacturing process of the three-dimensional memory, in order to realize the electrical connection between the contact structure and the gate electrode layer in the stacked structure, it is necessary to etch a contact hole in the dielectric layer covering the step region to expose the top surface of each gate electrode layer in the step region, and then fill a conductive material in the contact hole to form the contact structure.

However, as the integration level of the three-dimensional memory is increased and the number of stacked layers is increased, the depth of the contact hole is increased, and thus the gate layer is easily broken down during the formation of the contact hole. In this case, after the contact hole is filled with a conductive material for forming a contact structure, a short circuit between different gate electrode layers (i.e., a word line bridge between different layers) may be caused, thereby causing a failure of the memory device.

In addition, in the actual manufacturing process of the three-dimensional memory, a gate gap needs to be provided to divide the stacked structure into a plurality of memory blocks. However, in the step region, since the gate gap passes through a plurality of step steps having different thicknesses, the height of each gate gap has a certain difference, and thus the height of the gate gap cannot be well controlled.

Disclosure of Invention

The application provides a preparation method of a three-dimensional memory, which comprises the following steps: forming a protective layer with an etching stop structure on the doped layer; forming a stacked structure including a plurality of step steps on the protective layer, and forming a buffer layer on a top surface of each of the step steps; and forming a gate gap penetrating through the step and extending to the etch stop structure, wherein the gate gap extends in a direction perpendicular to the sidewall of the step.

In one embodiment, the material of the doped layer and the buffer layer includes polysilicon.

In one embodiment, forming a stacked structure including a plurality of step steps on the protective layer includes: alternately stacking a sacrificial layer and an insulating layer on the protective layer; and processing the insulating layer and the sacrificial layer to form a plurality of step steps, wherein a portion of the sacrificial layer is exposed as an upper surface of the step steps.

In one embodiment, forming a buffer layer on a top surface of each of the step steps includes: forming the buffer layer covering the step; and removing portions of the buffer layer covering the sidewalls of the step steps to form a buffer layer on a top surface of each of the step steps.

In one embodiment, the method further comprises: and forming a dielectric layer covering the step, wherein the grid gap penetrates through the dielectric layer and the step and extends to the etching stop structure.

In one embodiment, the method further comprises: and forming a virtual channel structure penetrating through the dielectric layer, the buffer layer and the step.

In one embodiment, the method further comprises: sequentially removing the remaining portions of the sacrificial layer and the buffer layer through the gate gap to form a first gap; removing the etch stop structure through the gate gap to form a second gap; and forming a gate layer and a conductive layer in the first gap and the second gap, respectively.

In one embodiment, forming a gate layer and a conductive layer in the first gap and the second gap, respectively, includes: sequentially forming a barrier layer and an adhesive layer in the first gap and the second gap; and forming a gate layer and a conductive layer on the adhesive layer in the first gap and the second gap, respectively.

In one embodiment, the method further comprises: and etching back the barrier layer, the adhesive layer, the gate layer and the conductive layer, and filling the etched-back part with an insulating material.

In one embodiment, forming a dummy channel structure through the dielectric layer, the buffer layer, and the step comprises: forming a virtual channel hole penetrating through the dielectric layer, the buffer layer and the step; removing at least a portion of the sacrificial layer adjacent to the virtual channel hole; and filling the virtual channel hole and at least one part of the removed sacrificial layer adjacent to the virtual channel hole with an insulating material to form the virtual channel structure.

Another aspect of the present application provides a three-dimensional memory, including: a protective layer; the laminated structure is positioned on the protective layer and comprises a plurality of step steps; the conducting layer is positioned on the top surface of the step; and a gate gap structure extending in a direction perpendicular to the sidewall of the step, penetrating the step, and extending to the protective layer.

In one embodiment, the stacked structure includes alternately stacked insulating layers and gate layers, wherein a portion of the gate layer is exposed as an upper surface of the step.

In one embodiment, the three-dimensional memory further comprises: and the dielectric layer is positioned on the side wall of the step and the conducting layer so as to cover the step.

In one embodiment, the three-dimensional memory further comprises: and the virtual channel structure penetrates through the dielectric layer, the conducting layer and the step.

In one embodiment, the three-dimensional memory further comprises: a barrier layer and an adhesive layer between the conductive layer and the insulating layer.

In one embodiment, the three-dimensional memory further comprises: the protective layer is located on the doped layer, and the doped layer is made of polycrystalline silicon.

In one embodiment, the material of the insulating layer includes an oxide; and the material of the gate layer and the conductive layer comprises metal.

In one embodiment, the material of the barrier layer includes a high dielectric constant material; and the material of the adhesion layer comprises nitride.

The three-dimensional memory and the preparation method thereof provided according to one or more embodiments of the present application may have at least one of the following advantages:

1) forming a protective layer with an etching stop structure on the doped layer, which is not only beneficial to stopping the grid gap at the etching stop structure, but also beneficial to reducing the influence of the actual preparation process on the doped layer below the etching stop structure; and

2) the buffer layer is formed on the top surface of each step, so that the thickness of each step is increased, the thickness of the subsequently formed gate layer is increased, and the risk of breakdown of the gate layer in the process of forming the contact hole is reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings. Wherein:

fig. 1 is a flowchart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application; and

fig. 2 to 19 are process step diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first gap discussed in this application may also be referred to as a second gap, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a height. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 1, a method 1000 for manufacturing a three-dimensional memory provided by the present application may include: s1, forming a protective layer with an etching stop structure on the doped layer; s2, forming a laminated structure including a plurality of step steps on the protective layer, and forming a buffer layer on the top surface of each step; and S3, forming a gate gap penetrating the step and extending to the etching stop structure, wherein the gate gap extends along a direction perpendicular to the side wall of the step. The steps S1 to S3 will be described in detail below.

Fig. 2 shows a schematic perspective structure diagram of the three-dimensional memory after the protective layer is formed in the XYZ three-dimensional space according to the embodiment of the present application. As shown in fig. 2, a protective layer 200 having an etch stop structure 210 may be formed on the doped layer 100. Illustratively, the doped layer 100 may be first formed on one side of the substrate 300, and then the protection layer 200 having the etch stop structure 210 may be formed on the doped layer 100. Illustratively, the material of the etch stop structure 210 may include metal tungsten, and the material of the doped layer 100 may include polysilicon. The etch stop structure 210 is disposed in the protection layer 200, which is not only beneficial for stopping the gate gap formed subsequently at the etch stop structure 210, but also beneficial for reducing the damage of the actual process to the doping layer 100 in the process of forming the gate layer subsequently. Illustratively, the protective layer 200 may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, the protective layer 200 may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, which are sequentially disposed.

In exemplary embodiments of the present application, the substrate 300 may be, for example, a polycrystalline silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 300 may also be a stacked structure, such as Si/SiGe or the like. In further embodiments, the substrate 300 may also be other epitaxial structures, such as Silicon Germanium On Insulator (SGOI) and the like.

In an exemplary embodiment of the present application, the material of the doped layer 100 may include polysilicon. In subsequent processes, doping of N-type or P-type dopants in the doped layer 100 may be performed via ion implantation and diffusion processes. Illustratively, the dopant may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb).

Fig. 3 to 9 are process step diagrams respectively illustrating a method for manufacturing a three-dimensional memory in YZ plane.

As shown in fig. 3 to 7, a stacked structure 500 including a plurality of step steps 400 may be formed on the protection layer 200, and a buffer layer 410 may be formed on a top surface of each step 400. Illustratively, as shown in fig. 3, an insulating layer 510 and a sacrificial layer 520 may be alternately stacked on the protective layer 200 to form a stacked structure 500, and the insulating layer 510 and the sacrificial layer 520 may be processed to form a plurality of step steps 400 (fig. 4). Illustratively, as shown in fig. 5, a portion of the sacrificial layer 520 of each step 400 may be exposed as an upper surface of the step 400. For example, the exposed portion of the insulating layer 510 of each step 400 (fig. 4) may be removed to expose at least a portion of the sacrificial layer 520 of each step 400 (fig. 5).

In an exemplary embodiment of the present application, forming the stacked structure 500 on the protective layer 200 may be achieved by one or more deposition processes. The deposition process to form the stacked structure 500 includes, but is not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof. It is to be understood that the number and thickness of the insulating layer 510 and the sacrificial layer 520 are not limited to those shown in fig. 3, and those skilled in the art may arrange the insulating layer 510 and the sacrificial layer 520 in any number and thickness as needed without departing from the concept of the present application. In addition, the materials of the insulating layer 510 and the sacrificial layer 520 may be selected from suitable materials known in the art. For example, the insulating layer 510 may be an oxide layer (such as silicon oxide) and the sacrificial layer 520 may be a nitride layer (such as silicon nitride).

As shown in fig. 4, the stacked structure 500 may have a core region (not shown) in addition to a stepped region having a stepped step 400, wherein the core region may be used to form an array of memory cell strings, which may be a plurality of interconnected memory cells formed in a direction perpendicular to the substrate 300; the stepped region may be used to form a contact structure on a gate layer (which may be formed by replacing a sacrificial layer) to draw current therefrom.

For the sake of brevity and clarity, the process is described herein only by way of an example of a stack structure comprising a single sub-stack, and it should be understood by those skilled in the art that the stack structure 500 may further comprise a plurality of sub-stacks, i.e. the stack structure 500 may be formed by a single sub-stack or a plurality of sub-stacks stacked in sequence. It should also be noted that, for the sake of clarity, in the various figures of the present application, only portions of the stepped region of the stacked structure 500 are shown.

In an exemplary embodiment of the present application, the stacked structure 500 may be first subjected to a repeated etch-trim process by using a patterned mask (not shown), thereby forming a plurality of step steps 400 in a step region. The patterned mask may include a photoresist or a carbon-based polymer material, and may be removed after the step 400 is formed. Referring to fig. 4, the top surface of each step 400 is formed to expose at least a portion of the insulating layer 510 at the corresponding layer. That is, each step 400 includes at least one level, and each level includes an insulating layer 510 and a sacrificial layer 520 in sequence from top to bottom.

In the exemplary embodiment of the present application, the step 400 may be formed at a central position of the stacked structure 500, and may also be formed at one side edge or a plurality of side edges of the stacked structure 500. By way of example, the following description will be primarily directed to a stepped step 400 formed at one or more side edges of the laminate structure 500. Further, it should be noted that in order to concisely and clearly illustrate the present application, the figures herein only show the case where each step ladder 400 includes one level. It should also be noted that the number of the step steps 400 can be adjusted as needed, depending on the number of sacrificial layers 520 in the stack structure 500 and the number of levels each step 400 contains.

In an exemplary embodiment of the present application, as shown in fig. 7, a top surface buffer layer 411 may be formed on the top surface of each step 400 through, for example, a deposition process. Specifically, first, a buffer layer 410 covering the step steps 400 may be formed (fig. 6, the buffer layer 410 may include a top surface buffer layer 411 at a top surface of each step 400 and a sidewall buffer layer 412 at a sidewall of each step 400); then, a portion of the buffer layer 410 covering the sidewalls of the step steps 400 (sidewall buffer layer 412) may be removed to form a top surface buffer layer 411 (fig. 7) on the top surface of each step 400. As an example, the top surface buffer layer 411 and the sidewall buffer layer 412 may be formed on the top surface and the sidewall of each step 400, respectively, by, for example, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof, to cover the step steps 400. For example, the buffer layer 410 may be formed by an atomic layer deposition process. As an example, the material forming the buffer layer 410 may be polysilicon.

Illustratively, the sidewall buffer layer 412 may be removed such that the top surface buffer layer 411 is spaced apart from the sacrificial layer 520 on the same plane. Such a space may prevent the top buffer layer 411 from contacting the sacrificial layer 520 on the same plane. In this way, when the top buffer layer 411 and the sacrificial layer 520 are subsequently replaced with gate layers, short circuits between different gate layers (i.e., word line bridges between different layers) can be effectively avoided. In addition, replacing the top buffer layer 411 with a gate layer can increase the thickness of the gate layer, thereby effectively avoiding the gate layer from being broken down when a contact hole is formed subsequently. As an example, the sidewall buffer layer 412 formed on the sidewall of the step may be removed using dry etching such as deep ion reactive etching (RIDE) or wet etching using phosphoric acid as an etchant, but the present application is not limited thereto. It should be understood that deep ion reactive etching (RIDE) may generally include the followingThe method comprises the following steps: (1) an etching step, usually with argon (Ar), oxygen (O)₂) Sulfur Fluoride (SF)₆) The mixed gas is subjected to plasma etching to form holes; (2) a polymer deposition step, typically with argon (Ar) and octafluorocyclobutane (C)₄F₈) The mixed gas forms a fluorocarbon polymer layer on the inner side surface of the hole, the thickness of the fluorocarbon polymer layer is generally in a nanometer level, sometimes called the polymer layer is a passivation layer, and in order to ensure that the fluorocarbon polymer layer is not formed on the bottom of the hole, a relatively low RF (Radio Frequency) Frequency is generally adopted in the step; (3) the etching step and the polymer deposition step are alternately carried out until the etching of the through hole is finished, in the etching step, because the polymer is deposited on the inner surface of the hole, particularly the inner side surface of the hole, when the vertical plasma etching is carried out, the incident ions can not damage the polymer on the inner side surface of the hole and can protect the side wall, and the incident ions in the vertical direction can damage the polymer at the bottom of the hole so that the etching reaction can be continued downwards, thereby ensuring the anisotropy of the whole hole etching process.

As an example, when performing the gate layer replacement, for example, a conventional etching process (e.g., wet etching) may be used to remove the top buffer layer 411, and then another etching process (e.g., acid etching) may be used to remove the sacrificial layer 520; finally, a conductive material such as tungsten metal is refilled to form a gate layer.

In an exemplary embodiment of the present application, as shown in fig. 8, a dielectric layer 600 may be formed to cover the step 400. The dielectric layer 600 fills the portion where the sidewall buffer layer 412 is removed, in addition to filling above the step 400. By way of example, dielectric layer 600 may be formed by depositing an oxide, which may be selected from, for example, silicon oxide-based materials. In an exemplary embodiment of the present application, dielectric layer 600 may be formed from a tetraethyl orthosilicate (TEOS) based silicon oxide fill. Illustratively, the dielectric layer 600 may be a multi-layer structure, and a first sub-film layer with good step coverage is formed first, such as a silicon oxide (SiO) layer deposited by High Density Plasma (HDP)₂) Or Atomic Layer Deposited (ALD) silicon oxide, or the like; then, the formation of a second sub-film layer with high filling efficiency is continued, and the second sub-film layer can be formedIs TEOS-based silicon oxide (TESO-based SiO)₂) And the like. In an exemplary embodiment, the density of the first sub-film layer is higher than that of the second sub-film layer, whereby the first sub-film layer has good step coverage and the second sub-film layer has high filling efficiency.

As an example, the dielectric layer 600 may be planarized by a chemical mechanical polishing process, such that the dielectric layer 600 provides a substantially flat upper surface for the step region of the stacked structure 500.

Fig. 9 to 19 are process step diagrams respectively illustrating a method for manufacturing a three-dimensional memory in an XZ plane.

In an exemplary embodiment of the present application, as shown in fig. 12, a dummy channel structure 700 may be formed to penetrate the dielectric layer 600, the buffer layer 410, and the step 400. Illustratively, first, the dielectric layer 600 may be etched to form a virtual channel hole 710 (fig. 10) through the dielectric layer 600, the buffer layer 410, and the step 400, with the patterned etch mask layer 10 (including the hard mask layer 11 and the photoresist layer 12 covering the hard mask layer 11) as a mask (fig. 9); next, at least a portion of the sacrificial layer 520 adjacent to the dummy channel hole 710 may be removed (fig. 11); then, the dummy channel hole 710 and at least a portion of the removed sacrificial layer 520 adjacent to the dummy channel hole 710 may be filled with an insulating material to form a dummy channel structure 700 (fig. 12). As an example, a dummy trench hole 710 penetrating through the dielectric layer 600 and extending to the doped layer 100 may be formed in the step region by, for example, a photolithography and etching process; next, a back etching process may be used to remove at least a portion of the sacrificial layer 520 adjacent to the dummy trench hole 710, so as to improve the insulation between the dummy trench structure 700 and the subsequently formed gate layer (formed by replacing the sacrificial layer 520) while ensuring the size of the subsequently formed dummy trench structure 700; then, an insulating material is filled in the dummy channel hole 710 and at least a portion of the removed sacrificial layer 520 adjacent to the dummy channel hole 710 to form a dummy channel structure 700, for example, by depositing a silicon nitride-based material by ALD to form the dummy channel structure 700. The dummy trench structure 700 can have a supporting function to prevent the collapse of the whole structure of the three-dimensional memory when the sacrificial layer 520 and the buffer layer 410 are replaced with a gate layer and a conductive layer, respectively. Illustratively, during the process of removing at least a portion of the sacrificial layer 520 adjacent to the dummy channel hole 710, the dummy channel hole 710 may serve as a passage for providing an etchant and a chemical precursor, and at least a portion of the sacrificial layer 520 adjacent to the dummy channel hole 710 may be removed using a process such as wet etching. Illustratively, a portion of the sacrificial layer 520 may be removed using, for example, a wet etching process, so as to form a concave-convex structure along the thickness direction of the stacked-layer structure 500 around the dummy trench hole 710, wherein the concave-convex structure includes a space formed after removing the portion of the sacrificial layer 520 in the stacked-layer structure 500.

As shown in fig. 13, a gate gap 800 may be formed through the step 400 and extending to the etch stop structure 210. The gate gap 800 may extend in a direction perpendicular to the sidewalls of the step 400. Illustratively, the gate gap 800 may be formed to extend in a direction perpendicular to the sidewalls of the step 400, and to extend through the dielectric layer 600 and the step 400 and to the etch stop structure 210. For example, a plurality of gate gaps 800 may be formed in the step region through a photolithography and etching process, and the plurality of gate gaps 800 may extend in a direction perpendicular to the sidewalls of the step 400. In an actual fabrication process, each gate gap 800 may cross the sidewall of the step 400.

Illustratively, the dielectric layer 600 and the step 400 have different densities. The density of the first sub-film layer is different from the density of the second sub-film layer in the dielectric layer 600. By providing the etching stop structure 210 in the protection layer 200, the plurality of gate gaps 800 extending in a direction perpendicular to the sidewalls of the step steps 400 and penetrating the step steps 400 with different heights can be stopped in the etching stop structure 210. Illustratively, the material forming the etch stop structure 210 may include metal tungsten, and the material forming the etch stop structure 210 is configured to have a relatively high etching selectivity, which is advantageous for the gate gaps 800 to stay in the etch stop structure 210. In addition, since both the buffer layer 410 and the doped layer 100 may be made of polysilicon, the protection layer 200 may be disposed on the doped layer 100 to prevent the doped layer 100 from being exposed, and thus, the doped layer 100 may be prevented from being damaged by the etching solution in the process of replacing the buffer layer 410 with the gate layer.

Illustratively, in the gate layer and conductive layer replacement, an etching process (e.g., wet etching) may be used to sequentially remove the sacrificial layer 520 and the buffer layer 410, such as first removing the sacrificial layer 520 (fig. 14) and then removing the buffer layer 410 (fig. 15). The space formed after removing the sacrificial layer 520 and the buffer layer 410 may be filled with a conductive material such as tungsten metal to form the gate layer 530 and the conductive layer 900, respectively (fig. 17). Illustratively, the sacrificial layer 520 and the buffer layer 410 may be removed via the gate gap 800 (fig. 16). The gate gap 800 may serve as a path for providing an etchant and a chemical precursor, and all of the sacrificial layer 520 and the buffer layer 410 in the stack structure 500 may be removed by a process such as wet etching.

In an exemplary embodiment of the present application, the process of replacing the sacrificial layer 520 and the buffer layer 410 with the gate layer 530 and the conductive layer 900, respectively, may include: the remaining portions of the sacrificial layer 520 and the buffer layer 410 may be sequentially removed through the gate gap 800 to form a first gap 20 (fig. 15); then, a conductive material may be filled in the first gap 20 to form the gate layer 530 and the conductive layer 900, respectively (fig. 17). Illustratively, the etch stop structure 210 may also be removed via the gate gap 800 after forming the first gap 20 to form the second gap 30 (fig. 16); then, a conductive material may be filled in the first and second gaps 20 and 30 to form the gate layer 530 and the conductive layer 900, respectively (fig. 17). It is understood that filling the second gap 30 with a conductive material facilitates electrical connection between the conductive layer 900 and the doped layer 100.

In the exemplary embodiment of the present application, as shown in fig. 17, a barrier layer 910 may be formed on inner walls of the first and second gaps 20 and 30. Illustratively, the barrier layer 910 may be formed on the inner walls of the first and second gaps 20 and 30 using a deposition process such as CVD, PVD, ALD, or any combination thereof. Specifically, as shown in fig. 17, after the first and second gaps 20 and 30 are formed, a barrier layer 910 covering the surface of the insulating layer 510 may be formed in the first and second gaps 20 and 30 using a deposition process.

In an exemplary embodiment of the present application, the material of the barrier layer 910 includes a high dielectric constant material. Forming the barrier layer 910 (high-k dielectric layer) on the inner walls of the first and second gaps 20 and 30 can effectively prevent charges in the conductive layer 900 and the gate layer 530 from diffusing into the insulating layer 510. On the other hand, the blocking layer 910 can increase the dielectric constant between the gate layer 530 and the insulating layer 510, thereby enhancing the controllability of the gate layer 530.

In an exemplary embodiment of the present application, as shown in fig. 17, an adhesive layer 920 may be formed on a surface of a barrier layer 910. Illustratively, a deposition process such as CVD, PVD, ALD, or any combination thereof may be employed to form the adhesion layer 920 on the surface of the barrier layer 910. Specifically, as shown in fig. 17, after the barrier layer 910 is formed, an adhesive layer 920 covering the surface of the barrier layer 910 may be formed in the first and second gaps 20 and 30 using a deposition process.

In an exemplary embodiment of the present application, the material of the adhesion layer 920 includes nitride. As shown in fig. 17, an adhesion layer 920 is formed on the surface of the barrier layer 910 to enhance the connection between the gate layer 530 and the barrier layer 910, and may be made of a material capable of blocking the diffusion of metal ions and having conductivity, such as titanium nitride (TiN), thallium nitride (TaN), or a combination thereof. In some embodiments, the adhesion layer 920 may be in direct contact with the gate layer 530 and the barrier layer 910, respectively. In some embodiments, adhesive layer 920 may be a multilayer structure.

In the exemplary embodiment of the present application, as shown in fig. 18, the barrier layer 910, the adhesion layer 920, the gate layer 530 and the conductive layer 900 may be etched back through the gate gap 800. Further, as shown in fig. 19, the etched-back portion may be filled with an insulating material to form a gate gap structure 40. Illustratively, a portion of the barrier layer 910, the adhesion layer 920, the gate layer 530, and the conductive layer 900 may be etched by, for example, an etching solution. In the present application, the etch-back barrier layer 910, the adhesive layer 920, the gate layer 530 and the conductive layer 900 are filled with an insulating material in the etch-back region to form the gate gap structure 40, so as to ensure the disconnection between adjacent gate layers 530 and avoid the subsequent phenomena of electrical connection of the gate layers 530 at different levels.

Another aspect of the present application provides a three-dimensional memory. Fig. 19 illustrates a schematic structure of a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 19, the three-dimensional memory may include a stacked structure, wherein the stacked structure may include a protective layer 200, a stacked structure, a conductive layer 900, and a gate gap structure 40.

The stacked structure may include insulating layers 510 and gate layers 530 that are alternately stacked. The stacked structure may be on the protective layer 200. The stacked structure includes a plurality of stepped steps (fig. 9), and a portion of the gate layer 530 may be exposed as an upper surface of the stepped steps. For example, the material of the insulating layer 510 may include oxide.

The conductive layer 900 may be located on the top surface of the step. For example, conductive layer 900 can be located on exposed portions of gate layer 530. This is advantageous for increasing the thickness of the exposed portion of the gate layer and for reducing the risk of subsequent gate layer breakdown during the formation of the contact hole. Illustratively, the material of the gate layer 530 and the conductive layer 900 may include metal tungsten.

The gate gap structure 40 may extend in a direction perpendicular to the sidewalls of the step, penetrate the step, and extend to the protection layer 200.

In an exemplary embodiment of the present application, the three-dimensional memory may further include a dielectric layer 600. A dielectric layer 600 may be positioned on the sidewalls of the step steps and the conductive layer 900 to cover the step steps.

In an exemplary embodiment of the present application, the three-dimensional memory may further include a dummy channel structure 700. The dummy channel structure 700 may penetrate the dielectric layer 600, the conductive layer 900, and the step. The dummy channel structure 700 may have a supporting function.

In an exemplary embodiment of the present application, the three-dimensional memory may further include a barrier layer 910 and an adhesive layer 920 between the conductive layer 900 and the insulating layer 510. The material of the barrier layer 910 includes a high dielectric constant material. A barrier layer 910 (a high-k dielectric layer) is disposed between the conductive layer 900 and the insulating layer 510, so that charges in the conductive layer 900 and the gate layer 530 can be effectively prevented from diffusing into the insulating layer 510. On the other hand, the blocking layer 910 can increase the dielectric constant between the gate layer 530 and the insulating layer 510, thereby enhancing the controllability of the gate layer 530. The material of adhesion layer 920 includes nitride. The adhesion layer 920 is formed on the surface of the barrier layer 910 to enhance the connection between the gate layer 530 and the barrier layer 910, and may be made of a material selected to block the diffusion of metal ions and have conductivity, such as titanium nitride (TiN), thallium nitride (TaN), or a combination thereof. In some embodiments, the adhesion layer 920 may be in direct contact with the gate layer 530 and the barrier layer 910, respectively. In some embodiments, adhesive layer 920 may be a multilayer structure.

In an exemplary embodiment of the present application, the three-dimensional memory may further include a doping layer 100. The passivation layer 200 may be disposed on the doped layer 100, and the material of the doped layer 100 includes polysilicon.

Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described herein again.

Although exemplary methods and structures for fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. In addition, the illustrated layers and materials thereof are merely exemplary.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (18)

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a protective layer with an etching stop structure on the doped layer;

forming a stacked structure including a plurality of step steps on the protective layer, and forming a buffer layer on a top surface of each of the step steps; and

and forming a gate gap penetrating through the step and extending to the etching stop structure, wherein the gate gap extends along a direction perpendicular to the side wall of the step.

2. The method according to claim 1, wherein the doped layer and the buffer layer are made of polysilicon.

3. The method of claim 1, wherein forming a stacked structure including a plurality of step steps on the protective layer comprises:

alternately stacking an insulating layer and a sacrificial layer on the protective layer; and

processing the insulating layer and the sacrificial layer to form a plurality of step steps, wherein a portion of the sacrificial layer is exposed as an upper surface of the step steps.

4. The method of claim 3, wherein forming a buffer layer on a top surface of each of the step steps comprises:

forming the buffer layer covering the step; and

removing portions of the buffer layer covering the sidewalls of the step steps to form a buffer layer on a top surface of each of the step steps.

5. The method of manufacturing according to claim 3, further comprising:

and forming a dielectric layer covering the step, wherein the grid gap penetrates through the dielectric layer and the step and extends to the etching stop structure.

6. The method of manufacturing according to claim 5, further comprising:

and forming a virtual channel structure penetrating through the dielectric layer, the buffer layer and the step.

7. The method of manufacturing according to claim 6, further comprising:

sequentially removing the remaining portions of the sacrificial layer and the buffer layer through the gate gap to form a first gap;

removing the etch stop structure through the gate gap to form a second gap; and

and respectively forming a gate layer and a conductive layer in the first gap and the second gap.

8. The method of manufacturing according to claim 7, wherein forming a gate layer and a conductive layer in the first gap and the second gap, respectively, comprises:

sequentially forming a barrier layer and an adhesive layer in the first gap and the second gap; and

forming a gate layer and a conductive layer on the adhesion layer within the first gap and the second gap, respectively.

9. The method of manufacturing according to claim 8, further comprising:

and etching back the barrier layer, the adhesive layer, the gate layer and the conductive layer, and filling the etched-back part with an insulating material.

10. The method of claim 6, wherein forming a dummy channel structure through the dielectric layer, the buffer layer, and the step comprises:

forming a virtual channel hole penetrating through the dielectric layer, the buffer layer and the step;

removing at least a portion of the sacrificial layer adjacent to the virtual channel hole; and

and filling the virtual channel hole and at least one part of the removed sacrificial layer, which is adjacent to the virtual channel hole, with an insulating material to form the virtual channel structure.

11. A three-dimensional memory, comprising:

a protective layer;

the laminated structure is positioned on the protective layer and comprises a plurality of step steps;

the conducting layer is positioned on the top surface of the step; and

and the grid gap structure extends along the direction vertical to the side wall of the step, penetrates through the step and extends to the protective layer.

12. The three-dimensional memory according to claim 11, wherein the stacked structure comprises alternately stacked insulating layers and gate layers, wherein a portion of the gate layers is exposed as an upper surface of the step.

13. The three-dimensional memory according to claim 12, further comprising:

and the dielectric layer is positioned on the side wall of the step and the conducting layer so as to cover the step.

14. The three-dimensional memory according to claim 13, further comprising:

and the virtual channel structure penetrates through the dielectric layer, the conducting layer and the step.

15. The three-dimensional memory according to claim 14, further comprising:

a barrier layer and an adhesive layer between the conductive layer and the insulating layer.

16. The three-dimensional memory according to claim 11, further comprising:

the protective layer is located on the doped layer, and the doped layer is made of polycrystalline silicon.

17. The three-dimensional memory according to claim 12,

the insulating layer is made of oxide; and

the material of the gate layer and the conductive layer comprises metal.

18. The three-dimensional memory according to claim 15,

the material of the barrier layer comprises a high dielectric constant material; and

the material of the adhesion layer comprises nitride.

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