CN114334876A

CN114334876A - Vertical interconnection structure, manufacturing method thereof, packaged chip and chip packaging method

Info

Publication number: CN114334876A
Application number: CN202011455250.6A
Authority: CN
Inventors: 魏潇赟; 杨勇; 邓抄军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-09-30
Filing date: 2020-12-10
Publication date: 2022-04-12

Abstract

The embodiment of the application discloses a vertical interconnection structure, a manufacturing method thereof, a packaged chip and a chip packaging method, and belongs to the technical field of chip packaging. The method comprises the steps of forming a conductive column on a first surface of a substrate, and forming a first insulating support layer on the first surface, wherein the conductive column is located in the first insulating support layer, and the upper surface, far away from the substrate, of the conductive column is not covered by the first insulating support layer; and finally, removing the substrate, wherein the first insulating support layer is formed by at least one material of amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride and diamond. The conductive columns are formed on the substrate firstly, and then the first insulation supporting layer wrapping the conductive columns is formed, so that through holes for containing the conductive columns are not required to be formed in the first insulation supporting layer through the processes of etching, laser ablation and the like, and adverse effects caused by the processes of etching, laser ablation and the like are avoided.

Description

Vertical interconnection structure, manufacturing method thereof, packaged chip and chip packaging method

The present application claims priority from chinese patent application No. 202011066391.9 entitled "semiconductor manufacturing method" filed 30/09/2020, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to the field of chip packaging technologies, and in particular, to a vertical interconnect structure, a method for manufacturing the same, a packaged chip, and a method for packaging the chip.

Background

With the development of the fields of the internet of things, artificial intelligence and the like, the integration level of the chip is higher and higher, so that the packaging technology of the chip is continuously developed. The application of the three-dimensional packaging technology greatly improves the integration level of the chip.

In the three-dimensional packaging of chips, vertical interconnect structures are typically used. The vertical interconnection structure comprises an insulation supporting layer and conductive columns, wherein the insulation supporting layer is in a plate shape and is provided with a plurality of through holes, the conductive columns are positioned in the through holes, and when the vertical interconnection structure is packaged, two ends of each conductive column are respectively and electrically connected with chips or packaging substrates positioned on two sides of the insulation supporting layer.

When a vertical interconnect structure is fabricated, a through hole is typically fabricated on an insulating support layer, and then a conductive pillar is formed in the through hole by electroplating or the like. The through hole is formed by an etching method or a laser ablation method, the side wall of the through hole formed by the etching method is usually uneven, and the local temperature is higher in the laser ablation process, so that a heat influence area is formed in the insulating support layer, and the reliability of the packaged chip is influenced by the problems.

Disclosure of Invention

The embodiment of the application provides a vertical interconnection structure and a manufacturing method thereof, a packaged chip and a chip packaging method, which can overcome the problems existing in the vertical interconnection structure manufacturing in the related technology, and the technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a method for manufacturing a vertical interconnect structure, where the method includes:

and forming the conductive columns on the first surface of the substrate. And forming a first insulating support layer on the first surface, wherein the conductive columns are positioned in the first insulating support layer, the upper surfaces, far away from the substrate, of the conductive columns are not covered by the first insulating support layer, and the substrate is removed. Wherein the first insulating support layer is formed by at least one material of amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride and diamond. In some embodiments, the substrate has a polygonal plate shape or a circular plate shape. The substrate has a first surface, a second surface and a side surface connecting the first surface and the second surface, wherein the substrate has a plurality of side surfaces if the plate body is polygonal plate-shaped, and a cylindrical side surface if the plate body is circular plate-shaped.

Based on the method, when the vertical interconnection structure is manufactured, the conductive column is formed before the first insulation supporting layer, so that when the first insulation supporting layer is formed, the material for manufacturing the first insulation supporting layer can be directly wrapped around the conductive column, the conductive column is embedded in the first insulation supporting layer, the manufacturing of the through hole on the first insulation supporting layer is not needed in the manufacturing process, and adverse effects caused by the technological process for manufacturing the through hole are avoided.

In some examples, the first insulating support layer is formed by controlling a thickness of an insulating support material formed on the first surface of the substrate, the insulating support material being a material forming the insulating support layer, such that the conductive posts are exposed outside the first insulating support layer away from the upper surface of the substrate without being covered by the first insulating support layer.

In some examples, a second insulating support layer is formed on the first surface of the substrate, and then the second insulating support layer is thinned to expose the conductive pillars away from the upper surface of the substrate, so as to obtain the first insulating support layer. The formed second insulating supporting layer completely covers the conductive columns, the thickness does not need to be accurately controlled when the second insulating supporting layer is formed, the first insulating supporting layer is manufactured in a thinning mode, and the process difficulty is reduced.

Illustratively, the second insulating support layer is thinned by grinding. And polishing the surface of the second insulating support layer far away from the substrate, so that the thickness of the second insulating support layer is reduced, and the upper surface of the conductive column far away from the substrate is exposed from the second insulating support layer.

Optionally, the thickness of the first insulating support layer is the same as the height of the conductive pillars, so that the end surface of the conductive pillar, which is far away from the substrate, is just flush with the surface of the first insulating support layer, which is far away from the substrate.

Optionally, the first insulating support layer is formed by depositing one of amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond.

Alternatively, the conductive pillars are formed on the substrate using the patterned photoresist layer as a mask.

In one possible implementation, a photoresist layer is formed on the first surface, and the photoresist layer has a through hole. And forming a conductive material in the through hole to form the conductive column. And removing the photoresist layer on the first surface.

In the solution shown in the embodiment of the present application, the photoresist layer is used as a mask, and the pattern of the photoresist layer includes a through hole penetrating through the photoresist layer. By forming the conductive material in the via hole due to the presence of the via hole, the conductive post can be formed.

Alternatively, the conductive posts with a large length to diameter ratio are formed by forming the photoresist layer multiple times, each time the photoresist layer is formed, forming a conductive material in the vias.

In some examples, a photoresist layer is formed again on the surface of the formed photoresist layer away from the substrate, and the through hole of the newly formed photoresist layer is communicated with the through hole of the formed photoresist layer. Forming a conductive material in the newly formed via hole of the photoresist layer, lengthening the conductive post.

Based on the method, the photoresist layer is formed on the first surface of the substrate, the photoresist layer is formed again after the conductive column is manufactured, the through hole of the newly formed photoresist layer is communicated with the through hole of the formed photoresist layer, and then the conductive material is formed in the through hole again, so that the length of the conductive column is increased. By repeating this process a plurality of times, the conductive post can be made to reach a larger length even if the diameter of the conductive post is small.

In some examples, a ratio of the length of the conductive post to the diameter of the conductive post is greater than 0 and equal to or less than 20. The related art process may cause defects of the conductive pillars, especially the conductive pillars with a large length-to-diameter ratio, and the larger the length-to-diameter ratio, the more serious the defects of the conductive pillars are, which results in that the length-to-diameter ratio of the conductive pillars may not exceed 8 in general. The process of forming the through hole on the first insulating supporting layer is avoided, so that the defect of the conductive column is avoided, and the conductive column is continuously lengthened in the manner, so that the length of the conductive column is increased by a certain length every time, and the length of the conductive column can reach 10 times or more of the diameter of the conductive column.

In some examples, the minimum pitch between the conductive pillars is 5 μm to 100 μm. In the related art, the process precision of forming the through holes on the insulating support layer is limited, and the minimum distance between the through holes is large, and is usually more than 120 μm, so that the minimum distance between the conductive pillars is also large. In the embodiment of the application, since the precision of the manufacturing process of the photoresist layer is higher, the minimum distance between the through holes of the photoresist layer can reach 20 μm or less, so that the minimum distance between the conductive posts can be greatly reduced, and the distribution density of the conductive posts is improved.

In one possible implementation manner, before forming the first insulating support layer, a blocking layer is formed on the conductive pillar, and the blocking layer covers the surface of the conductive pillar. The conductive pillar is usually a metal, such as copper, the first insulating support layer is formed of one of amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond, and the barrier layer can separate the conductive pillar from the first insulating support layer and prevent the metal material forming the conductive pillar and the insulating support material forming the first insulating support layer from being diffused and adversely affected.

In one possible implementation, after the barrier layer is formed and before the first insulating support layer is formed, a dielectric layer is formed on the conductive pillar, and the dielectric layer covers the barrier layer. The dielectric layer has high resistance and can play an insulating role.

Optionally, the barrier layer and the dielectric layer are formed by deposition.

In some examples, the material forming the barrier layer is silicon nitride. The barrier layer formed by using silicon nitride as a material can have the functions of preventing diffusion and current leakage, so that the structure of a dielectric layer can be omitted.

In a second aspect, embodiments of the present application provide a vertical interconnect structure fabricated using the fabrication method according to the first aspect.

In a third aspect, an embodiment of the present application provides a chip packaging method, where the chip packaging method includes:

and forming the conductive columns on the first surface of the substrate. And forming a first insulating support layer on the first surface, wherein the conductive column is positioned in the first insulating support layer. After the first insulating support layer is formed, a first chip is arranged on the surface, far away from the substrate, of the first insulating support layer. After the first chip is disposed to the first re-wiring layer, the substrate is removed. Based on the method, after the substrate is removed, one end of the conductive column far away from the first chip is exposed, so that the first chip can be connected with the packaging substrate, the printed circuit board or other chips through the conductive column.

In some examples, the method of forming the conductive pillars in the chip packaging method is the same as the method of forming the conductive pillars in the first aspect, and the conductive pillars are also formed on the substrate using the patterned photoresist layer as a mask. The method of forming the first insulating support layer is also the same as the method of forming the first insulating support layer in the first aspect.

Optionally, in the chip packaging method, before forming the first insulating support layer, a barrier layer is formed on the conductive pillar. The barrier layer is formed in the same manner as in the first aspect.

In some examples, a dielectric layer is also formed on the conductive pillars after forming the barrier layer and before forming the first insulating support layer. In the chip packaging method, the method of forming the dielectric layer is also the same as the method of forming the dielectric layer in the first aspect.

In some examples, disposing a first chip on a surface of the first insulating support layer remote from the substrate includes:

and forming a first re-wiring layer on the surface of the first insulation supporting layer far away from the substrate, wherein a first metal wiring in the first re-wiring layer is electrically connected with the conductive column. And arranging the first chip on the surface of the first rewiring layer, which is far away from the first insulating support layer, wherein the first chip is electrically connected with the first metal wiring. Based on the method, the first re-wiring layer is formed to provide a foundation for the subsequent arrangement of the first chip, and the first metal wiring in the first re-wiring layer is used for connecting the first chip and the conductive column, so that the bonding pad of the first chip and the conductive column can be conducted.

In some examples, the second chip is disposed on the first surface of the substrate before the conductive pillars are formed on the first surface of the substrate. Before the first insulating support layer is formed on the first surface, the conductive posts are also formed on the surface of the second chip far away from the substrate, and the conductive posts on the surface of the second chip are electrically connected with the second chip.

Based on the above method, the second chip arranged first occupies a part of the space of the first surface of the substrate, so that when the conductive pillars are formed subsequently, a part of the conductive pillars are formed on the first surface of the substrate, and another part of the conductive pillars can be directly formed on the surface of the second chip and electrically connected with the second chip.

In some examples, disposing a first chip on a surface of the first insulating support layer remote from the substrate includes;

two first chips are arranged on the surface, far away from the substrate, of the first insulating support layer at intervals, one of the first chips is connected with one part of the conductive columns, the other first chip is connected with the other part of the conductive columns, and each first chip is at least electrically connected with one conductive column on the surface of the second chip.

Based on the above method, since a portion of the conductive pillars is formed on the second chip and electrically connected to the second chip, the first chip can be electrically connected to the second chip through the conductive pillars on the surface of the second chip.

In other examples, three or more first chips are disposed on the surface of the first insulating support layer away from the substrate at intervals, at least two of the first chips are electrically connected to the conductive pillars on the surface of the substrate and the conductive pillars on the surface of the second chip, and another part of the first chips are only electrically connected to the conductive pillars on the surface of the substrate.

Based on the method, a plurality of first chips are arranged on the first insulating support layer, and part of the second chips are electrically connected by using the conductive columns on the surface of the second chips and the second chips.

In some examples, after removing the substrate, the chip packaging method further includes:

and connecting the surface of the first insulating support layer, which is far away from the first chip, to a packaging substrate. After the substrate is removed, one end of the conductive column far away from the first chip is exposed. The surface of the first insulating support layer, which is far away from the first chip, is connected to the package substrate, so that the conductive posts are electrically connected with the package substrate, and thus, the first chip is electrically connected with the package substrate.

and arranging a second re-wiring layer on the surface of the first insulating support layer far away from the first chip, wherein a second metal wiring in the second re-wiring layer is electrically connected with the conductive column. Connecting the second re-wiring layer to a package substrate.

Based on the method, after the substrate is removed and one end of the conductive post away from the first chip is exposed, a second redistribution layer is arranged on the surface of the first insulation support layer away from the first chip, and the conductive post can be connected with a part of the package substrate, which needs to be electrically connected, by using a second metal wiring in the second redistribution layer.

In a fourth aspect, the present application provides a packaged chip, and the packaged chip is packaged by using the chip packaging method according to the third aspect.

Drawings

FIG. 1 is a schematic diagram of a vertical interconnect structure;

FIG. 2 is a flow chart of a method of fabricating a vertical interconnect structure provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a process for fabricating a vertical interconnect structure according to an embodiment of the present application;

FIG. 4 is a flow chart of a method of fabricating a vertical interconnect structure provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a process for fabricating a vertical interconnect structure according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a process of lengthening a conductive pillar according to an embodiment of the present disclosure;

fig. 7 is a flowchart of a chip packaging method according to an embodiment of the present application;

fig. 8 is a schematic diagram of a chip packaging process according to an embodiment of the present application;

fig. 9 is a schematic diagram of a chip packaging process according to an embodiment of the present application;

fig. 10 is a schematic diagram of a chip packaging process according to an embodiment of the present application;

fig. 11 is a flowchart of a chip packaging method according to an embodiment of the present application;

fig. 12 is a schematic diagram of a chip packaging process according to an embodiment of the present application.

Detailed Description

Fig. 1 is a schematic diagram of a vertical interconnect structure. As shown in fig. 1, the vertical interconnect structure includes a first insulating support layer 30 and a conductive pillar 20. The first insulating support layer 30 has a plurality of through holes 30a, and the conductive posts 20 are located in the through holes 30 a. The vertical interconnect structure is used for connection in chip packaging, such as connection between a chip and a chip, connection between a chip and a package substrate using the conductive pillars 20.

In the related art, when the vertical interconnect structure is fabricated, a via 30a is formed on the first insulating support layer 30, and then the conductive pillar 20 is formed by electroplating in the via 30 a.

In forming the through-hole 30a, there are two more common methods, one is etching and one is laser ablation.

For etching, SF is generally used₆Plasma etching, however, the etching process cannot control the etching speed of the material in different directions, so that the shape of the through hole formed by etching is generally irregular, multiple times of etching are often required to form a through hole with a large depth, and a C is formed on the inner wall of the through hole after each etching₄F₈The passivation layer is complex in process and low in efficiency, and the inner wall of the finally formed through hole is uneven.

In the laser ablation, the first insulating support layer 30 is irradiated with a high-energy pulsed laser, and the irradiated portion of the first insulating support layer 30 is melted or even directly vaporized, thereby forming a through hole. Since a local high temperature is formed in a laser-irradiated area of the first insulating support layer 30 during the laser ablation process, a heat-affected area is inevitably formed, which may affect the reliability of the packaged chip, and after the laser ablation is finished, a spherical nodule may be formed on the inner wall of the first insulating support layer 30 due to rapid solidification of the material, resulting in a rough hole wall.

The rough hole wall of the through hole 30a may have an adverse effect on the conductive pillar 20, so that a pit or the like appears on the surface of the conductive pillar 20, which finally affects the quality of the vertical interconnection structure, and may have an adverse effect on the normal operation of the packaged chip.

Fig. 2 is a flowchart of a method for fabricating a vertical interconnect structure according to an embodiment of the present disclosure. Fig. 3 is a schematic view illustrating a manufacturing process of a vertical interconnect structure according to an embodiment of the present disclosure. As shown in fig. 2 and 3, the manufacturing method includes:

in step 101, a conductive post 20 is formed on the first surface 10a of the substrate 10.

As shown in a of fig. 3, the conductive post 20 is formed on the first surface 10a of the substrate 10.

In step 102, a first insulating support layer 30 is formed on the first surface 10 a.

As shown in C in fig. 3, a first insulating support layer 30 is formed on the first surface 10 a.

The conductive posts 20 are located in the first insulating support layer 30, and the upper surfaces of the conductive posts 20 far away from the substrate 10 are not covered by the first insulating support layer. The first insulating and supporting layer 30 includes at least one of the following materials: amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond.

In step 103, the substrate 10 is removed.

As shown in fig. 3D, the substrate 10 is removed, resulting in a completed vertical interconnect structure.

In the embodiment of the present invention, when the vertical interconnect structure is fabricated, the conductive pillar 20 is first formed on the first surface 10a of the substrate 10, and then the first insulating support layer 30 is directly formed on the first surface 10a of the substrate 10, because the conductive pillar 20 is formed before the first insulating support layer 30, when the first insulating support layer 30 is formed, the material forming the first insulating support layer 30 can be directly wrapped outside the conductive pillar 20, so that the conductive pillar 20 is directly embedded in the first insulating support layer 30, and the fabrication of the through hole on the first insulating support layer is not required in the whole fabrication process, thereby avoiding adverse effects caused by the process of fabricating the through hole.

In the embodiment of the present application, the first insulating support layer 30 is formed of at least one material selected from amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond. These materials enable the first insulating support layer 30 to be formed with good heat dissipation capability and sufficient structural strength to maintain the vertical interconnect structure in a certain shape.

In some examples, the conductive posts 20 are exposed outside the first insulating support layer 30 away from the upper surface of the substrate 10 without being covered by the first insulating support layer 30 by controlling the thickness of the material formed on the first surface 10a of the substrate 10 in step 102, where the material is the material forming the first insulating support layer 30.

For example, when the first insulating support layer 30 is formed by deposition, under the condition that the deposition rate is constant, the deposition time is controlled, so as to control the thickness of the deposited insulating support material, so that the upper surface of the conductive pillar 20 away from the substrate 10 is just flush with the surface of the first insulating support layer 30 away from the substrate 10, and is not covered by the first insulating support layer 30.

In other examples, the second insulating support layer 30 'with a larger thickness is formed on the first surface 10a of the substrate 10, and then the first insulating support layer 30 with a smaller thickness is obtained by thinning the second insulating support layer 30'.

As shown in fig. 3B, a second insulating support layer 30 'is formed on the first surface 10a of the substrate 10, and the second insulating support layer 30' covers the conductive posts 20. The second insulating support layer 30' is thinned to expose the upper surfaces of the conductive posts 20 away from the substrate 10, so as to obtain the first insulating support layer 30. The thickness of the deposit does not need to be precisely controlled and the process is relatively simpler.

Alternatively, the first insulating support layer 30 and the second insulating support layer 30' are both formed by deposition. Such as plasma enhanced chemical vapor deposition.

Fig. 4 is a flowchart of a method for fabricating a vertical interconnect structure according to an embodiment of the present disclosure. Fig. 5 is a schematic view illustrating a manufacturing process of a vertical interconnect structure according to an embodiment of the present disclosure. As shown in fig. 4 and 5, the manufacturing method includes:

in step 201, the substrate 10 is pretreated.

In some examples, the substrate 10 is a glass substrate or a silicon substrate.

Optionally, the pre-treatment comprises cleaning the substrate 10. For example, the substrate 10 is ultrasonically cleaned with a cleaning agent, and then the substrate 10 is blow-dried with nitrogen gas. Wherein, the cleaning agent comprises at least one of acetone, isopropanol and deionized water. The stains on the surface of the substrate 10 are removed by cleaning, so that the stains are prevented from having adverse effects on the subsequent manufacturing process.

In step 202, the first surface 10a of the substrate 10 forms a peeling layer 11.

As shown in B in fig. 5, the first surface 10a of the substrate 10 is formed with a peeling layer 11, and the peeling layer 11 facilitates removal of the substrate 10 in a subsequent step.

Illustratively, the release layer 11 is a temporary bonding paste, and the thickness of the release layer 11 is 25 μm to 100 μm.

In step 203, an adhesive layer 12 and a seed layer (seed layer)13 are formed in this order on the surface of the peeling layer 11.

As shown in fig. 5C, the bonding layer 12 is located between the peeling layer 11 and the seed layer 13, the bonding layer 12 can improve the adhesion of the seed layer 13, and prevent the seed layer 13 from separating from the peeling layer 11, and the seed layer 13 can facilitate the formation of the conductive post 20 in a subsequent step by electroplating.

In some examples, the adhesion layer 12 is formed by Physical Vapor Deposition (PVD), and the seed layer 13 is formed on the surface of the substrate 10 by Chemical Vapor Deposition (CVD).

Illustratively, the adhesion layer 12 is formed of titanium Ti metal, and the thickness of the adhesion layer 12 is 2nm to 500 nm. The seed layer 13 is formed of copper Cu, and the thickness of the seed layer 13 is 30nm to 500 nm.

In step 204, a photoresist layer 40 is formed on the first surface 10a of the substrate 10.

As shown in D of fig. 5, the photoresist layer 40 has a through hole 40 a.

Illustratively, the photoresist layer 40 is formed on the first surface 10a of the substrate 10 through a patterning process. A layer of photoresist is first coated on the first surface 10a of the substrate 10, and then the photoresist is cured through exposure and development to form the photoresist layer 40 having the through hole 40 a.

In step 205, a conductive material is formed in the via 40a, forming the conductive post 20.

In some examples, the conductive material is a metallic material, such as metallic copper.

Alternatively, the conductive post 20 is formed in the through hole 40a using an electroplating process. In the electroplating process, the seed layer 13 is used as an electrode, so that a conductive material is continuously deposited on the surface of the seed layer 13 in the through hole 40a, and finally the through hole 40a is filled.

In step 206, the photoresist layer 40 on the first surface 10a is removed.

After removing the photoresist layer 40, the conductive pillars 20 formed on the first surface 10a are exposed, as shown by F in fig. 5.

Optionally, after the conductive pillars 20 are formed, the adhesive layer 12 and the seed layer 13 are etched, and portions of the adhesive layer 12 and the seed layer 13 between the conductive pillars 20 are removed. This eliminates the need to remove the adhesion layer 12 and the seed layer 13 after subsequent removal of the substrate 10.

In step 207, barrier layer 50 is formed.

As shown at G in fig. 5, the barrier layer 50 covers the surface of the conductive post 20. Covering the surface of the conductive post 20 with the barrier layer 50 can separate the conductive post 20 from the first insulating support layer 30 to be formed in the subsequent step, and prevent the metal material constituting the conductive post 20 and the insulating support material constituting the first insulating support layer 30 from being diffused and adversely affected.

In some examples, the barrier layer 50 is formed using a chemical vapor deposition method or an Atomic Layer Deposition (ALD) method. For example, the barrier layer 50 is deposited on the surface of the conductive pillar 20 by Plasma Enhanced Chemical Vapor Deposition (PECVD).

Optionally, the barrier layer 50 has a thickness of 2nm to 100 nm. The barrier layer 50 has an isolation effect which is dependent on the material forming the barrier layer 50 and the thickness of the barrier layer 50, the thicker the barrier layer 50 the better the isolation effect for the same material, and the barrier layer 50 is provided with a corresponding thickness in accordance with the isolation effect to be achieved for a given material. In some examples, the barrier layer 50 has a thickness of 2nm to 20nm, and a thinner barrier layer 50 has been able to produce sufficient isolation for a material with better isolation. In the present embodiment, the thickness of the barrier layer 50 is 5 nm.

Optionally, the material forming the barrier layer 50 is Ti, W, Ta, TiN, Pt, TaN, TiW, Si₃N₄At least one of (1).

Illustratively, after depositing the material forming the barrier layer 50, the deposited material is etched, leaving the material covering the surfaces of the conductive pillars 20.

In step 208, a dielectric layer 60 is formed on the surface of the barrier layer 50.

As shown at H in fig. 5, a dielectric layer 60 covers the surface of the barrier layer 50. The dielectric layer 60 can perform an insulating function, so that the conductive pillar 20 is insulated from the first insulating support layer 30 to be formed in a subsequent step, and the vertical interconnection structure is prevented from having poor problems such as electric leakage.

In some examples, dielectric layer 60 is formed using the same method as barrier layer 50, such as using a chemical vapor deposition method or an atomic layer deposition method to form dielectric layer 60.

Optionally, the dielectric layer 60 has a thickness of 3nm to 200 nm. The insulating ability of the dielectric layer 60 is dependent on the material from which the dielectric layer 60 is formed and the thickness of the dielectric layer 60, the thicker the thickness of the dielectric layer 60, the stronger the insulating ability of the dielectric layer 60 for the same material, and the corresponding thickness of the dielectric layer 60 is set in accordance with the insulating ability to be achieved for a given material. For better insulating materials, a thinner dielectric layer 60 has been able to produce sufficient insulating capability, in the present embodiment, the thickness of the dielectric layer 60 is 10 nm.

Optionally, the insulating material forming the dielectric layer 60 is SiO₂，Al₂O₃，HfO₂，Si₃N₄，Al₂O₃Of AlNAt least one of them.

Illustratively, after depositing the material forming the dielectric layer 60, the deposited material is etched, leaving the material overlying the conductive posts 20. In addition, in other embodiments, the barrier layer 50 and the dielectric layer 60 are etched together, and the material covering the conductive pillars 20 is remained, so as to reduce one etching process.

In some examples, if the material forming the barrier layer 50 is Si in step 204₃N₄The dielectric layer 60 may be omitted and accordingly, in the method of manufacturing the vertical interconnect structure, the step 205 is omitted. This is because of Si₃N₄The barrier layer 50 formed of a material has both diffusion prevention and current leakage prevention functions. Of course, even with Si₃N₄The barrier layer 50 is formed by a material, and a dielectric layer 60 is further provided to further enhance the insulating effect and prevent current leakage.

In step 209, a second insulating support layer is formed on the first surface of the substrate.

As shown in fig. 5I, a second insulating support layer 30' is formed on the first surface 10a of the substrate 10.

In the present embodiment, the second insulating support layer 30' is formed by deposition. For example, the second insulating support layer 30' is formed using plasma enhanced chemical vapor deposition.

The material forming the second insulating support layer 30' is at least one of amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, diamond. For example, polysilicon is used as the material, and an insulating support material, i.e., polysilicon material, is deposited on the first surface 10a of the substrate 10, and a thickness of the insulating support material is deposited to form the second insulating support layer 30'.

Illustratively, when the insulating support material is deposited, the radio frequency is 13.5 MHz-90 MHz, the radio frequency power is 20W-1000W, and the reaction temperature is 140-400 ℃.

In the embodiment of the application, monocrystalline silicon is used as a target material, the purity is 99.99%, the sputtering gas is Ar, and the purity is 99.99%.

Alternatively, when the second insulating support layer 30' is formed, the raw material gas is SiH₄、SiH₂Cl₂，SiHCl₃And SiF₄At least one of (1). The raw material gas is mixed with catalytic gas H₂And a diluent gas Ar.

In step 210, the second insulating support layer 30' is thinned to expose the conductive pillars 20, so as to obtain the first insulating support layer 30.

As shown by J in fig. 5, the second insulating support layer 30' is thinned, resulting in the first insulating support layer 30, and the conductive posts 20 are exposed from the first insulating support layer 30 away from the upper surface of the substrate 10.

In the embodiment of the present application, the second insulating support layer 30 ' is polished from the upper surface of the second insulating support layer 30 ' away from the substrate 10, so as to reduce the thickness of the second insulating support layer 30 ', and expose the conductive pillars 20 away from the upper surface of the substrate 10.

Alternatively, by controlling the thickness of the material formed on the first surface 10a of the substrate 10, which is the material for forming the first insulating support layer 30, the conductive posts 20 are not covered away from the upper surface of the substrate 10, so that the first insulating support layer 30 is directly manufactured without thinning, and the material is saved from the viewpoint of material consumption.

Optionally, the thickness of the first insulating support layer 30 is the same as the height of the conductive pillars 20, that is, two end surfaces of the conductive pillars 20 are just flush with two surfaces of the first insulating support layer 30, so that the conductive pillars 20 are conveniently electrically connected with the chip, the package substrate, the redistribution layer, and the like.

In step 211, the substrate is removed.

After removing the substrate 10, a completed vertical interconnect structure is obtained, as indicated by K in fig. 5.

In the present embodiment, before step 201, the peeling layer 11 has been formed on the first surface 10a of the substrate 10, and the substrate 10 is separated from the first insulating support layer 30 by causing the peeling layer 11 to lose its adhesiveness. Illustratively, the release layer 11 is a temporary bonding paste, and the substrate 10 is separated by debonding the temporary bonding paste. Alternatively, the substrate 10 is thinned to remove the substrate.

In other examples, the formed conductive pillars 20 are also lengthened prior to step 206. By lengthening the conductive posts 20, the length of the conductive posts 20 is longer, and the design requirements are met. Fig. 6 is a schematic diagram of a process for lengthening the conductive pillar according to an embodiment of the present disclosure, and at least the peeling layer 11, the adhesive layer 12, the seed layer 13, the barrier layer 50, and the dielectric layer 60 are omitted in fig. 6. As shown in fig. 6, in the embodiment of the present application, the conductive post 20 is lengthened as follows:

the method comprises the following steps: the photoresist layer 40 is formed again on the surface of the formed photoresist layer 40 away from the substrate 10, and the through-hole 40a of the newly formed photoresist layer 40 communicates with the through-hole 40a of the formed photoresist layer 40.

Step two: conductive material is formed in the newly formed via holes 40a of the photoresist layer 40, lengthening the conductive pillars 20.

As shown in a of fig. 6, after step 205 is performed, a photoresist layer 40 with a certain thickness and a conductive pillar 20 with a certain height are formed on the first surface 10a of the substrate 10. After step 205, as shown in B of fig. 6, the thickness of the total photoresist formed is increased by performing step one. As shown in fig. 6C, in the second step, by forming the conductive material again, since the through hole 40a of the photoresist layer 40 formed in the first step is communicated with the through hole 40a formed before, the conductive material formed again may be deposited on the conductive pillar 20 formed already, and the conductive material formed in the second step also becomes a part of the conductive pillar 20, so that the length of the conductive pillar 20 is increased. As an example, only the case where step one and step two are performed once is shown in fig. 6. After the conductive pillars 20 are completely lengthened, the conductive pillars 20 are exposed after all of the photoresist layer 40 is removed, as shown at D in fig. 6.

In the embodiment of the present application, by repeating step one and step two for a plurality of times, the length of the conductive pillar 20 can be further lengthened, so as to form a conductive pillar 20 with a larger ratio of length to diameter. For example, before step 203, step one and step two are performed once to lengthen the length of the conductive pillar 20, and step one and step two are performed again to lengthen the length of the conductive pillar 20 again.

Optionally, the ratio of the length of the conductive pillar 20 to the diameter of the conductive pillar 20 is greater than 0 and equal to or less than 20. By repeating the first and second steps a and b a plurality of times, the ratio of the length to the diameter of the conductive post 20 can be enlarged.

The vertical interconnect structure fabricated by the related art process method is limited by the precision of the process for forming the via hole on the insulating support layer, the conductive pillar has a generally small length-to-diameter ratio, and the larger the length-to-diameter ratio, the more serious the defect of the fabricated conductive pillar is, which results in that the length-to-diameter ratio of the conductive pillar is generally not more than 8. In the embodiment of the present application, the first step and the second step are repeatedly performed to lengthen the conductive pillar 20 for multiple times, so that the ratio of the length to the diameter of the conductive pillar 20 can reach a relatively large range. Illustratively, the ratio of the length of the conductive post 20 to the diameter of the conductive post 20 is 15: 1 to 12: 1.

In some examples, the photoresist layer 40 formed in step 201 and step one each has a thickness of 30 μm to 50 μm. The thicker the thickness of the photoresist layer 40, the longer the through-hole 40a to be formed, and the lower the accuracy of the through-hole 40a, in each process of forming the photoresist layer 40. The thickness of the photoresist layer 40 formed each time is limited to 30 μm to 50 μm, so that the length of the through hole 40a formed each time is only 30 μm to 50 μm, and the influence on the formation of the conductive post 20 due to the low precision of the through hole 40a is avoided.

Optionally, the minimum pitch between the conductive pillars 20 is 5 μm to 100 μm. That is, the pitch between the nearest conductive posts 20 is 5 μm to 100 μm. As an example, in the embodiment of the present application, the minimum pitch between the conductive pillars 20 is 10 μm to 20 μm.

In the related art, the process precision of forming the through holes on the insulating support layer is limited, and the distance between adjacent through holes is relatively large, usually more than 120 μm, which results in that the distance between the conductive pillars in the formed vertical interconnection structure is relatively large, so that the distribution density of the conductive pillars is relatively small. In the embodiment of the present application, since the vias 40a are formed on the photoresist layer 40, and the process for forming the vias 40a on the photoresist layer 40 has a much higher precision than the process for forming the vias on the insulating support layer, the more densely distributed vias 40a can be formed on the photoresist layer 40, so that the vertical interconnect structure can be obtained in which the conductive pillars 20 are distributed at a higher density and the minimum distance between the conductive pillars 20 can be set smaller.

The embodiment of the present application also provides a vertical interconnect structure manufactured by the manufacturing method shown in fig. 2 or 4.

An embodiment of the present application further provides a chip packaging method, and fig. 7 is a flowchart of the chip packaging method provided in the embodiment of the present application. Fig. 8 is a schematic diagram of a chip packaging process according to an embodiment of the present application. With reference to fig. 7 and 8, the method includes:

in step 301: conductive post 20 is formed on first surface 10a of substrate 10.

As shown in a of fig. 8, the conductive post 20 is formed on the first surface 10a of the substrate 10.

In step 302: a first insulating support layer 30 is formed on the first surface 10 a.

As shown in fig. 8C, the conductive posts 20 are located in the insulating support layer 30, and the upper surfaces of the conductive posts 20 away from the substrate 10 are not covered by the first insulating support layer 30.

In the present embodiment, the first insulating support layer 30 includes at least one of the following materials: amorphous silicon, polysilicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond.

In some examples, the first insulating support layer 30 is prepared by forming the second insulating support layer 30 'on the first surface 10a, and then thinning the second insulating support layer 30' to expose the conductive pillars 20.

As shown in fig. 8B and C, the second insulating support layer 30 'is formed to cover the upper surfaces of the conductive posts 20 away from the substrate 10, and after thinning the second insulating support layer 30', the upper surfaces of the conductive posts 20 away from the substrate 10 are exposed.

In the embodiment of the present application, the formation of the conductive pillar 20 and the formation of the first insulating support layer 30 refer to the steps before the substrate is removed in the manufacturing method of the vertical interconnect structure shown in fig. 2, or refer to the steps before the substrate is removed in the manufacturing method of the vertical interconnect structure shown in fig. 4, and are not described again here.

In step 303: the first chip 81 is disposed on the surface of the first insulating support layer 30 away from the substrate 10.

In step 304: the substrate 10 is removed.

As shown at F in fig. 8, the substrate 10 is removed, exposing the ends of the conductive posts 20.

Optionally, after the substrate 10 is removed, a Chemical Mechanical Polishing (CMP) is performed on the surface of the first insulating support layer 30 away from the first chip 81, so as to make the surface of the first insulating support layer 30 flat and smooth and ensure that the conductive pillars 20 can be exposed.

In the embodiment of the present invention, the conductive pillar 20 is formed on the first surface 10a of the substrate 10, and then the first insulating support layer 30 is directly formed on the first surface 10a of the substrate 10, because the conductive pillar 20 is formed before the first insulating support layer 30, when the first insulating support layer 30 is formed, the material forming the first insulating support layer 30 directly wraps the conductive pillar 20, so that the conductive pillar 20 is directly embedded in the first insulating support layer 30. In the whole manufacturing process, the through hole 40a does not need to be manufactured on the first insulating support layer 30, so that adverse effects caused by the process for manufacturing the through hole 40a are avoided.

Alternatively, as shown in D and E in fig. 8, the disposing the first chip 81 on the surface of the first insulating support layer 30 away from the substrate 10 in step 303 includes:

a first re-wiring layer 71 is formed on the surface of the first insulating support layer 30 remote from the substrate 10.

The first chip 81 is disposed on the surface of the first re-wiring layer 71 away from the first insulating support layer 30. The first metal wire 711 in the first redistribution layer 71 is electrically connected to the conductive pillar 20, and the first chip 81 is electrically connected to the first metal wire 711.

As shown in D in fig. 8, by forming the first re-wiring layer 71 first, a basis is provided for the arrangement of the first chip 81. As shown in E in fig. 8, the first metal wiring 711 in the first re-wiring layer 71 is used to connect the first chip 81 and the conductive pillar 20, so that the pad of the first chip 81 and the conductive pillar 20 can be electrically connected.

Alternatively, the surface of the first re-wiring layer 71 away from the first insulating support layer 30 is provided with two or more first chips 81. The number of first chips 81 provided on the first re-wiring layer 71 is set according to a specific chip packaging structure.

Fig. 9 is a schematic diagram of a chip packaging process according to an embodiment of the present application. In some examples, as shown in a and B in fig. 9, after the first re-wiring layer 71 is disposed away from the surface of the first insulating support layer 30, an underfill (underfill)91 is formed between the first chip 81 and the first re-wiring layer 71. The underfill 91 can enhance at least the heat exchange between the first chip 81 and the first re-wiring layer 71, and also reduce the possibility of disconnection between the first chip 81 and the first re-wiring layer 71 when the chip package structure is subjected to an impact of an external force, such as dropping.

As shown in B in fig. 9, after the underfill 91 is formed, the first chip 81 is also subjected to plastic molding.

As an example, a polymer molding material 92 is covered on the first re-wiring layer 71, and the first chip 81 is wrapped by the polymer molding material 92. Illustratively, the polymeric molding material 92 includes a resin. The first chip 81 is covered by the polymer molding material 92, which can protect the first chip 81.

Referring to fig. 8, in some examples, after the substrate 10 is removed in step 304, the surface of the first insulating support layer 30 remote from the first chip 81 is connected to the package substrate 90.

As shown in fig. 9C, after the substrate 10 is removed, one end of the conductive post 20 away from the first chip 81 is exposed, and the first chip 81 is connected to the package substrate 90 by the conductive post 20. Illustratively, the conductive posts 20 and the package substrate 90 are soldered by solder balls.

Fig. 10 is a schematic diagram of a chip packaging process according to an embodiment of the present application. As shown in fig. 10, in some examples, as shown in a in fig. 10, after the substrate 10 is removed in step 304, the second re-wiring layer 72 is provided on the surface of the first insulating support layer 30 away from the first chip 81. As shown in B in fig. 10, the second re-wiring layer 72 is connected to the package substrate 90. The second metal wiring 721 in the second redistribution layer 72 is electrically connected to the conductive pillar 20.

After removing the substrate 10, the first insulating support layer 30 is not directly connected to the package substrate 90, but the second redistribution layer 72 is first fabricated and then connected to the package substrate 90 by using the second redistribution layer 72. The conductive pillars 20 are enabled to form connections with pads on the package substrate 90 by the second metal wirings 721 in the second re-wiring layer 72.

Fig. 11 is a flowchart of a chip packaging method according to an embodiment of the present application. Fig. 12 is a schematic diagram of a chip packaging process according to an embodiment of the present application. With reference to fig. 11 and 12, the method includes:

in step 401: the second chip 82 is disposed on the first surface 10a of the substrate 10.

In some examples, the second chip 82 is a silicon bridge chip. The surface of the second chip 82 remote from the substrate 10 has pads for electrical connection of the second chip 82.

The second chip 82 is disposed on the first surface 10a of the substrate 10 to occupy a certain space, so that the photoresist layer formed in the subsequent step can cover the substrate 10 and the second chip 82, and when the conductive pillars 20 are formed, a part of the conductive pillars 20 can be formed on the surface of the second chip 82.

Optionally, the first surface 10a of the substrate 10 is provided with a temporary bonding adhesive to facilitate the adhesion of the second chip 82 to the substrate 10 and also to facilitate the separation of the substrate 10 in subsequent steps.

In step 402: the conductive post 20 is formed on the first surface 10a of the substrate 10, and the conductive post 20 is also formed on the surface of the second chip 82 away from the substrate 10.

The conductive posts 20 on the surface of the second chip 82 are electrically connected to the second chip 82.

As shown in a in fig. 12, before the conductive pillar 20 is formed, at least the seed layer 13 is also formed on the surfaces of the substrate 10 and the second chip 82.

Since the second chip 82 is disposed on the surface of the substrate 10 before the conductive pillars 20 are formed, the second chip 82 occupies a part of the space, so that a part of the conductive pillars 20 can be formed on the second chip 82.

The method for forming the conductive pillars 20 in step 402 refers to steps 202-206 of the aforementioned method.

In the embodiment of the present application, in the process of forming the conductive pillars 20, on the surface of the second chip 82 far from the substrate 10, an orthogonal projection of a portion of the through hole of the photoresist layer at least partially coincides with the pad on the surface of the second chip 82, so that the conductive pillars 20 formed on the surface of the second chip 82 can be electrically connected to the pad on the surface of the second chip 82.

In step 403: the seed layer 13 on the surface of the second chip 82 is removed.

As shown in step 203, before the photoresist layer 40 is formed, the seed layer 13 is formed on the surface of the substrate 10 to form the conductive pillar 20 by electroplating. In the subsequent step, after the substrate 10 is removed, the seed layer 13 may be removed, but the portion of the seed layer 13 covering the surface of the second chip 82 cannot be removed after the substrate 10 is removed, and as shown in fig. 12B, the portion of the seed layer 13 covering the surface of the second chip 82 also integrally connects all the conductive pillars 20 located on the surface of the second chip 82, and the portion of the seed layer 13 covering the surface of the second chip 82 is processed in step 403.

In some examples, as shown in fig. 12C, the seed layer 13 is etched to remove portions of the seed layer 13 between the conductive pillars 20, so as to avoid short circuits between the conductive pillars 20 caused by the seed layer 13.

In the embodiment of the present application, when the seed layer 13 is etched, at least a portion of the seed layer 13 on the surface of the second chip 82 is etched. The portion of the seed layer 13 on the first surface 10a of the substrate 10 may be removed after the subsequent removal of the substrate 10 even if etching is not performed in step 403.

Optionally, after removing the seed layer on the surface of the second chip 82, the barrier layer 50 is formed on the surface of the conductive pillar 20, or the barrier layer 50 and the dielectric layer 60 are sequentially formed. The barrier layer 50 is formed in step 207 and the dielectric layer 60 is formed in step 208.

In step 404: a second insulating support layer 30' is formed on the first surface 10 a.

In the present embodiment, the second insulating support layer 30' is formed in step 404 by referring to step 209.

In step 405: the second insulating support layer 30' is thinned to expose the conductive pillars 20, so as to obtain the first insulating support layer 30.

In the present embodiment, the manner of thinning the second insulating support layer 30' in step 405 is described with reference to step 210 above.

In some examples, the first insulating support layer 30 can be directly manufactured by controlling the thickness of the material formed on the first surface 10a of the substrate 10, where the material is the material forming the first insulating support layer 30, and the conductive post 20 is not covered with the material far from the upper surface of the substrate 10, so that the material is saved in terms of material consumption without being thinned.

In step 406: two first chips 81 are disposed at an interval on the surface of the first insulating support layer 30 away from the substrate 10.

As shown in fig. 12F, one of the first chips 81 is connected to a portion of the conductive pillars 20, the other first chip 81 is connected to another portion of the conductive pillars 20, and each first chip 81 is electrically connected to at least one conductive pillar 20 on the surface of the second chip 82.

Since the conductive pillars 20 electrically connected to the pads of the second chip 82 are formed on the surface of the second chip 82 away from the substrate 10 in the foregoing step 402, the disposed first chip 81 can be electrically connected to the second chip 82 through the conductive pillars 20 on the surface of the second chip 82.

The number of the first chips 81 is set according to a specific structure of the packaged chips. For example, in other examples, three or more first chips 81 are spaced apart from the surface of the first insulating support layer 30 away from the substrate 10. At least two of the first chips 81 are electrically connected to the conductive pillars 20 on the surface of the substrate 10, and are also electrically connected to the conductive pillars 20 on the surface of the second chip 82.

As shown in fig. 12, after the first chip 81 is disposed on the first insulating support layer 30, an underfill 91 is formed between the first chip 81 and the first insulating support layer 30, so as to reduce the possibility of disconnection between the first chip 81 and the first insulating support layer 30.

In step 407: the substrate 10 is removed.

In some examples, as shown at H in fig. 12, after the substrate 10 is removed in step 407, the surface of the first insulating support layer 30 remote from the first chip 81 is connected to the package substrate 90.

Optionally, the substrate 10 is removed by thinning the substrate 10. Or the temporary bonding glue is debonded to remove the substrate 10.

Optionally, after the substrate 10 is removed, the surface of the first insulating support layer 30 away from the first chip 81 is subjected to chemical mechanical polishing, so that the surface of the first insulating support layer 30 away from the first chip 81 is flat and smooth, and the conductive posts 20 can be ensured to be exposed.

After the substrate 10 is removed, one end of the conductive pillar 20 away from the first chip 81 is exposed, and the first chip 81 is connected to the package substrate 90 by using the conductive pillar 20. Illustratively, the conductive posts 20 and the package substrate 90 are soldered by solder balls.

In some examples, after the substrate 10 is removed in step 407, a second re-wiring layer 72 is also provided. For example, referring to fig. 10, the second re-wiring layer 72 is provided on the surface of the first insulating support layer 30 away from the first chip 81; the first insulating support layer 30 is connected to the package substrate 90. The second metal wiring 721 in the second redistribution layer 72 is electrically connected to the conductive pillar 20.

The embodiment of the application also provides a packaged chip, and the packaged chip is packaged by adopting any one of the chip packaging methods shown in fig. 7 or fig. 11.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of "first," second, "" third, "and the like in the description and in the claims does not denote any order, quantity, or importance, but rather the terms first," "second," and the like are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes.

The above description is only one embodiment of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of fabricating a vertical interconnect structure, comprising:

forming a conductive post (20) on a first surface (10a) of a substrate (10);

forming a first insulating support layer (30) on said first surface (10a), said conductive posts (20) being located within said first insulating support layer (30), said first insulating support layer (30) comprising at least one of the following materials: amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride and diamond, the upper surface of the conductive column (20) away from the substrate (10) is not covered by the first insulating support layer (30);

removing the substrate (10).

2. The manufacturing method according to claim 1, wherein the forming of the conductive pillar (20) on the first surface (10a) of the substrate (10) comprises:

forming a photoresist layer (40) on the first surface (10a), wherein the photoresist layer (40) is provided with a through hole (40 a);

forming a conductive material in the via (40a), forming the conductive post (20);

the photoresist layer (40) on the first surface (10a) is removed.

3. Manufacturing method according to claim 2, characterized in that, before removing the photoresist layer (40) located at the first surface (10a), the following procedure is performed at least once:

forming a photoresist layer (40) again on the surface of the formed photoresist layer (40) far away from the substrate (10), wherein the through hole (40a) of the newly formed photoresist layer (40) is communicated with the through hole (40a) of the formed photoresist layer (40);

forming a conductive material in the newly formed via hole (40a) of the photoresist layer (40) to lengthen the conductive post (20).

4. A method of manufacturing according to any one of claims 1 to 3, further comprising, before forming the first insulating support layer (30) on the first surface (10 a):

forming a barrier layer (50), wherein the barrier layer (50) covers the surface of the conductive column (20).

5. The manufacturing method according to claim 4, further comprising, before forming the first insulating support layer (30) on the first surface (10 a):

after forming the barrier layer (50), a dielectric layer (60) is formed on the surface of the barrier layer (50).

6. The manufacturing method according to any one of claims 1 to 5, wherein forming a first insulating support layer (30) on the first surface (10a) includes:

-forming a second insulating supporting layer (30 ') on said first surface (10a), said second insulating supporting layer (30') covering said conductive studs (20);

and thinning the second insulating support layer (30') to expose the upper surface of the conductive column (20) far away from the substrate (10), thereby obtaining the first insulating support layer (30).

7. The manufacturing method according to any one of claims 1 to 6, wherein the thickness of the first insulating support layer (30) is the same as the height of the conductive pillar (20).

8. A manufacturing method according to any one of claims 1 to 7, wherein the first insulating support layer (30) is formed by deposition.

9. The manufacturing method according to any one of claims 1 to 8, wherein a ratio of the length of the conductive post (20) to the diameter of the conductive post (20) is greater than 0 and equal to or less than 20.

10. The manufacturing method according to any one of claims 1 to 9, wherein a minimum pitch between the conductive posts (20) is 5 μm to 100 μm.

11. A vertical interconnect structure manufactured by the method according to any one of claims 1 to 10.

12. A method of chip packaging, comprising:

forming a conductive post (20) on a first surface (10a) of a substrate (10);

arranging a first chip (81) on the surface of the first insulating support layer (30) far away from the substrate (10);

removing the substrate (10).

13. The chip packaging method according to claim 12, wherein disposing the first chip (81) on the surface of the first insulating support layer (30) away from the substrate (10) comprises:

forming a first redistribution layer (71) on the surface of the first insulation support layer (30) far away from the substrate (10), wherein a first metal wiring (711) in the first redistribution layer (71) is electrically connected with the conductive column (20);

and arranging the first chip (81) on the surface of the first re-wiring layer (71) far away from the first insulating support layer (30), wherein the first chip (81) is electrically connected with the first metal wiring (711).

14. The chip packaging method according to claim 12, further comprising:

providing a second chip (82) on the first surface (10a) of the substrate (10) before forming the conductive post (20) on the first surface (10a) of the substrate (10);

before the first insulating support layer (30) is formed on the first surface (10a), the conductive posts (20) are also formed on the surface of the second chip (82) away from the substrate (10), and the conductive posts (20) on the surface of the second chip (82) are electrically connected with the second chip (82);

-providing a first chip (81) on a surface of said first insulating support layer (30) remote from said substrate (10), including;

two first chips (81) are arranged on the surface of the first insulating support layer (30) far away from the substrate (10) at intervals, wherein one first chip (81) is connected with one part of the conductive columns (20), the other first chip (81) is connected with the other part of the conductive columns (20), and each first chip (81) is electrically connected with at least one conductive column (20) on the surface of the second chip (82).

15. The chip packaging method according to any one of claims 12 to 14, further comprising:

connecting the surface of the first insulating support layer (30) away from the first chip (81) to a package substrate (90).

16. The chip packaging method according to any one of claims 12 to 14, further comprising:

arranging a second re-wiring layer (72) on the surface of the first insulation supporting layer (30) far away from the first chip (81), wherein a second metal wiring (721) in the second re-wiring layer (72) is electrically connected with the conductive column (20);

connecting the second re-wiring layer (72) to a package substrate (90).

17. The chip packaging method according to any one of claims 12 to 16, wherein forming a first insulating support layer (30) on the first surface (10a) comprises:

18. The chip packaging method according to any one of claims 12 to 17, wherein the thickness of the first insulating support layer (30) is the same as the height of the conductive pillar (20).

19. A packaged chip, wherein the packaged chip is packaged by the chip packaging method according to any one of claims 12 to 18.