CN101814477B - A Silicon through holes after the interlinked structure being passivated. - Google Patents
A Silicon through holes after the interlinked structure being passivated. Download PDFInfo
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- CN101814477B CN101814477B CN201010119558.3A CN201010119558A CN101814477B CN 101814477 B CN101814477 B CN 101814477B CN 201010119558 A CN201010119558 A CN 201010119558A CN 101814477 B CN101814477 B CN 101814477B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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Abstract
This invention discloses a integrated circuit structure which utilizing the interlinked structure to form silicon through holes after passivating treatment. Said structure includes: a semiconductor underlay; silicon through holes extending in the semiconductor underlay; a solder plate formed on the upside of the semiconductor underlay and separated from the TSV; a interlinked structure formed on the upside of the semiconductor underlay and electrically connected with the TSV and a solder plate. Said interlinked structure includes an upper side part formed on the upside of the solder plate and a downside part being adjacent with the solder plate, and the upper side part extends to electrically connected with the TSV.
Description
The cross reference of related application
The present invention requires in the priority of the U.S. Provisional Application 61/154,979 of submission on February 24th, 2009, and its full content is hereby expressly incorporated by reference.
Technical field
One or more embodiment relate to the manufacturing of semiconductor device, more specifically, relate to the manufacturing of (post passivation) interconnection structure after silicon through hole and the passivation.
Background technology
Semi-conductor industry has experienced the fast development that continues owing to the continuous improvement of the integration density of various electronic units (for example, transistor, diode, resistor, capacitor etc.).Largely, this improvement of integration density be derived from the minimal parts size repeat reduce, make more parts be integrated in the given chip area.These integrated improvement are two dimension (2D) in essence, promptly are integrated volume that parts take mainly on the surface of semiconductor wafer.Although the remarkable improvement that the significant improvement of photoetching causes the 2D integrated circuit to form is for having physical restriction the density of two dimension realization.A kind of being limited in need make minimized in size to these parts.In addition, when more device being placed in the chip, need more complicated design.The increase that other are limited in along with number of devices, the remarkable increase of quantity that interconnects between the device and length.When quantity that interconnects and length increase, circuit RC postpones and power consumption all can increase.In the effort that is used for solving above-mentioned restriction, use three dimensional integrated circuits (3DIC) and stack chip usually.
Thus, silicon through hole (TSV) is used in 3DIC and the stack chip that is used for being connected tube core.In this case, TSV is generally used for the integrated circuit on the tube core is connected to the dorsal part of tube core.In addition, TSV also is used to provide the short circuit grounding path, and it is used for making integrated circuit ground connection through the die backside that is grounded the metal film covering.Integrated circuit generally includes the contact area that is used for integrated circuit is connected to other circuit.Contact combine (contact-bonding, CB) pad is formed in the metal level (that is, the top layer of metal) usually, it interconnects after through passivation, and (post passivation interconnect, PPI) structure is connected to TSV.Yet traditional P PI technology provides the weak adhesion to CB, and causes high contact impedance.Therefore, need improved structure and preparation method thereof to overcome the shortcoming of traditional handicraft.
Summary of the invention
One or more disclosed embodiment have described a kind of integrated circuit structure, and this structure comprises: Semiconductor substrate; Silicon through hole (TSV) extends in the Semiconductor substrate; Pad is formed on the Semiconductor substrate top, and separates with TSV; And interconnection structure, be formed on the Semiconductor substrate top, and be electrically connected TSV and pad.This interconnection structure comprises the top that is formed on the pad and the bottom adjacent with pad, and extend to be electrically connected TSV on top.
At least one embodiment has described a kind of integrated circuit structure, and this structure comprises: Semiconductor substrate; Low k dielectric layer is above Semiconductor substrate; Metal wire is formed in the low k dielectric layer; First passivation layer is formed on the part of hanging down on the k dielectric layer and exposing metal wire; Pad is formed in first passivation layer and on the exposed portions serve of metal wire; Silicon through hole (TSV) passes first passivation layer and low k dielectric layer, and extends in the Semiconductor substrate; And interconnection structure, be formed on the top of first passivation layer, and be electrically connected TSV and pad.This interconnection structure comprises top and the bottom adjacent with pad on the pad, and extend to be electrically connected TSV on top.
Description of drawings
Carry out following detailed description with reference to accompanying drawing, wherein:
Fig. 1 to Fig. 7 is the sectional view of the exemplary embodiment of interconnection (PPI) structure after the passivation that in TSV technology, forms.
Embodiment
The disclosure relates in general to the manufacturing of through-hole structure, and it can be applied to have the manufacturing of the silicon through hole (TSV) of interconnection (PPI) structure after the passivation (be connected to contact and combine (CB) pad, be used on stacked wafer/tube core, forming perpendicular interconnection).Silicon through hole (TSV) also is called as substrate through vias or wafer via; As defined herein; Connection between one or more conductive layers on the substrate (for example, metal interconnecting layer, comprise the contact pad of bond pad) is provided, and conductive layer (for example; And/or be formed on the substrate or other expectations of being connected between the parts of substrate connect metal interconnecting layer) and the connection between the semiconductor layer (such as silicon parts).In certain embodiments, this connection that is provided by through hole provides the power path from parts to another parts.Through hole can be filled with the other materials that use electric conducting material, insulating material and/or this area.In addition, through hole can be formed on the substrate, and this substrate comprises opening in one or more layers (the comprising dielectric layer, metal level, semiconductor layer and/or miscellaneous part known in the art) on substrate.
Here, the sectional view of Fig. 1 to Fig. 7 shows the exemplary embodiment of the PPI structure that in TSV technology, forms.
Now, with reference to Fig. 1, show the sectional view of wafer 100, it comprises the interconnection structure 12 of Semiconductor substrate 10 and Semiconductor substrate 10 tops.Semiconductor substrate 10 is formed by silicon, although can also use other semi-conducting materials, comprises III family, IV family, V group element and SiGe.Alternatively, Semiconductor substrate 10 comprises non-conductive layer.The integrated circuit that comprises transistor, resistor, capacitor and other known elements is formed on the Semiconductor substrate 10.
Fig. 1 also shows contact and combines (CB) pad 18, and it is used in the combined process so that the integrated circuit in each chip is connected to external component.In first passivation layer 16, form CB pad 18, to be connected to following metal wire 12a.In the manufacturing of CB pad 18, for example comprise that first passivation layer 16 of the first dielectric layer 16a and the second dielectric layer 16b is deposited on the top layer of dielectric layer 14, be patterned then and expose the opening of following metal wire 12a with etching with formation.Then, deposits conductive material and carry out one patterned in opening to form CB pad 18.First passivation layer 16 can be formed by the dielectric material such as silica, silicon nitride, polyimides or their combination.In one embodiment, the first dielectric layer 16a is a silicon oxide layer, and the second dielectric layer 16b is a silicon nitride layer.In certain embodiments, the electric conducting material of CB pad 18 comprises the metal that is selected from aluminium, tungsten, silver, copper, aluminium alloy, copper alloy and their combination.
Fig. 2 and Fig. 3 show the formation of TSV opening 22, and the TSV opening extends in the Semiconductor substrate 10.With reference to Fig. 2, spin coating photoresist layer 20 on first passivation layer 16 and CB pad 18.Then, through make public, cure, development and/or other photoetching processes known in the art come one patterned photoresist layer 20, so that opening 21 to be provided in photoresist layer 20, expose the part of first passivation layer 16.As shown in Figure 3, then, this method proceeds to the layer that the photoresist layer 20 that uses one patterned comes etching to expose as mask element, passes the TSV opening 22 of first passivation layer 16, dielectric layer 14 and a part of Semiconductor substrate 10 with formation.Then, the stripping photolithography glue-line 20.In certain embodiments, use any suitable engraving method to come etching TSV opening 22, for example comprise plasma etching, chemical wet, laser drill and/or other technologies known in the art.In one embodiment, use reactive ion etching (RIE) to come etching TSV opening 22.In certain embodiments, the degree of depth of TSV opening 22 is approximately 100 μ m to 300 μ m.Etch process can be so that opening has vertical sidewall profile or tapered sidewalls profile.
Fig. 4 shows the formation of second passivation layer 24.Second passivation layer 24 that for example comprises the first barrier film 24a and the second barrier film 24b covers and is formed on first passivation layer 16 and the CB pad 18, and to the sidewall and the bottom lining of TSV opening 22.In certain embodiments, second passivation layer 24 is formed by the dielectric material such as silica, silicon nitride, polyimides etc.The formation method comprises plasma enhanced chemical vapor deposition (PECVD) or other CVD methods commonly used.In one embodiment, the first barrier film 24a is a silicon oxide layer, and the second barrier film 24b is a silicon nitride layer.
Fig. 5 and Fig. 6 show in second passivation layer 24 formation of the via openings 28 adjacent with CB pad 18.With reference to Fig. 5, form mask 26 on the structure that formerly forms.In one embodiment, mask 26 comprises the organic material that increases tunic (ABF) such as Ajinimoto.The ABF film at first is laminated on the structure shown in Figure 5.Then, to laminated film heating and pressurization with softening its, make to form smooth end face.In resulting structure, mask 26 has the thickness greater than about 5 μ m, more preferably between about 10 μ m and about 100 μ m.Yet mask 26 can comprise the other materials such as prepreg and resin coated copper foil (RCC).Alternatively, mask 26 is photoresists, and it can be positive photoetching rubber or negative photoresist.Then, mask 26 is carried out one patterned to form opening 27, expose the part of second passivation layer 24 above CB pad 18 and outer peripheral areas thereof.One patterned mask 26 covers TSV opening 22.
As shown in Figure 6, this method uses one patterned mask 26 to come part that etching second passivation layer 24 exposes exposing CB pad 18 as mask element, and in second passivation layer adjacent with CB pad 18, forms at least one via openings 28.In one embodiment, via openings 28 is the circular opening around CB pad 18, for example has the circular opening of anistree profile.Use any suitable engraving method (for example comprising plasma etching, chemical wet and/or other technologies known in the art) to come etching vias opening 28.In one embodiment, use reactive ion etching (RIE) to come etching vias opening 28.After the passivation etch process, remove mask 26 then.If mask 26 is dry films, then can remove through alkaline solution.If mask 26 is formed by photoresist, then can pass through removals such as acetone, N-methyl pyrrolidone (NMP), dimethyl sulfoxide (DMSO) (DMSO), amino ethoxy ethanol.As a result, expose the TSV opening 22 that is lined with second passivation layer 24.
Next, as shown in Figure 7, on resulting structures deposits conductive material layer 30 filling TSV opening 22 and the outer desired regions of TSV opening 22, thereby formation conductive plunger 32.In whole description, conductive plunger 32 is known as silicon through hole (TSV).In one embodiment, conductive material layer 30 comprises copper or copper alloy.Can also use other metals such as aluminium, silver, gold, titanium, tantalum and their combination.The formation method can comprise sputter, printing, plating, chemical plating and common chemical gas deposition (CVD) method.In the moment of TSV opening 22 filled conductive material layers 30, also on CB pad 18, form identical electric conducting material and filling vias opening 28, interconnection (PPI) structure 34 after the formation passivation.PPI structure 34 comprises top 34a and the bottom 34b that is used to cover CB pad 18.Top 34a is called as conductor wire 34a, and the bottom is called as support 34b.Conductor wire 34a is formed on the CB pad 18 and is connected to the support 34b of below.Conductor wire 34a also extends to connect the top of TSV 32.Support 34b is formed in the adjacent via openings 28 of second passivation layer 24 and CB pad 18.Therefore, PPI structure 34 covers CB pads 18, with the adhesiveness that provides and reduce contact impedance therebetween.In one embodiment, support 34b is the becket around CB pad 18.Alternatively, support 34b comprises a plurality of metal columns adjacent with CB pad 18.In one embodiment, PPI structure 34 has the thickness less than about 30 μ m, for example between about 2 μ m and about 25 μ m.Then, one patterned conductive material layer 30 is to form resulting structures as shown in Figure 7.Use with forming TSV 32 identical technologies and form PPI structure 34, TSV 32 is interconnected to CB pad 18, and CB pad 18 further is connected to active circuit.
In the embodiment that forms conductive layer 30, can also form copper layer by PVD, sputter or chemical plating, then, spraying plating copper is to fill desired regions.Fill process is well known in the art, and therefore no longer repeats here.The formation method can comprise sputter, printing, plating, chemical plating and common chemical gas deposition (CVD) method.Before forming copper layer and copper layer, can cover the deposition diffusion impervious layer, cover the part of exposing.Diffusion impervious layer can comprise barrier material commonly used, such as titanium, titanium nitride, tantalum, tantalum nitride and their combination, and can use formation such as PVD, sputter.
In later step, can formerly discuss on the end face of the structure that forms in the step chip glass is installed.Then, carry out wafer grinding with the back side of attenuate Semiconductor substrate 10 up to exposing TSV 32.Then, pull down chip glass.In certain embodiments, this method comprises that also the processing step such as metallization process interconnects and/or other technologies known in the art to provide.
In the detailed description formerly, specific embodiment has been described.Yet, should be understood that and under the situation that does not deviate from the spirit and scope of the present invention, can make various modifications, structure, technology and change.Therefore, specification and accompanying drawing are considered to exemplary, are not limited to the present invention.Should be appreciated that the disclosed embodiments can be used various other combinations and environment, and change in the concept and range that can here be shown or modification.
Claims (15)
1. integrated circuit structure comprises:
Semiconductor substrate;
Silicon through hole TSV extends in the said Semiconductor substrate;
Pad is formed on said Semiconductor substrate top, and separates with said TSV; And
Interconnection structure is formed on said Semiconductor substrate top, and is electrically connected said TSV and said pad,
Wherein, said interconnection structure comprises the top that is formed on the said pad and the bottom adjacent with said pad, and extend to be electrically connected said TSV on said top.
2. integrated circuit structure according to claim 1, wherein, the said bottom of said interconnection structure is the ring around said pad.
3. integrated circuit structure according to claim 1, wherein, said interconnection structure is formed by identical electric conducting material with said TSV, and wherein, said interconnection structure comprises copper, and said TSV comprises copper.
4. integrated circuit structure according to claim 1, wherein, said pad comprises aluminum or aluminum alloy.
5. integrated circuit structure according to claim 1; Also comprise passivation layer; Be formed between the said top of said Semiconductor substrate and said interconnection structure; And around the said bottom of said interconnection structure, said passivation layer extends in the said Semiconductor substrate, with sidewall and the bottom lining to said TSV.
6. integrated circuit structure according to claim 5, wherein, said passivation layer comprises two separators.
7. integrated circuit structure according to claim 5, wherein, said passivation layer comprises silica, silicon nitride or their combination.
8. integrated circuit structure comprises:
Semiconductor substrate;
Low k dielectric layer is above said Semiconductor substrate;
Metal wire is formed in the said low k dielectric layer;
First passivation layer is formed on the said low k dielectric layer and exposes the part of said metal wire;
Pad is formed in said first passivation layer and on the exposed portions serve of said metal wire;
Silicon through hole TSV passes said first passivation layer and said low k dielectric layer, and extends in the said Semiconductor substrate, and wherein, said TSV and said pad are spaced apart; And
Interconnection structure is formed on the top of said first passivation layer, and is electrically connected said TSV and said pad;
Wherein, said interconnection structure comprises top and the bottom adjacent with said pad on the said pad, and extend to be electrically connected said TSV on said top.
9. integrated circuit structure according to claim 8, wherein, the said bottom of said interconnection structure is the ring around said pad.
10. integrated circuit structure according to claim 8, wherein, said interconnection structure is formed by identical electric conducting material with said TSV, and wherein, said interconnection structure comprises copper, and said TSV comprises copper.
11. integrated circuit structure according to claim 8, wherein, said pad comprises at least a in aluminium, copper, aluminium alloy or the copper alloy.
12. integrated circuit structure according to claim 8 also comprises second passivation layer, is formed between the said top of said first passivation layer and said interconnection structure, and around the said bottom of said interconnection structure.
13. integrated circuit structure according to claim 12, wherein, said second passivation layer extends, with sidewall and the bottom lining to said TSV.
14. integrated circuit structure according to claim 12, wherein, said second passivation layer comprises at least a in silica, silicon nitride or their combination.
15. integrated circuit structure according to claim 8, wherein, said first passivation layer comprises at least a in silica, silicon nitride or their combination.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15497909P | 2009-02-24 | 2009-02-24 | |
| US61/154,979 | 2009-02-24 | ||
| US12/684,859 US7932608B2 (en) | 2009-02-24 | 2010-01-08 | Through-silicon via formed with a post passivation interconnect structure |
| US12/684,859 | 2010-01-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101814477A CN101814477A (en) | 2010-08-25 |
| CN101814477B true CN101814477B (en) | 2012-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201010119558.3A Active CN101814477B (en) | 2009-02-24 | 2010-02-23 | A Silicon through holes after the interlinked structure being passivated. |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214624B (en) * | 2011-05-17 | 2013-05-29 | 北京大学 | Semiconductor structure with through holes and manufacturing method thereof |
| KR101870155B1 (en) * | 2012-02-02 | 2018-06-25 | 삼성전자주식회사 | Via Connection Structures and Semiconductor Devices Having the Same, and methods of Fabricating the Sames |
| US9070698B2 (en) * | 2012-11-01 | 2015-06-30 | International Business Machines Corporation | Through-substrate via shielding |
| US10043740B2 (en) * | 2016-07-12 | 2018-08-07 | Intel Coporation | Package with passivated interconnects |
| US10312207B2 (en) | 2017-07-14 | 2019-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Passivation scheme for pad openings and trenches |
| US11404378B2 (en) * | 2020-11-24 | 2022-08-02 | Omnivision Technologies, Inc. | Semiconductor device with buried metal pad, and methods for manufacture |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101006582A (en) * | 2004-07-08 | 2007-07-25 | 斯班逊有限公司 | Bond pad structure for copper metallization having increased reliability and method for fabricating same |
| CN101308825A (en) * | 2007-05-14 | 2008-11-19 | 台湾积体电路制造股份有限公司 | Integrated circuit contruction |
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- 2010-02-23 CN CN201010119558.3A patent/CN101814477B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101006582A (en) * | 2004-07-08 | 2007-07-25 | 斯班逊有限公司 | Bond pad structure for copper metallization having increased reliability and method for fabricating same |
| CN101308825A (en) * | 2007-05-14 | 2008-11-19 | 台湾积体电路制造股份有限公司 | Integrated circuit contruction |
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| CN101814477A (en) | 2010-08-25 |
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