CN114334866A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114334866A CN114334866A CN202210030628.0A CN202210030628A CN114334866A CN 114334866 A CN114334866 A CN 114334866A CN 202210030628 A CN202210030628 A CN 202210030628A CN 114334866 A CN114334866 A CN 114334866A
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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Abstract
A semiconductor device and method of forming the same, the semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, a first temperature control region and a second temperature control region, wherein the semiconductor substrate comprises a chip region and the temperature control region surrounding the chip region; the Peltier device is positioned in the temperature control area and comprises a plurality of P-type doped areas and a plurality of N-type doped areas which are positioned in the semiconductor substrate of the temperature control area and are alternately arranged along the boundary direction of the chip area; the first end metal layer and the second end metal layer are positioned on one sides of the N-type doped regions and the P-type doped regions, which are far away from the chip region, the first end metal layer is electrically connected with the N-type doped regions, and the second end metal layer is electrically connected with the P-type doped regions; and the third end metal layer is positioned in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region and is electrically connected with the N-type doped region and the P-type doped region. The temperature control efficiency is improved.
Description
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The temperature variation has influence on the working state and circuit performance of the chip. When the chip works, only a part of input power is used for outputting useful work, and a lot of electric energy is converted into heat energy, so that the temperature of components in the chip is increased. The allowable working temperature of the components is limited, and if the actual temperature exceeds the allowable temperature of the components, the performance of the components can be deteriorated or even burnt. As are transistors, resistors, capacitors, transformers, printed circuit boards, memories.
Although some temperature control devices can be used for controlling the temperature of the chip in the prior art, the temperature control efficiency is not high, and the volume of the whole device is larger due to the fact that the temperature control devices and the chip are packaged together.
Disclosure of Invention
Some embodiments of the present application provide a semiconductor structure, comprising:
the semiconductor device comprises a semiconductor substrate, a first temperature control region and a second temperature control region, wherein the semiconductor substrate comprises a chip region and the temperature control region surrounding the chip region;
the Peltier device is positioned in the temperature control area and comprises a plurality of P-type doped areas and a plurality of N-type doped areas which are positioned in the semiconductor substrate of the temperature control area and are alternately arranged along the boundary direction of the chip area; the first end metal layer and the second end metal layer are positioned on one sides of the N-type doped regions and the P-type doped regions, which are far away from the chip region, the first end metal layer is electrically connected with the N-type doped regions, and the second end metal layer is electrically connected with the P-type doped regions; and the third end metal layer is positioned in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region and is electrically connected with the N-type doped region and the P-type doped region.
In some embodiments, the third end metal layer is an elongated metal layer, and the elongated metal layer is electrically connected to all of the N-type doped regions and the P-type doped regions.
In some embodiments, the third terminal metal layer includes a plurality of sequentially spaced third terminal metal layers, each of which is electrically connected to at least one pair of adjacent N-type and P-type doped regions.
In some embodiments, the semiconductor substrate of the N-type doped region and the P-type doped region near the chip region has a first trench exposing a sidewall surface of the N-type doped region and the P-type doped region near the chip region, and the third terminal metal layer fills the first trench.
In some embodiments, each of the first end metal layer and the second end metal layer includes a plurality of teeth protruding away from the chip region and a body portion connected to the plurality of teeth, and the body portion is electrically connected to the corresponding N-type doped region and the corresponding P-type doped region.
In some embodiments, the first end metal layer is located below the second end metal layer, and the first end metal layer is located in the semiconductor substrate on a side of the N-type doped region and the P-type doped region away from the chip region; the semiconductor structure further comprises a dielectric layer, and the first end metal layer and the second end metal layer are isolated through the dielectric layer.
In some embodiments, the semiconductor structure further includes a plurality of first connecting metal pads and first metal plugs connected to an upper surface of each of the first connecting metal pads, the first connecting metal pads are located in the semiconductor substrate at a side of the P-type doped region away from the chip region and are electrically connected to a side of the P-type doped region away from the chip region, and the second end metal layer is connected to the corresponding first connecting metal pad through the first metal plug located in the dielectric layer.
In some embodiments, the first end metal layer is located above a second end metal layer, and the second end metal layer is located in the semiconductor substrate on a side of the N-type doped region and the P-type doped region away from the chip region; the semiconductor structure further comprises a dielectric layer, and the first end metal layer and the second end metal layer are isolated through the dielectric layer.
In some embodiments, the semiconductor structure further includes a plurality of second connection metal pads and a second metal plug connected to an upper surface of each of the second connection metal pads, the second connection metal pads are located in the semiconductor substrate at a side of the N-type doped region away from the chip region and are electrically connected to a side of the N-type doped region away from the chip region, and the first end metal layer is connected to the corresponding second connection metal pads through the second metal plugs located in the dielectric layer.
In some embodiments, the N-type and P-type doped regions are formed by an ion implantation process.
In some embodiments, the peltier device in the temperature controlled zone surrounds the chip zone along the direction of the chip zone boundary.
In some embodiments, the first terminal metal layer is connected to a positive power supply electrode and the second terminal metal layer is connected to a negative power supply electrode.
In some embodiments, the chip region includes a semiconductor chip, the semiconductor structure further comprising a guard ring device comprising a number of metal layers and metal plugs connecting adjacent layers of the metal layers, the guard ring device disposed between the peltier device and the semiconductor chip and surrounding the semiconductor chip.
Some embodiments of the present application further provide a method for forming a semiconductor structure, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a chip area and a temperature control area surrounding the chip area;
forming a peltier device at the temperature controlled zone, comprising:
forming a plurality of P-type doped regions and a plurality of N-type doped regions which are alternately arranged along the boundary direction of the chip region in the semiconductor substrate positioned in the temperature control region;
forming a first end metal layer and a second end metal layer which are positioned on one sides of the N-type doped regions and the P-type doped regions far away from the chip region, wherein the first end metal layer is electrically connected to the N-type doped regions, and the second end metal layer is electrically connected to the P-type doped regions;
and forming a third end metal layer in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region, wherein the third end metal layer is electrically connected with the N-type doped region and the P-type doped region.
In some embodiments, the forming of the third terminal metal layer includes: forming a first groove in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region, wherein the first groove exposes the side wall surface of one side of the N-type doped region and the P-type doped region close to the chip region; and filling metal in the first groove to form a third end metal layer.
In some embodiments, the forming of the first and second terminal metal layers comprises: forming comb-shaped second grooves in the semiconductor substrate on one side of the N-type doped region far away from the chip region, wherein the second grooves expose the side wall surfaces of the N-type doped regions on one side far away from the chip region; forming a plurality of third grooves in the semiconductor substrate on one side of each P-type doped region far away from the chip, wherein the side wall surface of one side of each P-type doped region far away from the chip is correspondingly exposed by each third groove; filling metal into the comb-shaped second grooves to form a first end metal layer, and filling metal into the third grooves to form a plurality of first connecting metal pads; forming a dielectric layer on the semiconductor substrate, wherein a plurality of first metal plugs connected with corresponding first connecting metal pads are formed in the dielectric layer; and forming a second end metal layer connected with the first metal plugs on the dielectric layer.
In some embodiments, the forming of the first and second terminal metal layers comprises: forming a comb-shaped fourth groove in the semiconductor substrate on one side of the P-type doped region far away from the chip region, wherein the fourth groove exposes the side wall surfaces of the P-type doped regions on one side far away from the chip region; forming a plurality of fifth grooves in the semiconductor substrate on one side of each N-type doped region, which is far away from the chip, wherein each fifth groove correspondingly exposes the side wall surface of one N-type doped region, which is far away from the chip; filling metal into the comb-shaped fourth grooves to form a second end metal layer, and filling metal into the fifth grooves to form a plurality of second connecting metal pads; forming a dielectric layer on the semiconductor substrate, wherein a plurality of second metal plugs connected with corresponding second connecting metal pads are formed in the dielectric layer; and forming a first end metal layer connected with the plurality of second metal plugs on the dielectric layer.
In some embodiments, the forming of the N-type and P-type doped regions includes: forming a groove in the temperature control area; filling bismuth telluride materials in the grooves; and doping the bismuth telluride material to form an N-type doped region and a P-type doped region.
In some embodiments, further comprising: forming a semiconductor chip on the chip area, and forming a guard ring device surrounding the semiconductor chip between the Peltier device and the semiconductor chip, wherein the guard ring device comprises a plurality of metal layers and metal plugs connecting the metal layers of adjacent layers.
In the semiconductor device in some embodiments of the present application, since the third end metal layer is located as the cold end in the semiconductor substrate on the side where the N-type doped region and the P-type doped region are close to the chip region, and the first end metal layer and the second end metal layer are located as the hot end in the semiconductor substrate on the side where the N-type doped region and the P-type doped region are far away from the chip region, heat generated by components formed in the semiconductor substrate in the chip region can be transversely and directly absorbed through the third end metal layer, so as to improve the efficiency of temperature control, and since the peltier device is located in the temperature control region around the chip region, the semiconductor chip formed with the chip region can be subsequently and integrally packaged, and the peltier device does not occupy too large volume.
Drawings
FIGS. 1-7 are schematic structural diagrams of semiconductor devices in some embodiments of the present application;
FIGS. 8-11 are schematic structural diagrams of semiconductor devices in further embodiments;
fig. 12-13 are schematic structural diagrams of semiconductor devices in further embodiments.
Detailed Description
The following detailed description of embodiments of the present application refers to the accompanying drawings. In describing the embodiments of the present application in detail, the drawings are not necessarily to scale, and the drawings are merely exemplary and should not be construed as limiting the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Some embodiments of the present application provide a semiconductor device, and referring to fig. 2 to 7, fig. 3 and 6 are schematic partial enlarged structural views of the peltier device in fig. 2, fig. 4 is a schematic sectional structural view of fig. 3 along a cutting line AB, fig. 5 is a schematic sectional structural view of fig. 3 along a cutting line CD, and fig. 7 is a schematic sectional structural view of fig. 6 along the cutting line AB, including:
the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a chip area 101 and a temperature control area 102 surrounding the chip area 101;
a peltier device 104 located in the temperature control region 102, wherein the peltier device 104 comprises a plurality of P-type doped regions 105 and a plurality of N-type doped regions 106 (refer to fig. 3 and 5) located in the semiconductor substrate 100 of the temperature control region 102 and alternately arranged along the boundary direction of the chip region 101; a first end metal layer 107 (refer to fig. 3, the second end metal layer 112 is not shown in fig. 3 for convenience of illustration) and a second end metal layer 112 (refer to fig. 6, the first end metal layer 107 is not shown in fig. 6 for convenience of illustration) located on a side of the N-type doped region 106 and the P-type doped region 105 away from the chip region 101, wherein the first end metal layer 107 is electrically connected to the N-type doped regions 106, and the second end metal layer 112 is electrically connected to the P-type doped regions 105; a third terminal metal layer 111 (refer to fig. 3 and 4) in the semiconductor substrate 100 on a side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101, wherein the third terminal metal layer 111 is electrically connected to the N-type doped region 106 and the P-type doped region 105.
The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is silicon.
The chip region 101 is a region including a semiconductor chip, which may be a sensor chip, a memory chip, or a chip having other functions, or an integrated circuit. The temperature control region 102 surrounds the chip region 101 and is in contact with the peripheral edge of the chip region, the peltier device 104 of the temperature control region 102 controls the temperature of the chip region 101 through a semiconductor refrigeration effect, so that the temperature of the chip region 101 is kept at a predetermined temperature, and the semiconductor chip or the integrated circuit in the chip region 101 is prevented from being degraded due to over-temperature.
Referring to fig. 3 and 5, when the number of the N-type doped regions and the number of the P-type doped regions are both multiple, the multiple N-type doped regions and the multiple P-type doped regions are alternately arranged along the boundary extending direction of the chip region.
In some embodiments, the N-type and P-type doped regions are formed by an ion implantation process. Specifically, N-type impurity ions are implanted into a plurality of discrete first regions in the semiconductor substrate 100 of the temperature control region 102 to form a plurality of N-type doped regions, and P-type impurity ions are implanted into a plurality of discrete second regions in the semiconductor substrate 100 of the temperature control region 102 to form a plurality of P-type doped regions. The impurity ions injected by the ion implantation are P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions. In other embodiments, the process of forming the N-type doped region 106 and the P-type doped region 105 may further include: forming a groove in the temperature-controlled area 102; filling bismuth telluride materials in the grooves; and doping the bismuth telluride material to form an N-type doped region 106 and a P-type doped region 105.
In this embodiment, referring to fig. 3 and fig. 4, the third end metal layer 111 is a strip-shaped metal layer, and the strip-shaped metal layer 111 is electrically connected to all of the N-type doped regions 106 and the P-type doped regions 105. When the peltier device 104 is used for cooling, a voltage is applied to the first terminal metal layer 107 and the second terminal metal layer 112 (specifically, the first terminal metal layer 107 is connected to the positive electrode of a power supply, and the second terminal metal layer 112 is connected to the negative electrode of the power supply), the N-type doped region and the P-type doped region are connected to one end of the third terminal metal layer 111 as a cold end, and the heat generated by the chip region is absorbed by the third terminal metal layer 111, in this application, since the third terminal metal layer 111 is located in the semiconductor substrate 100 on the side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101, the heat generated by components formed in the semiconductor substrate of the chip region can be absorbed laterally and directly by the third terminal metal layer 111, so that the efficiency of temperature control is improved, and since the peltier device 104 is located in the temperature control region 102 around the chip region 101, the semiconductor chip which can be subsequently formed with the chip region 101 is integrally packaged without occupying too much volume.
In some embodiments, the third terminal metal layer 111 may be a single layer structure formed of one material of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, Wsi, or a stacked layer structure formed of two or more materials selected from the group consisting of the above materials.
In some embodiments, the semiconductor substrate 100 of the N-type doped region 106 and the P-type doped region 105 near the chip region 101 has a first trench 121 (refer to fig. 9) exposing a sidewall surface of one side of the N-type doped region 106 and the P-type doped region 105 near the chip region 101, and the third terminal metal layer 111 fills the first trench.
Referring to fig. 3 to fig. 7, the first end metal layer 107 and the second end metal layer 112 are located at different layers (it should be noted that, for convenience of illustration, only the first end metal layer 107 is shown in fig. 3, and the second end metal layer 112 is not shown, and only the second end metal layer 112 is shown in fig. 7, and the first end metal layer 107 is not shown). In this embodiment, the first end metal layer 107 is located below the second end metal layer 112, the first end metal layer 107 is a lower layer or a front layer, and the second end metal layer 112 is an upper layer or a current layer. In some other embodiments, the first end metal layer is located above the second end metal layer, the first end metal layer is an upper layer or a current layer, and the second end metal layer is a lower layer or a front layer.
In some embodiments, the first end metal layer 107 and the second end metal layer 112 may be a single layer structure formed of one material of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, Wsi, or a stacked layer structure formed of two or more materials selected from the group consisting of the above materials.
In some embodiments, each of the first end metal layer 107 (see fig. 3) and the second end metal layer 112 (see fig. 6) includes a plurality of teeth (108 or 113) protruding away from the chip region 101 and a body portion (109 or 114) connected to the teeth (108 or 113), the body portion (109 or 114) is electrically connected to the corresponding N-type doped region 106 and the P-type doped region 105, and when the first end metal layer 107 and the second end metal layer 112 are used as hot ends, the heat dissipation area per unit volume is larger and the heat dissipation efficiency is improved. Specifically, the first terminal metal layer 107 (see fig. 3) includes a plurality of teeth 108 protruding away from the chip region 101 and a body portion 109 connected to the plurality of teeth 108, the body portion 109 is electrically connected to the corresponding N-type doped region 106, and in some embodiments, the body portion 109 is electrically connected to the corresponding N-type doped region 106 through a connection portion 110. The second end metal layer 112 (refer to fig. 6) includes a plurality of teeth 113 protruding away from the chip region 101 and a body portion 114 connected to the teeth 113, wherein the body portion 114 is electrically connected to the corresponding P-type doped region 105, and in some embodiments, the body portion 114 is electrically connected to the corresponding P-type doped region 105 through a connection portion 115.
In this embodiment, referring to fig. 3-4 and fig. 6-7, the first end metal layer 107 is located below the second end metal layer 112, and the first end metal layer 107 is located in the semiconductor substrate 100 at a side of the N-type doped region 106 and the P-type doped region 105 away from the chip region 101. In some embodiments, referring to fig. 7, the semiconductor structure further comprises a dielectric layer 118, and the first end metal layer 107 and the second end metal layer 112 are separated by the dielectric layer 118.
In some embodiments, the dielectric layer 118 is a single layer structure formed of one of silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-doped silicon dioxide), low-k material, or a stacked layer structure formed of two or more materials selected from the group consisting of the above materials.
In some embodiments, referring to fig. 7, the semiconductor structure further includes a plurality of first connection metal pads 116 and first metal plugs 117 connected to an upper surface of each of the first connection metal pads 116, the first connection metal pads 116 are located in the semiconductor substrate 100 at a side of the P-type doped region 105 away from the chip region 101 and are electrically connected to a side of the P-type doped region 105 away from the chip region 101, and the second end metal layer 112 is connected to the corresponding first connection metal pad 116 through the first metal plugs 117 located in the dielectric layer 118, so as to be electrically connected to a side of the corresponding P-type doped region 105 away from the chip region 101.
In some embodiments, the peltier device 104 in the temperature controlled zone 102 may be located on one or more sides of a boundary of the chip zone, so that the temperature of the chip zone can be controlled from one direction or multiple directions.
In some embodiments, the peltier device 104 in the temperature control zone 102 surrounds the chip area 101 along the boundary of the chip area 101, so that the temperature of the chip area 101 can be controlled directly from the periphery of the chip area 101 in the transverse direction, thereby better controlling the temperature of the chip area 101.
In some embodiments, the semiconductor structure further comprises a guard ring device comprising a number of metal layers and metal plugs connecting adjacent layers of the metal layers, the guard ring device disposed between the peltier device and the semiconductor chip and surrounding the semiconductor chip.
In some embodiments, the temperature control region 102 may also serve as a protection ring region, and the semiconductor structure further includes a protection ring device, where the protection ring device includes a plurality of metal layers and a metal plug connecting the metal layers of adjacent layers, and the protection ring device is disposed on the peltier device and surrounds the chip region, so that both temperature control and protection of the semiconductor chip in the chip region can be achieved in one region.
The guard ring device (also referred to as a seal ring device or a guard ring device) can prevent the semiconductor chip from being damaged by a dicing process and from being degraded by moisture, and can also prevent moisture from penetrating or chemical damage such as diffusion of a contamination source including an acid and an alkali, thereby protecting the semiconductor chip. The protection ring device is of a multilayer structure and comprises a plurality of metal layers, metal plugs for connecting the metal layers of the adjacent layers and dielectric layers for isolating the metal layers from the corresponding metal plugs, wherein the dielectric layers are of the multilayer structure.
Another embodiment of the present invention further provides a semiconductor structure, which is different from the aforementioned embodiments in that, the first end metal layer is located above the second end metal layer, as shown in fig. 8-11, fig. 9 is a schematic sectional structure view along a cutting line AB in fig. 8, fig. 11 is a schematic sectional structure view along the cutting line AB in fig. 10 (it should be noted that, for convenience of illustration, only the second end metal layer 112 is shown in fig. 8, the first end metal layer 107 is not shown, only the first end metal layer 107 is shown in fig. 10, the second end metal layer 112 is not shown), the first terminal metal layer 107 is located above the second terminal metal layer 112 (refer to figure 11), and the second end metal layer 112 is located in the semiconductor substrate 100 on the side of the N-type doped region 106 and the P-type doped region 105 away from the chip region 101 (refer to fig. 8 and 9); the semiconductor structure further includes a dielectric layer 118 (refer to fig. 11), and the first terminal metal layer 107 and the second terminal metal layer 112 are separated by the dielectric layer 118.
In some embodiments, referring to fig. 11, the semiconductor structure further includes a plurality of second connection metal pads 126 and second metal plugs 127 connected to an upper surface of each of the second connection metal pads 126, the second connection metal pads 126 are located in the semiconductor substrate 100 at a side of the N-type doped region 106 away from the die region 101 and are electrically connected to a side of the N-type doped region 106 away from the die region 101, and the first end metal layer 107 is connected to the corresponding second connection metal pad 126 through the second metal plug 127 located in the dielectric layer 118, so as to be electrically connected to a side of the corresponding N-type doped region 106 away from the die region 101.
In another embodiment of the present invention, a semiconductor structure is further provided, which is different from the foregoing embodiments in that the third terminal metal layer has a different specific structure, specifically referring to fig. 12 and 13, the third terminal metal layer includes a plurality of sequentially spaced third terminal metal layers (111a, 111b, 111c), and each of the third terminal metal layers (111a, 111b, 111c) is electrically connected to at least one pair of adjacent N-type doped regions 106 and P-type doped regions 105.
In some embodiments of the present invention, there is also provided a method for forming a semiconductor structure, including:
referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a chip region 101 and a temperature controlled region 102 surrounding the chip region 101.
In some embodiments, the semiconductor substrate 100 is a wafer, the semiconductor substrate 100 includes a plurality of chip regions 101 arranged in rows and columns, each chip region 100 has a temperature control region 102 surrounding the chip region 101, and a scribe line region 103 is between the temperature control regions 102. The temperature control region 102 is used for forming a peltier device subsequently, the chip region 101 is used for forming a semiconductor chip subsequently, and the dicing street region 103 is used as a dicing street for dividing a wafer subsequently.
Referring to fig. 2, the peltier device 104 is formed at the temperature controlled zone, including:
referring to fig. 3 and 5, a plurality of N-type doped regions 106 and a plurality of P-type doped regions 105 alternately arranged along the boundary direction of the chip region 101 are formed in the semiconductor substrate 100 located in the temperature control region 102.
In some embodiments, the N-type and P-type doped regions are formed by an ion implantation process. Specifically, N-type impurity ions are implanted into a plurality of discrete first regions in the semiconductor substrate 100 of the temperature control region 102 to form a plurality of N-type doped regions, and P-type impurity ions are implanted into a plurality of discrete second regions in the semiconductor substrate 100 of the temperature control region 102 to form a plurality of P-type doped regions. The impurity ions injected by the ion implantation are P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions or indium ions. In other embodiments, the process of forming the N-type doped region 106 and the P-type doped region 105 may further include: forming a groove in the temperature-controlled area 102; filling bismuth telluride materials in the grooves; and doping the bismuth telluride material to form an N-type doped region 106 and a P-type doped region 105.
Referring to fig. 3 and 6, a first end metal layer 107 and a second end metal layer 112 are formed on the sides of the N-type doped regions 106 and the P-type doped regions 105 away from the chip region 101, wherein the first end metal layer 107 is electrically connected to the N-type doped regions 106, and the second end metal layer 112 is electrically connected to the P-type doped regions 105.
In some embodiments, the first end metal layer 107 is located below the second end metal layer 112, and the forming process of the first end metal layer 107 and the second end metal layer 112 includes: forming comb-shaped second grooves in the semiconductor substrate on the side of the N-type doped region 106 away from the chip region, wherein the second grooves expose the sidewall surfaces of the N-type doped regions 106 on the side away from the chip region; forming a plurality of third grooves in the semiconductor substrate on one side of each P-type doped region 105 far away from the chip, wherein each third groove correspondingly exposes a side wall surface of one P-type doped region 105 far away from the chip; filling metal in the comb-shaped second trenches to form a first terminal metal layer 107 (refer to fig. 3 and 4), filling metal in the plurality of third trenches to form a plurality of first connection metal pads 116 (refer to fig. 3 and 5); forming a dielectric layer 118 (refer to fig. 7) on the semiconductor substrate 100, wherein a plurality of first metal plugs 117 connected with corresponding first connection metal pads 116 are formed in the dielectric layer 118; a second terminal metal layer 112 connected to a plurality of first metal plugs 117 is formed on the dielectric layer 118.
In other embodiments, referring to fig. 8-11, the first end metal layer 107 is located above the second end metal layer 112, and the forming of the first end metal layer 107 and the second end metal layer 112 includes: forming a comb-shaped fourth groove in the semiconductor substrate on the side of the P-type doped region 105 away from the chip region, wherein the fourth groove exposes the sidewall surfaces of the P-type doped regions 105 on the side away from the chip region; forming a plurality of fifth grooves in the semiconductor substrate on one side of each N-type doped region 106 away from the chip, wherein each fifth groove correspondingly exposes a sidewall surface of one side of each N-type doped region 106 away from the chip; filling metal in the comb-shaped fourth trenches to form a second terminal metal layer 112 (refer to fig. 8-9), filling metal in the fifth trenches to form second connecting metal pads 126 (refer to fig. 8); forming a dielectric layer 118 (refer to fig. 11) on the semiconductor substrate 100, wherein a plurality of second metal plugs 127 connected to corresponding second connection metal pads 126 are formed in the dielectric layer 118; a first terminal metal layer 107 connected to a plurality of second metal plugs 127 is formed on the dielectric layer 118.
Referring to fig. 3 and 4, a third terminal metal layer 111 is formed in the semiconductor substrate 100 on a side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101, and the third terminal metal layer 111 is electrically connected to the N-type doped region 106 and the P-type doped region 105.
In some embodiments, the forming process of the third end metal layer 111 includes: forming a first groove 121 in the semiconductor substrate 100 at a side of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101, wherein the first groove 121 exposes a side wall surface of the N-type doped region 106 and the P-type doped region 105 close to the chip region 101; and filling metal in the first trench 121 to form a third terminal metal layer 111.
In some embodiments, the third end metal layer 111 is formed simultaneously with the first end metal layer 107 or the second end metal layer 112 on the same layer, and in particular, the third end metal layer 111 is formed simultaneously with the first end metal layer 107 when the first end metal layer 107 is located below the second end metal layer 112. When the second terminal metal layer 112 is located under the first terminal metal layer 107, the third terminal metal layer 111 is formed simultaneously with the second terminal metal layer 112.
In some embodiments, further comprising: forming a semiconductor chip on the chip region 101, and forming a guard ring device surrounding the semiconductor chip between the Peltier device and the semiconductor chip, wherein the guard ring device comprises a plurality of metal layers and metal plugs connecting the metal layers of adjacent layers.
In some embodiments, the peltier device and the semiconductor chip may be integrated, for example, the formation process of the first end metal layer 107 or the second end metal layer 112 located at the upper layer may be performed simultaneously with the underlying metal line process when the semiconductor chip is manufactured, the formation process of the N-type doped region 106 and the P-type doped region 105 may be performed simultaneously with the related doping process in the semiconductor chip, and the process of forming the groove in the temperature control region may be performed simultaneously with the process of forming the groove in the chip region.
In some embodiments, after the peltier device and the semiconductor chip are fabricated, the wafer may be diced along the dicing street regions to form a plurality of individual chips.
Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible variations and modifications of the present application using the methods and technical content disclosed above without departing from the spirit and scope of the present application, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application shall fall within the scope of the present application.
Claims (19)
1. A semiconductor structure, comprising:
the semiconductor device comprises a semiconductor substrate, a first temperature control region and a second temperature control region, wherein the semiconductor substrate comprises a chip region and the temperature control region surrounding the chip region;
the Peltier device is positioned in the temperature control area and comprises a plurality of P-type doped areas and a plurality of N-type doped areas which are positioned in the semiconductor substrate of the temperature control area and are alternately arranged along the boundary direction of the chip area; the first end metal layer and the second end metal layer are positioned on one sides of the N-type doped regions and the P-type doped regions, which are far away from the chip region, the first end metal layer is electrically connected with the N-type doped regions, and the second end metal layer is electrically connected with the P-type doped regions; and the third end metal layer is positioned in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region and is electrically connected with the N-type doped region and the P-type doped region.
2. The semiconductor structure of claim 1, wherein the third metal layer is an elongated metal layer electrically connected to all of the N-type doped regions and the P-type doped regions.
3. The semiconductor structure of claim 1, wherein the third terminal metal layer comprises a plurality of sequentially spaced third terminal metal layers, each third terminal metal layer being electrically connected to at least one pair of adjacent N-type and P-type doped regions.
4. The semiconductor structure of claim 1, wherein the semiconductor substrate of the N-type and P-type doped regions near the chip region has a first trench therein exposing a sidewall surface of the N-type and P-type doped regions near the chip region, and the third terminal metal layer fills the first trench.
5. The semiconductor structure of claim 1, wherein the first end metal layer and the second end metal layer each include a plurality of teeth projecting away from the chip area and a body portion connected to the plurality of teeth, the body portion being electrically connected to the respective N-type doped region and P-type doped region.
6. The semiconductor structure of claim 1, wherein the first end metal layer is located below the second end metal layer, and the first end metal layer is located in the semiconductor substrate at a side of the N-type and P-type doped regions away from the chip region; the semiconductor structure further comprises a dielectric layer, and the first end metal layer and the second end metal layer are isolated through the dielectric layer.
7. The semiconductor structure of claim 6, further comprising a plurality of first link metal pads and first metal plugs connected to an upper surface of each of the first link metal pads, the first link metal pads being located in the semiconductor substrate on a side of the P-doped region away from the die region and being electrically connected to the side of the P-doped region away from the die region, the second end metal layer being connected to the corresponding first link metal pad through the first metal plug located in the dielectric layer.
8. The semiconductor structure of claim 1, wherein the first end metal layer is located above a second end metal layer, and the second end metal layer is located in the semiconductor substrate on a side of the N-type and P-type doped regions away from the chip region; the semiconductor structure further comprises a dielectric layer, and the first end metal layer and the second end metal layer are isolated through the dielectric layer.
9. The semiconductor structure of claim 8, further comprising a plurality of second connecting metal pads and a second metal plug connected to an upper surface of each of the second connecting metal pads, wherein the second connecting metal pads are located in the semiconductor substrate on a side of the N-doped region away from the die region and are electrically connected to a side of the N-doped region away from the die region, and the first terminal metal layer is connected to the corresponding second connecting metal pad through the second metal plug located in the dielectric layer.
10. The semiconductor structure of claim 1, wherein the N-type doped region and the P-type doped region are formed by an ion implantation process.
11. The semiconductor structure of claim 1, wherein the peltier device in the temperature controlled zone surrounds the chip region along a direction of a boundary of the chip region.
12. The semiconductor structure of claim 1, wherein the first terminal metal layer is connected to a positive power supply and the second terminal metal layer is connected to a negative power supply.
13. The semiconductor structure of claim 1, wherein the die region comprises a semiconductor die, the semiconductor structure further comprising a guard ring device comprising a number of metal layers and metal plugs connecting adjacent layers of the metal layers, the guard ring device disposed between the peltier device and the semiconductor die and surrounding the semiconductor die.
14. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a chip area and a temperature control area surrounding the chip area;
forming a peltier device at the temperature controlled zone, comprising:
forming a plurality of P-type doped regions and a plurality of N-type doped regions which are alternately arranged along the boundary direction of the chip region in the semiconductor substrate positioned in the temperature control region;
forming a first end metal layer and a second end metal layer which are positioned on one sides of the N-type doped regions and the P-type doped regions far away from the chip region, wherein the first end metal layer is electrically connected to the N-type doped regions, and the second end metal layer is electrically connected to the P-type doped regions;
and forming a third end metal layer in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region, wherein the third end metal layer is electrically connected with the N-type doped region and the P-type doped region.
15. The method of forming a semiconductor structure of claim 14, wherein the forming of the third terminal metal layer comprises: forming a first groove in the semiconductor substrate at one side of the N-type doped region and the P-type doped region close to the chip region, wherein the first groove exposes the side wall surface of one side of the N-type doped region and the P-type doped region close to the chip region; and filling metal in the first groove to form a third end metal layer.
16. The method of forming a semiconductor structure of claim 14, wherein the forming of the first and second terminal metal layers comprises: forming comb-shaped second grooves in the semiconductor substrate on one side of the N-type doped region far away from the chip region, wherein the second grooves expose the side wall surfaces of the N-type doped regions on one side far away from the chip region; forming a plurality of third grooves in the semiconductor substrate on one side of each P-type doped region far away from the chip, wherein the side wall surface of one side of each P-type doped region far away from the chip is correspondingly exposed by each third groove; filling metal into the comb-shaped second grooves to form a first end metal layer, and filling metal into the third grooves to form a plurality of first connecting metal pads; forming a dielectric layer on the semiconductor substrate, wherein a plurality of first metal plugs connected with corresponding first connecting metal pads are formed in the dielectric layer; and forming a second end metal layer connected with the first metal plugs on the dielectric layer.
17. The method of forming a semiconductor structure of claim 15, wherein the forming of the first and second terminal metal layers comprises: forming a comb-shaped fourth groove in the semiconductor substrate on one side of the P-type doped region far away from the chip region, wherein the fourth groove exposes the side wall surfaces of the P-type doped regions on one side far away from the chip region; forming a plurality of fifth grooves in the semiconductor substrate on one side of each N-type doped region, which is far away from the chip, wherein each fifth groove correspondingly exposes the side wall surface of one N-type doped region, which is far away from the chip; filling metal into the comb-shaped fourth grooves to form a second end metal layer, and filling metal into the fifth grooves to form a plurality of second connecting metal pads; forming a dielectric layer on the semiconductor substrate, wherein a plurality of second metal plugs connected with corresponding second connecting metal pads are formed in the dielectric layer; and forming a first end metal layer connected with the plurality of second metal plugs on the dielectric layer.
18. The method of claim 14, wherein the forming of the N-type and P-type doped regions comprises: forming a groove in the temperature control area; filling bismuth telluride materials in the grooves; and doping the bismuth telluride material to form an N-type doped region and a P-type doped region.
19. The method of forming a semiconductor structure of claim 14, further comprising: forming a semiconductor chip on the chip area, and forming a guard ring device surrounding the semiconductor chip between the Peltier device and the semiconductor chip, wherein the guard ring device comprises a plurality of metal layers and metal plugs connecting the metal layers of adjacent layers.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210030628.0A CN114334866A (en) | 2022-01-12 | 2022-01-12 | Semiconductor structure and forming method thereof |
| PCT/CN2022/084281 WO2023134024A1 (en) | 2022-01-12 | 2022-03-31 | Semiconductor structure and forming method therefor |
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| CN202210030628.0A CN114334866A (en) | 2022-01-12 | 2022-01-12 | Semiconductor structure and forming method thereof |
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| JP2002289752A (en) * | 2001-03-27 | 2002-10-04 | Toshiba Elevator Co Ltd | Semiconductor switch device and power conversion device using the same |
| JP2004241714A (en) * | 2003-02-07 | 2004-08-26 | Okano Electric Wire Co Ltd | Thermoelectric conversion module |
| US20110128727A1 (en) * | 2008-07-23 | 2011-06-02 | Nxp B.V. | Integrated seebeck device |
| CN108490577A (en) * | 2018-03-12 | 2018-09-04 | 广东欧珀移动通信有限公司 | Structured light projector, image acquiring device and electronic equipment |
| CN111430466A (en) * | 2020-05-06 | 2020-07-17 | 厦门芯达茂微电子有限公司 | TE-cooler MOSFET structure and preparation and adjustment methods thereof |
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