CN114333727B - Display panel - Google Patents

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CN114333727B
CN114333727B CN202111635858.1A CN202111635858A CN114333727B CN 114333727 B CN114333727 B CN 114333727B CN 202111635858 A CN202111635858 A CN 202111635858A CN 114333727 B CN114333727 B CN 114333727B
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potential
pulse signal
sub
discharging rod
signal
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CN114333727A (en
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胡春晓
严允晟
何孝金
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TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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Abstract

The application discloses a display panel, wherein the display panel includes: the display device comprises a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a main region sub-pixel and a sub-region sub-pixel, and the sub-region sub-pixels are electrically connected with a shared discharging rod; when the sub-pixel is of a first polarity, the signal on the shared discharging rod is a first pulse signal; when the sub-pixel is of the second polarity, the signal on the shared discharging rod is a second pulse signal; when the sub-pixel is switched from the first polarity to the second polarity, the signal on the shared discharging rod is a third pulse signal in the blanking time interval between two adjacent frames of pictures, and the third pulse signal enables the potential of the shared discharging rod to reach the target potential in advance when the potential is switched from the first pulse signal to the second pulse signal. The method and the device enable the signal of the shared discharging rod to reach the target potential in advance before switching between the first pulse signal and the second pulse signal, so that the problem of delay of the pulse signal of the shared discharging rod is solved, and the display image quality is remarkably improved.

Description

Display panel
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
As the technology of display panels has been more and more mature, liquid crystal display panels have been widely used in various large, medium and small-sized display devices due to their light weight, small size, thin thickness, and the like. At present, the performance requirements of corresponding liquid crystal display products in the market are developed towards characteristics such as high contrast ratio, wide view angle and the like. The current technology capable of realizing the requirement of wide view angle mainly comprises three modes: twisted nematic liquid crystal display device, in-plane switching liquid crystal display device, and multi-domain vertical alignment mode liquid crystal display device. The vertical alignment mode is a common display mode with the advantages of high contrast ratio, wide viewing angle, no rubbing alignment and the like. At present, a vertical alignment pixel design of an 8-domain 3 transistor is generally adopted, so that the rotation angles of liquid crystal molecules of 4 domains of a main region sub-pixel and 4 domains of a secondary region sub-pixel in the same sub-pixel are different, and the color cast is improved.
With the continuous improvement of information technology and living standard, the requirements of people on the image quality of the display, such as the transmittance and the visual angle, are also increasing. In order to increase the viewing angle, it is necessary to divide the pixel into multiple domains, but this causes a loss of transmittance, so that the viewing angle and the transmittance are in an inverse relationship. The AC sharing discharging rod technology is a technology capable of improving the visual angle with low gray level and improving the penetration with high gray level, namely, the visual angle and the penetration of the panel can be improved simultaneously.
However, for large-size panels, the voltage switching delay of the common discharging rod is caused when the voltage is switched due to the heavy resistance-capacitance load of the panel. FIG. 1 is a schematic delay diagram of a pulse signal of a common discharging rod in the prior art, as shown in FIG. 1 (a), when a sub-pixel is positive, the signal of the common discharging rod is V11; when the subpixel is negative, the signal of the shared discharging rod is V12, and when the signal of the electric shared discharging rod is changed from V11 to V12, the resistive-capacitive load needs a certain time to rise to the target voltage due to the existence of the resistive-capacitive load. As shown in fig. 1 (b), when the signal of the shared discharging rod is changed from V12 to V11, a phenomenon of signal delay is also generated.
Therefore, the problem of delay of the pulse signal of the shared discharging rod needs to be solved, so that the display image quality can be remarkably improved.
Disclosure of Invention
The application provides a display panel to solve the problem of sharing discharging rod pulse signal delay.
The application provides a display panel, it includes:
the sub-pixels are arranged in an array mode and comprise main area sub-pixels and secondary area sub-pixels, and the secondary area sub-pixels are electrically connected with the shared discharging rod;
when the sub-pixel is of a first polarity, the signal on the shared discharging rod is a first pulse signal; when the sub-pixel is of the second polarity, the signal on the shared discharging rod is a second pulse signal;
when the sub-pixel is switched from the first polarity to the second polarity, in a blanking time interval between two adjacent frames of pictures, the signal on the shared discharging rod is a third pulse signal, and the third pulse signal enables the potential of the shared discharging rod to reach a target potential in advance when the potential is switched from the first pulse signal to the second pulse signal.
Optionally, in some embodiments of the present application, when the first polarity is positive and the second polarity is negative, a potential of the third pulse signal is greater than a potential of the second pulse signal, and the potential of the second pulse signal is between a potential of the first pulse signal and a potential of the third pulse signal.
Optionally, in some embodiments of the present application, the blanking time interval includes a first time period, a second time period, and a third time period;
in the first period, the potential of the third pulse signal rises from the potential of the first pulse signal to a potential greater than the potential of the second pulse signal;
the potential of the third pulse signal is maintained at a potential greater than the potential of the second pulse signal in the second period;
in the third period, the potential of the third pulse signal is reduced from a potential greater than the potential of the second pulse signal to the potential of the second pulse signal.
Optionally, in some embodiments of the present application, in the first period, the potential of the third pulse signal rises from the potential of the first pulse signal to a first potential, and then from the first potential to a potential greater than the potential of the second pulse signal.
Optionally, in some embodiments of the present application, in the third period, the potential of the third pulse signal is reduced from a potential greater than the potential of the second pulse signal to a second potential, and then from the second potential to the potential of the second pulse signal.
Optionally, in some embodiments of the present application, when the first polarity is a negative polarity and the second polarity is a positive polarity, a potential of the second pulse signal is greater than a potential of the third pulse signal, and the potential of the second pulse signal is between a potential of the first pulse signal and a potential of the third pulse signal.
Optionally, in some embodiments of the present application, the blanking time interval includes a fourth time period, a fifth time period, and a sixth time period;
in the fourth period, the potential of the third pulse signal is reduced from the potential of the first pulse signal to a potential smaller than the potential of the second pulse signal;
in the fifth period, the potential of the third pulse signal is maintained at a potential smaller than the potential of the second pulse signal;
in the sixth period, the potential of the third pulse signal rises from a potential smaller than the potential of the second pulse signal to the potential of the second pulse signal.
Optionally, in some embodiments of the present application, in the fourth period, the potential of the third pulse signal decreases from the potential of the first pulse signal to a third potential, and then from the third potential to a potential smaller than the potential of the second pulse signal.
Optionally, in some embodiments of the present application, in the sixth period, the potential of the third pulse signal rises from a potential smaller than the potential of the second pulse signal to a fourth potential, and then from the fourth potential to the potential of the second pulse signal.
Optionally, in some embodiments of the present application, a frequency of the third pulse signal is the same as a frequency of a blanking time of a driving signal of the display panel.
The application provides a display panel, wherein the display panel includes: the display device comprises a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a main region sub-pixel and a secondary region sub-pixel, and the secondary region sub-pixels are electrically connected with a shared discharging rod; when the sub-pixel is of a first polarity, the signal on the shared discharging rod is a first pulse signal; when the sub-pixel is of the second polarity, the signal on the shared discharging rod is a second pulse signal; when the sub-pixel is switched from the first polarity to the second polarity, in a blanking time interval between two adjacent frames of pictures, the signal on the shared discharging rod is a third pulse signal, and the third pulse signal enables the potential of the shared discharging rod to reach a target potential in advance when the potential is switched from the first pulse signal to the second pulse signal. According to the method, before the first pulse signal and the second pulse signal are switched, the third pulse signal is applied to the sharing discharging rod, the third pulse signal is located in the blanking time interval of the driving signal of the display panel, so that the potential of the sharing discharging rod reaches the target potential in advance when the first pulse signal is switched to the second pulse signal, the problem of delay of the pulse signal of the sharing discharging rod is solved, and the display image quality is remarkably improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic delay diagram of a prior art shared discharge bar pulse signal;
fig. 2 is an equivalent circuit diagram of an 8Domin pixel of the display panel provided in the present application;
fig. 3 is a schematic diagram of a pulse signal of a shared discharging rod of a first embodiment of a display panel provided in the present application;
fig. 4 is a schematic diagram of a pulse signal of a shared discharging rod of a second embodiment of a display panel provided in the present application;
fig. 5 is a schematic diagram of a pulse signal of a shared discharging rod of a third embodiment of a display panel provided in the present application;
fig. 6 is a schematic diagram of a pulse signal of a shared discharging rod of a fourth embodiment of a display panel provided in the present application;
fig. 7 is a schematic diagram of a pulse signal of a shared discharging rod of a fifth embodiment of a display panel provided by the present application;
fig. 8 is a schematic diagram of a pulse signal of a shared discharging rod of a sixth embodiment of a display panel provided in the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and the like indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The present application provides a display panel, which is described in detail below. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present application.
Referring to fig. 2 and fig. 3, fig. 2 is an equivalent circuit diagram of an 8Domin pixel of the display panel provided by the present application, and fig. 3 is a schematic diagram of a Vshare pulse signal of a first embodiment of the display panel provided by the present application. The application provides a display panel, which comprises a plurality of sub-pixels 100, wherein the sub-pixels 100 are divided into a main region sub-pixel 10 and a sub-region sub-pixel 20, and the sub-region sub-pixel 20 is electrically connected with a shared discharging rod Vshare.
When the sub-pixel 100 is of the first polarity, the signal on the shared discharging rod Vshare is the first pulse signal VL; when the sub-pixel 100 is of the second polarity, the signal on the common discharging rod Vshare is the second pulse signal VH. The signal of the shared discharging rod Vshare is adjusted to be switched between the first pulse signal VL and the second pulse signal VH, so that the release voltage of the sub-pixels in the secondary region is adjusted, the ratio of the pixel voltage of the sub-pixels in the secondary region to the pixel voltage of the sub-pixels in the main region can be adjusted, and the purposes of improving the visual angle with low gray scale and improving the penetration with high gray scale are achieved through an alternate power supply mode of the shared discharging rod Vshare.
Due to the existence of the resistive-capacitive load, a delay problem occurs when the signal of the common discharging rod Vshare is switched between the first pulse signal VL and the second pulse signal VH.
Therefore, when the sub-pixel 100 is switched from the first polarity to the second polarity, the signal on the shared discharging rod Vshare is the third pulse signal VM in the blanking time t interval between two adjacent frames, and the third pulse signal VM makes the potential of the shared discharging rod Vshare reach the target potential in advance when the potential is switched from the first pulse signal VL to the second pulse signal VH.
Specifically, when the potential of the first pulse signal VL is smaller than the potential of the second pulse signal VH, the signal of the shared discharging rod Vshare is made to be the third pulse signal VM in the blanking time t interval between two adjacent frames before the first pulse signal VL is switched to the second pulse signal VH, and the potential of the third pulse signal VM is greater than the potential of the second pulse signal VH, so that even if a resistive-capacitive load is present, the signal of the shared discharging rod Vshare can be made to reach the target potential in advance.
Further, in some embodiments, the first polarity is positive, the second polarity is negative, and the potential of the third pulse signal VM is greater than the potential of the second pulse signal VH, which is between the potential of the first pulse signal VL and the potential of the third pulse signal VM.
When the sub-pixel 100 is of the first polarity, the signal of the shared discharging rod Vshare is the first pulse signal VL, when the sub-pixel 100 is of the second polarity, the signal of the shared discharging rod Vshare is the second pulse signal VH, and when the sub-pixel 100 is switched from the positive polarity to the negative polarity, the signal of the shared discharging rod Vshare is also switched from the first pulse signal VL to the second pulse signal VH, so that the signal on the shared discharging rod Vshare is first set to the third pulse signal VM in the blanking time t interval between two adjacent frames of pictures, and the potential of the third pulse signal VM is greater than the potential of the second pulse signal VH, so that even if a resistive-capacitive load exists, the signal of the shared discharging rod Vshare can reach the target potential in advance, the problem of delay of the pulse signal of the shared discharging rod Vshare is solved, and the display quality is remarkably improved.
In some embodiments, the blanking time t interval includes a first time period t1, a second time period t2, and a third time period t3; in the first period t1, the potential of the third pulse signal VM rises from the potential of the first pulse signal VL to a potential greater than the potential of the second pulse signal VH; in the second period t2, the potential of the third pulse signal VM is maintained at a potential greater than the potential of the second pulse signal VH; in the third period t3, the potential of the third pulse signal VM decreases from a potential greater than the potential of the second pulse signal VH to the potential of the second pulse signal VH.
Since the signal of the common discharging rod Vshare generates a large instantaneous current during the switching process, the instantaneous current may have an adverse effect on the display of the display panel. The blanking time t interval of the embodiment includes a first time period t1, a second time period t2 and a third time period t3, and the signals of the shared charging bar Vshare are in a sectional adjustment mode in the blanking time t interval, so that the signals of the shared charging bar Vshare can be prevented from generating larger instant current when the electric potential of the signals of the shared charging bar Vshare is instantly and rapidly switched, thereby greatly reducing the instant current and reducing the influence of the instant current on the display panel.
In some embodiments, the frequency of the third pulse signal VM is the same as the frequency of the blanking time t of the driving signal of the display panel. That is, in the display process of the display panel, each display period of the display panel is guaranteed to input the third pulse signal VM to the shared discharging rod Vshare, so that the display quality of each display period of the display panel can be further effectively guaranteed.
In some embodiments, the duration of the third pulse signal VM is close to or equal to the blanking time t of the driving signal of the display panel. By fully utilizing the blanking time t to adjust the potential of the shared discharging rod Vshare to a position higher than the potential of the second pulse signal VH, the signal of the shared discharging rod Vshare can be stabilized for a short period of time higher than the target value, and then the signal of the shared discharging rod Vshare is adjusted to the second pulse signal VH, so that the delay of the pulse signal of the shared discharging rod Vshare is smaller, and a better display effect is obtained.
In some embodiments, the duration of the second pulse signal VH and the first pulse signal VL is a duration of one frame of the display panel. Time of one frame=1/refresh rate, if the refresh rate is 60HZ, time of one frame is 1/60=16.7 ms, and if the refresh rate is 120HZ, time of one frame is 1/120=8.3 ms. Setting the durations of the second pulse signal VH and the first pulse signal VL to correspond to the duration of one frame of the display panel can improve the display quality of the display panel.
Further, in some embodiments, the potential values of the second pulse signal VH and the first pulse signal VL range from 0 to 14 volts.
Specifically, in some embodiments, the potential value of the second pulse signal VH is 10 volts, and the potential value of the first pulse signal VL is 7 volts. That is, the first pulse signal VL of 7 volts is applied to the common discharging rod Vshare when the sub-pixel is positive, and the second pulse signal VH of 10 volts is applied to the common discharging rod Vshare when the sub-pixel is negative.
Specifically, in some embodiments, the potential value of the second pulse signal VH is 8 volts, and the potential value of the first pulse signal VL is 4 volts. That is, the first pulse signal VL of 4 volts is applied to the common discharging rod Vshare when the sub-pixel is positive, and the second pulse signal VH of 8 volts is applied to the common discharging rod Vshare when the sub-pixel is negative.
Specifically, in some embodiments, referring to fig. 2, the main area sub-pixel 10 includes a first thin film transistor T1, and the sub-area sub-pixel includes a second thin film transistor T2 and a third thin film transistor T3;
wherein, within the sub-pixel 100, the gate electrode of the first thin film transistor T1, the gate electrode of the second thin film transistor T2 and the gate electrode of the third thin film transistor T3 are connected to a scan line, one of the source electrode and the drain electrode of the first thin film transistor T1 and one of the source electrode and the drain electrode of the second thin film transistor T2 are connected to a data line, the pixel electrode of the main region sub-pixel 10 is connected to the other of the source electrode and the drain electrode of the first thin film transistor T1, the pixel electrode of the sub-region sub-pixel 20 is connected to the other of the source electrode and the drain electrode of the second thin film transistor T2, the other of the source electrode and the drain electrode of the third thin film transistor T3 is connected to a common drain bar Vshare.
Referring to fig. 4, fig. 4 is a schematic diagram of a pulse signal of a shared discharging rod of a second embodiment of a display panel provided in the present application. This embodiment differs from the embodiment shown in fig. 3 in that: in the first period t1, the potential of the third pulse signal VM increases from the potential of the first pulse signal VL to a first potential V1, and then from the first potential V1 to a potential greater than the potential of the second pulse signal VH.
In this embodiment, in the first period t1, the potential of the third pulse signal VM rises from the potential of the first pulse signal VL to the first potential V1, and then from the first potential V1 to a potential greater than the potential of the second pulse signal VH, and the mode is set to a multi-stage boosting mode, so that the instant change of the potential of the shared charging bar Vshare in the first period t1 is avoided, the instant current is further reduced, and the influence of the instant current on the display panel is reduced. The first potential V1 may be an average value between the potential of the first pulse signal VL and the potential of the third pulse signal VM.
Referring to fig. 5, fig. 5 is a schematic diagram of a pulse signal of a shared discharging rod of a second embodiment of a display panel provided by the present application. This embodiment differs from the embodiment shown in fig. 3 in that: in the third period t3, the potential of the third pulse signal VM decreases from a potential greater than the potential of the second pulse signal VH to a second potential V2, and then from the second potential V2 to the potential of the second pulse signal VH.
In this embodiment, in the third time period t3, the third pulse signal VM is reduced from a potential greater than the potential of the second pulse signal VH to the second potential V2, and then from the second potential V2 to the potential of the second pulse signal VH, and the mode of multi-stage voltage reduction is set, so that the instant change of the potential of the shared charging rod Vshare in the third time period t3 is avoided, the instant current is further reduced, and the influence of the instant current on the display panel is reduced. The second potential V2 may be an average value between the potential of the second pulse signal VH and the potential of the third pulse signal VM.
Referring to fig. 6, fig. 6 is a schematic diagram of a pulse signal of a shared discharging rod of a fourth embodiment of a display panel provided by the present application. This embodiment differs from the embodiment shown in fig. 3 in that: when the first polarity is negative and the second polarity is positive, the potential of the second pulse signal VH is greater than the potential of the third pulse signal VM, and the potential of the second pulse signal VH is between the potential of the first pulse signal VL and the potential of the third pulse signal VM.
When the sub-pixel 100 is of the first polarity, the signal of the shared discharging rod Vshare is the first pulse signal VL, when the sub-pixel 100 is of the second polarity, the signal of the shared discharging rod Vshare is the second pulse signal VH, and when the sub-pixel 100 is switched from the negative polarity to the positive polarity, the signal of the shared discharging rod Vshare is also switched from the first pulse signal VL to the second pulse signal VH, so that the signal on the shared discharging rod Vshare is first set to the third pulse signal VM in the blanking time t interval between two adjacent frames of pictures, and the potential of the second pulse signal VH is greater than the potential of the third pulse signal VM, so that even if a resistive-capacitive load exists, the signal of the shared discharging rod Vshare can reach the target potential in advance, the problem of delay of the shared discharging rod Vshare pulse signal is solved, and the display quality is remarkably improved.
In some embodiments, the blanking time t interval includes a fourth time period t4, a fifth time period t5, and a sixth time period t6; in the fourth period t4, the potential of the third pulse signal VM decreases from the potential of the first pulse signal VL to a potential smaller than the potential of the second pulse signal VH; in the fifth period t5, the potential of the third pulse signal VM is maintained at a potential smaller than the potential of the second pulse signal VH; in the sixth period t6, the potential of the third pulse signal VM rises from a potential smaller than the potential of the second pulse signal VH to the potential of the second pulse signal VH.
Since the signal of the common discharging rod Vshare generates a large instantaneous current during the switching process, the instantaneous current may have an adverse effect on the display of the display panel. The blanking time t interval of the embodiment includes a fourth time period t4, a fifth time period t5 and a sixth time period t6, and the signals of the shared charging bar Vshare are in a sectional adjustment mode in the blanking time t interval, so that the signal potential of the shared charging bar Vshare can be prevented from generating larger instantaneous current when the signal potential is instantaneously and rapidly switched, thereby greatly reducing the instantaneous current and reducing the influence of the instantaneous current on the display panel.
Referring to fig. 7, fig. 7 is a schematic diagram of a Vshare pulse signal of a fifth embodiment of a display panel provided by the present application. This embodiment differs from the embodiment shown in fig. 6 in that: in the fourth period t4, the potential of the third pulse signal VM decreases from the potential of the first pulse signal VL to a third potential V3, and then from the third potential V3 to a potential smaller than the potential of the second pulse signal VH.
In the embodiment, in the fourth time period t4, the potential of the third pulse signal VM is reduced from the potential of the first pulse signal VL to the third potential V3, and then the third potential V3 is reduced to a potential smaller than the potential of the second pulse signal VH, so that the potential of the shared charging bar is prevented from instantaneously changing too much in the fourth time period t4, thereby further reducing the instantaneous current and reducing the influence of the instantaneous current on the display panel. The third potential V3 may be an average value between the potential of the first pulse signal VL and the potential of the third pulse signal VM.
Referring to fig. 8, fig. 8 is a schematic diagram of a Vshare pulse signal of a sixth embodiment of a display panel provided by the present application. This embodiment differs from the embodiment shown in fig. 6 in that: in the sixth period t6, the potential of the third pulse signal VM increases from a potential smaller than the potential of the second pulse signal VH to a fourth potential V4, and then from the fourth potential V4 to the potential of the second pulse signal VH.
In this embodiment, in the sixth time period t6, the potential of the third pulse signal VM is increased from a potential smaller than the potential of the second pulse signal VH to the fourth potential V4, and then from the fourth potential V4 to the potential of the second pulse signal VH, and the mode is set to a multi-stage boosting mode, so that the momentary change of the potential of the shared charging bar in the sixth time period t6 is avoided, the momentary current is further reduced, and the influence of the momentary current on the display panel is reduced. The fourth potential V4 may be an average value between the potential of the second pulse signal VH and the potential of the third pulse signal VM.
The foregoing has described in detail a display panel provided by embodiments of the present application, and specific examples have been set forth herein to illustrate the principles and embodiments of the present application, the above examples being provided only to assist in understanding the methods of the present application and their core ideas; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present application, the contents of the present specification should not be construed as limiting the present application in summary.

Claims (9)

1. The display panel is characterized by comprising a plurality of sub-pixels which are arranged in an array, wherein each sub-pixel comprises a main region sub-pixel and a sub-region sub-pixel, and the sub-region sub-pixels are electrically connected with a shared discharging rod;
when the sub-pixel is of a first polarity, the signal on the shared discharging rod is a first pulse signal; when the sub-pixel is of the second polarity, the signal on the shared discharging rod is a second pulse signal;
when the sub-pixel is switched from the first polarity to the second polarity, in a blanking time interval between two adjacent frames of pictures, the signal on the shared discharging rod is a third pulse signal, and the third pulse signal enables the potential of the shared discharging rod to reach a target potential in advance when the potential of the shared discharging rod is switched from the first pulse signal to the second pulse signal;
the first polarity is positive, and the second polarity is negative, the potential of the third pulse signal is greater than the potential of the second pulse signal, and the potential of the second pulse signal is between the potential of the first pulse signal and the potential of the third pulse signal.
2. The display panel of claim 1, wherein the blanking interval comprises a first period of time, a second period of time, and a third period of time;
in the first period, the potential of the third pulse signal rises from the potential of the first pulse signal to a potential greater than the potential of the second pulse signal;
the potential of the third pulse signal is maintained at a potential greater than the potential of the second pulse signal in the second period;
in the third period, the potential of the third pulse signal is reduced from a potential greater than the potential of the second pulse signal to the potential of the second pulse signal.
3. The display panel according to claim 2, wherein in the first period, the potential of the third pulse signal rises from the potential of the first pulse signal to a first potential, and then from the first potential to a potential larger than the potential of the second pulse signal.
4. The display panel according to claim 2, wherein in the third period of time, the potential of the third pulse signal is decreased from a potential larger than the potential of the second pulse signal to a second potential, and then decreased from the second potential to the potential of the second pulse signal.
5. The display panel according to claim 1, wherein when the first polarity is negative and the second polarity is positive, the potential of the second pulse signal is larger than the potential of the third pulse signal, and the potential of the second pulse signal is between the potential of the first pulse signal and the potential of the third pulse signal instead of the first polarity being positive, and when the second polarity is negative, the potential of the third pulse signal is larger than the potential of the second pulse signal, and the potential of the second pulse signal is between the potential of the first pulse signal and the potential of the third pulse signal.
6. The display panel of claim 5, wherein the blanking interval includes a fourth period of time, a fifth period of time, and a sixth period of time;
in the fourth period, the potential of the third pulse signal is reduced from the potential of the first pulse signal to a potential smaller than the potential of the second pulse signal;
in the fifth period, the potential of the third pulse signal is maintained at a potential smaller than the potential of the second pulse signal;
in the sixth period, the potential of the third pulse signal rises from a potential smaller than the potential of the second pulse signal to the potential of the second pulse signal.
7. The display panel according to claim 6, wherein in the fourth period, the potential of the third pulse signal is decreased from the potential of the first pulse signal to a third potential, and then decreased from the third potential to a potential smaller than the potential of the second pulse signal.
8. The display panel according to claim 6, wherein in the sixth period, the potential of the third pulse signal rises from a potential smaller than the potential of the second pulse signal to a fourth potential, and then from the fourth potential to the potential of the second pulse signal.
9. The display panel according to claim 1, wherein a frequency of the third pulse signal is the same as a frequency of a blanking time of a driving signal of the display panel.
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Publication number Priority date Publication date Assignee Title
CN114822368B (en) * 2022-06-06 2023-06-30 Tcl华星光电技术有限公司 Driving circuit, driving method and display panel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005227474A (en) * 2004-02-12 2005-08-25 Seiko Epson Corp Liquid crystal device, driving circuit for liquid crystal device, its driving method, and electronic equipment

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06208338A (en) * 1993-01-11 1994-07-26 Sharp Corp Driving circuit for display device
TW502234B (en) * 2001-05-21 2002-09-11 Chi Mei Optoelectronics Corp Sub-frame driving method
JP2003244936A (en) * 2002-02-18 2003-08-29 Ricoh Co Ltd Power unit
GB0318611D0 (en) * 2003-08-08 2003-09-10 Koninkl Philips Electronics Nv Circuit for signal amplification and use of the same in active matrix devices
CN101471055B (en) * 2007-12-25 2012-08-08 奇美电子股份有限公司 Transient control drive method and circuit, and image display system thereof
CN101217252B (en) * 2008-01-04 2010-09-01 华中科技大学 A soft start circuit for PDM DC-DC switching power supply
CN101771339A (en) * 2008-12-29 2010-07-07 深圳艾科创新微电子有限公司 Soft start circuit for switch power supply
CN103140885A (en) * 2010-09-03 2013-06-05 高通Mems科技公司 System and method of leakage current compensation when sensing states of display elements
US20130321379A1 (en) * 2012-05-31 2013-12-05 Qualcomm Mems Technologies, Inc. System and method of sensing actuation and release voltages of interferometric modulators
FR3018653B1 (en) * 2014-03-11 2016-03-04 E2V Semiconductors IMAGE CAPTURE METHOD WITH DARK CURRENT REDUCTION AND LOW CONSUMPTION
CN106712486B (en) * 2017-03-09 2019-02-15 中国人民解放军海军航空工程学院 A kind of high-voltage switch power supply start-up system and method
KR102312348B1 (en) * 2017-06-30 2021-10-13 엘지디스플레이 주식회사 Display panel and electroluminescence display using the same
CN112198726A (en) * 2020-10-30 2021-01-08 Tcl华星光电技术有限公司 Multi-domain vertical alignment mode display panel and display device thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005227474A (en) * 2004-02-12 2005-08-25 Seiko Epson Corp Liquid crystal device, driving circuit for liquid crystal device, its driving method, and electronic equipment

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