CN114333695A

CN114333695A - Display panel, repairing method and display device

Info

Publication number: CN114333695A
Application number: CN202111617462.4A
Authority: CN
Inventors: 张欢喜
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-04-12

Abstract

The embodiment of the application provides a display panel, a repairing method and a display device, wherein the display panel comprises: a plurality of pixel circuits, a light emission control signal line, and a first power signal line, the pixel circuits including storage capacitors electrically connected to the first power signal line; at least one of the first power signal line, the light emission control signal line and the first plate includes a body portion and an extension portion electrically connected, and in a region where the extension portion is located, the light emission control signal line and the at least one of the first power signal line and the first plate at least partially overlap; the pixel circuit further includes at least one emission control transistor, at least one of the plurality of pixel circuits is a target pixel circuit, and an emission control signal line between a gate of the at least one emission control transistor of the target pixel circuit and an adjacent pixel circuit is disconnected and/or electrically connected to the first power signal line through the extension portion. The embodiment of the application can realize the restoration of the bright spot and improve the display effect of the display panel.

Description

Display panel, repairing method and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a display panel, a repairing method and a display device.

Background

With the development of display technology, display panels and display devices are applied more and more widely in life. The display panel may include a plurality of sub-pixels arranged in an array, and when one or more sub-pixels fail, the display panel may have "bright spots", which may be understood as abnormal sub-pixels (dots) that are normally bright. These "bright spots" in turn can lead to poor display performance of the display panel or to poor display of the display panel.

Disclosure of Invention

The embodiment of the application provides a display panel, a repairing method and a display device, which can repair bright spots appearing in the display panel and improve the display effect of the display panel.

In a first aspect, an embodiment of the present application provides a display panel, including: a plurality of pixel circuits, a light emission control signal line extending in a first direction, and a first power signal line extending in a second direction, the pixel circuits including storage capacitors having first plates electrically connected to the first power signal line, the first direction crossing the second direction; at least one of the first power signal line, the light-emitting control signal line and the first polar plate comprises a body part and an extension part which are electrically connected, and in at least partial area where the orthographic projection of the extension part on the light-emitting surface of the display panel is located, in the direction perpendicular to the plane where the display panel is located, at least one of the first power signal line and the first polar plate and the light-emitting control signal line are at least partially overlapped; the pixel circuit also comprises at least one light-emitting control transistor for controlling the light-emitting element to emit light, the light-emitting control signal line is electrically connected with the grid electrodes of the light-emitting control transistors of the M pixel circuits which are sequentially arranged along the first direction, and M is a positive integer; at least one of the plurality of pixel circuits is a target pixel circuit, a light emission control signal line between a gate of at least one light emission control transistor of the target pixel circuit and an adjacent pixel circuit is disconnected, and/or a gate of at least one light emission control transistor of the target pixel circuit is electrically connected to the first power signal line through the extension portion.

In a second aspect, an embodiment of the present application provides a repair method, where the repair method is applied to the display panel provided in the first aspect, and the repair method includes: detecting a target pixel circuit in which a bright point is located from among the plurality of pixel circuits; disconnecting a light emission control signal line between a gate of at least one light emission control transistor of a target pixel circuit and an adjacent pixel circuit; and/or a gate of at least one light emission control transistor of the target pixel circuit is electrically connected to the first power supply signal line through the extension portion.

In a third aspect, an embodiment of the present application provides a display device, which includes the display panel provided in the first aspect.

In the display panel, the repairing method and the display device of the embodiment of the application, for a target pixel circuit (namely, a pixel circuit in a normally-on abnormal sub-pixel) in the display panel, a light-emitting control signal line between a gate of at least one light-emitting control transistor of the target pixel circuit and an adjacent pixel circuit is disconnected, and/or the gate of at least one light-emitting control transistor of the target pixel circuit is electrically connected with a first power signal line through an extension portion. Therefore, at least one light-emitting control transistor of the target pixel circuit is in a cut-off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, the normally-on abnormal sub-pixel is made not to emit light any more, the repair of a bright point is realized, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic top view of a display panel;

fig. 2 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a local layout structure of a display panel provided in the embodiment of the present application;

fig. 4 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

fig. 5 is a schematic partial cross-sectional view of a first light-emitting control transistor in a display panel according to an embodiment of the present application;

fig. 6 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

fig. 7 is a schematic partial cross-sectional view of a display panel according to an embodiment of the present application;

fig. 8 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

fig. 9 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

fig. 10 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

FIG. 11 is a schematic cross-sectional view taken along line A-A' of FIG. 10;

fig. 12 is a schematic circuit diagram of a display panel according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

fig. 14 is a schematic diagram of another local layout structure of a display panel provided in the embodiment of the present application;

FIG. 15 is a schematic flow chart of a repairing method according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

Note that the transistors in the embodiments of the present application are described using P-type transistors as examples, but the transistors are not limited to P-type transistors, and may be replaced with N-type transistors. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

In the embodiments of the present application, the first node and the second node are defined only for convenience of describing the circuit structure, and the first node and the second node are not an actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the prior art:

as shown in fig. 1, the display panel 10 'includes a plurality of sub-pixels 100' arranged in a row direction X and a column direction Y. Here, the color of the sub-pixel 100 ' is not limited, and for example, the display panel 10 ' may include sub-pixels 100 ' of three colors of red, green, and blue. The sub-pixel 100 'may in turn include a pixel circuit 101' and a light emitting element 102 'electrically connected to the pixel circuit 101'. The pixel circuit 101 'can drive the light emitting element 102' to emit light. The inventor of the present application has found that when the pixel circuit 101 'fails (e.g., the pixel circuit 101' is short-circuited), the pixel circuit 101 'continuously drives the corresponding electrically connected light emitting element 102' to emit light, so that a "bright spot" phenomenon occurs. These "bright spots" in turn can lead to poor display performance of the display panel or to poor display of the display panel.

In view of the above research of the inventors, embodiments of the present application provide a display panel, a repairing method, and a display device, which can solve the technical problem of the display panel appearing bright spots in the related art.

The technical idea of the embodiment of the application is as follows: for a target pixel circuit (i.e., a pixel circuit in a normally-on abnormal sub-pixel) in the display panel, the gate of at least one emission control transistor of the target pixel circuit is disconnected from an emission control signal line between adjacent pixel circuits, and/or the gate of at least one emission control transistor of the target pixel circuit is electrically connected to the first power supply signal line through an extension portion. Therefore, at least one light-emitting control transistor of the target pixel circuit is in a cut-off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, the normally-on abnormal sub-pixel is made not to emit light any more, the repair of a bright point is realized, and the display effect of the display panel is improved.

The following first describes a display panel provided in an embodiment of the present application.

For better explaining the present application with reference to the drawings, the following explanation is made by taking an example in which the pixel circuit includes seven transistors and one storage capacitor (i.e., a 7T1C pixel circuit), and it should be understood that this is not intended to limit the present application, and the pixel circuit may also take other circuit configurations, such as a 7T2C pixel circuit, a 9T1C pixel circuit, or a 9T2C pixel circuit. Among them, the 7T2C pixel circuit, i.e. the pixel circuit, includes seven transistors and two storage capacitors, and so on for other types of pixel circuits.

As shown in fig. 2 and 3 in conjunction, the display panel 20 includes a plurality of pixel circuits 200, a light emission control signal line Emit extending in a first direction X, and a first power supply signal line PVDD extending in a second direction Y, the first direction X and the second direction Y crossing each other. It will be readily appreciated that the first power signal line PVDD is used to provide a positive voltage signal, such as a voltage signal of 4.6V or other positive voltage value. The pixel circuit 200 includes a storage capacitor Cst, a first plate of which is electrically connected to the first power signal line PVDD, and a second plate of which is electrically connected to the first node N1, for maintaining a potential of the first node N1.

In the embodiment of the present application, at least one of the first power supply signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst includes the body portion B1 and the extension portion Y1, which are electrically connected. The extension portion is understood to be a portion extending from the original body portion. The material of the body portion B1 and the material of the extension portion Y1 may be the same or different, and this embodiment of the present application is not limited thereto. Wherein at least one of the first power supply signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst includes the body portion B1 and the extension portion Y1, it can be understood to include the following cases: (1) any one of the first power supply signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst includes a body portion B1 and an extension portion Y1; (2) any two of the first power supply signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst include the body portion B1 and the extension portion Y1; (3) the first power signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst all include the body portion B1 and the extension portion Y1. Fig. 3 illustrates only a case where the emission control signal line Emit includes the body portion B1 and the extension portion Y1.

It is noted that, in at least a partial region where the orthographic projection of the extension portion Y1 on the light emitting surface of the display panel 20 is located, at least one of the first power signal line PVDD and the first plate of the storage capacitor Cst and the emission control signal line Emit at least partially overlap in a direction perpendicular to the plane of the display panel 20. It can be simply understood that at least one of the first power signal line PVDD and the first plate of the storage capacitor Cst may at least partially overlap the emission control signal line Emit (in a region where the front projection of the extension Y1 is located) in a direction perpendicular to the plane of the display panel 20 by adding the extension Y1.

For example, the first power supply signal line PVDD includes the body portion B1 and the extension portion Y1, and the extension portion Y1 of the first power supply signal line PVDD at least partially overlaps the emission control signal line Emit in a direction perpendicular to the plane of the display panel 20. For another example, the first plate of the storage capacitor Cst includes the body portion B1 and the extension portion Y1, and the extension portion Y1 of the first plate of the storage capacitor Cst overlaps at least part of the emission control signal line Emit in a direction perpendicular to the plane of the display panel 20. For another example, the emission control signal line Emit includes a body portion B1 and an extension portion Y1, and the extension portion Y1 of the emission control signal line Emit at least partially overlaps the first power signal line PVDD and/or the first plate of the storage capacitor Cst in a direction perpendicular to the plane of the display panel 20.

Of course, it is also possible that at least two of the first plates of the first power supply signal line PVDD, the emission control signal line Emit, and the storage capacitor Cst include the body portion B1 and the extension portion Y1, and the extension portions Y1 of the at least two at least partially overlap in a direction perpendicular to the plane of the display panel 20. For example, the first plates of the emission control signal line Emit and the storage capacitor Cst each include a body portion B1 and an extension portion Y1, and the extension portion Y1 of the emission control signal line Emit and the extension portion Y1 of the first plate of the storage capacitor Cst at least partially overlap in a direction perpendicular to the plane of the display panel 20.

The technical effect of the embodiment of the present application of adding the extension part Y1 is: by additionally arranging the extension part Y1, when a bright spot is repaired subsequently to the pixel circuit 200, laser can be directly performed on the extension part Y1, so that at least one of the first power signal line PVDD and the first plate of the storage capacitor Cst is connected with the emission control signal line Emit in a laser manner. Without the extension Y1, it is difficult to connect at least one of the first power signal line PVDD and the first plate of the storage capacitor Cst to the emission control signal line Emit by a laser process, or if it is possible to connect them, other wirings or devices in the pixel circuit 200 may be damaged by laser, for example, an active layer overlapping the first power signal line PVDD in a direction perpendicular to the plane of the display panel.

With continued reference to fig. 2 and 3, the pixel circuit 200 further includes at least one emission control transistor MF for controlling the light emission of the light emitting element, the emission control signal line Emit is electrically connected to the gates of the emission control transistors MF of the M pixel circuits 200 sequentially arranged along the first direction X, and M is a positive integer. That is, the display panel 20 may include a plurality of emission control signal lines Emit, and each emission control signal line Emit may be electrically connected to the gate electrodes of the emission control transistors MF of one or more rows of the pixel circuits 200. It should be noted that the light emission control transistor MF can be at least one of the first light emission control transistor M6 and the second light emission control transistor M7, and different situations of the light emission control transistor MF will be described in detail below, and will not be described herein again.

It is easily understood that the emission control signal line Emit may multiplex the gate of the emission control transistor MF. That is, as shown in fig. 3, in a direction perpendicular to the plane of the display panel 20, a portion where the emission control signal line Emit overlaps with the channel region of the emission control transistor MF serves as the gate of the emission control transistor MF.

With continued reference to fig. 3, at least one pixel circuit 200 of the plurality of pixel circuits 200 is a target pixel circuit 200A, and the target pixel circuit 200A can be understood as a pixel circuit in an abnormal sub-pixel that is normally on. In some embodiments, the gate of at least one emission control transistor MF of the target pixel circuit 200A may be disconnected from the emission control signal line Emit between the adjacent pixel circuits 200, so that the gate of at least one emission control transistor MF in the target pixel circuit 200A does not receive the emission control signal transmitted by the emission control signal line Emit, so that at least one emission control transistor MF in the target pixel circuit 200A is in an off state. Thus, the driving current in the target pixel circuit 200A cannot reach the anode of the corresponding light emitting element, so that the normally-on abnormal sub-pixel does not emit light any more, and the bright point is repaired. In another embodiment, the gate of at least one emission control transistor MF of the target pixel circuit 200A may be electrically connected to the first power signal line PVDD through the extension portion Y1. Since the first power signal line PVDD outputs an off level, at least one emission control transistor MF in the target pixel circuit 200A is in an off state, so that the driving current in the target pixel circuit 200A cannot reach the anode of the corresponding light emitting element, and the normally-on abnormal sub-pixel no longer emits light, thereby realizing the repair of the bright point.

It is readily understood that, in still other embodiments, the gate of at least one emission control transistor MF of the target pixel circuit 200A may be electrically connected to the first power supply signal line PVDD through the extension portion Y1 on the basis that the emission control signal line Emit between the gate of at least one emission control transistor MF of the target pixel circuit 200A and the adjacent pixel circuit 200 is disconnected. Therefore, on one hand, the driving current in the target pixel circuit 200A can not reach the anode of the corresponding light-emitting element, so that the normally-bright abnormal sub-pixel can not emit light any more, and the bright point can be repaired; on the other hand, since the emission control signal line Emit between the gate of at least one emission control transistor MF of the target pixel circuit 200A and the adjacent pixel circuit 200 is disconnected, the first power supply signal transmitted by the first power supply signal line PVDD can be prevented from entering the adjacent pixel circuit 200, and the adjacent pixel circuit 200 can be ensured to display normally; on the other hand, since the gate of the at least one emission control transistor MF of the target pixel circuit 200A is electrically connected to the first power signal line PVDD through the extension portion Y1, the gate of the at least one emission control transistor MF in the target pixel circuit 200A is always kept at a high potential, which can prevent the at least one emission control transistor MF in the target pixel circuit 200A from being turned on by some interference signals and reduce the leakage current of the emission control transistor MF, and further ensure that the light emitting element connected to the target pixel circuit 200A does not emit light.

The display panel 20 of the embodiment of the application, for the target pixel circuit (i.e., the pixel circuit in the normally-on abnormal sub-pixel) in the display panel 20, disconnects the gate of at least one emission control transistor of the target pixel circuit from the emission control signal line between the adjacent pixel circuits, and/or electrically connects the gate of at least one emission control transistor of the target pixel circuit to the first power signal line through the extension portion. Therefore, at least one light-emitting control transistor of the target pixel circuit is in a cut-off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, the normally-on abnormal sub-pixel is made not to emit light any more, the repair of a bright point is realized, and the display effect of the display panel is improved.

The following describes different cases of the emission control transistor MF in detail.

As shown in fig. 2 and 4, according to some embodiments of the present application, the emission control transistor MF may be a first emission control transistor M6. Specifically, the pixel circuit 200 may include a driving transistor M1, the gate of the first light emission controlling transistor M6 may be electrically connected to the light emission control signal line Emit, the first pole of the first light emission controlling transistor M6 is electrically connected to the first power supply signal line PVDD, and the second pole of the first light emission controlling transistor M6 is electrically connected to the first pole of the driving transistor M1.

Exemplarily, the first light emitting control transistor M6 shown in fig. 5 is taken as an example. The first light emitting control transistor M6 includes an active layer b6, a gate g6, a source s6, and a drain d 6. The active layer includes a channel region and source and drain regions located at both sides of the channel region. The doping concentration of the channel region is lower than the doping concentrations of the source region and the drain region. For example, the active layer b6 of the first light emission controlling transistor M6 includes a lightly doped region CHD and two heavily doped regions PD located at both sides of the lightly doped region CHD. In a direction perpendicular to the plane of the display panel, the lightly doped region CHD overlaps with the gate g6 of the first light emission control transistor M6, the two heavily doped regions PD do not overlap with the gate g6 of the first light emission control transistor M6, the lightly doped region CHD is a channel region, and the two heavily doped regions PD are a source region and a drain region, respectively. Exemplarily, the source and drain regions of the active layer b6 may directly serve as the source s6 and the drain d6 of the first light emitting control transistor M6. The first pole of the first light emitting control transistor M6 may be a source s6, and the second pole of the first light emitting control transistor M6 may be a drain d 6. Alternatively, the first pole of the first light emitting control transistor M6 may be the drain d6, and the second pole of the first light emitting control transistor M6 may be the source s 6.

With continued reference to fig. 4, it is easily understood that the first pole of the first light emission control transistor M6 and the first power signal line PVDD may be located at different film layers, so that the first pole of the first light emission control transistor M6 and the first power signal line PVDD may be electrically connected through the via h 1. The second pole of the first light-emitting control transistor M6 may be located on the same layer as the first pole of the driving transistor M1, for example, both located on the active layer, so that the second pole of the first light-emitting control transistor M6 may be electrically connected to the first pole of the driving transistor M1 through a connection portion located on the active layer. The connection portion located in the active layer may be integrally formed with the second pole of the first light emitting control transistor M6 and the first pole of the driving transistor M1.

In the embodiment shown in fig. 4, the gate of the first light emission controlling transistor M6 in the target pixel circuit 200A may be disconnected from the light emission control signal line Emit between the adjacent pixel circuits 200, and/or the gate of the first light emission controlling transistor M6 in the target pixel circuit 200A is electrically connected to the first power supply signal line PVDD through the extension Y1.

In this way, the first light emitting control transistor M6 of the target pixel circuit is in the off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light emitting element, and the normally-on abnormal sub-pixel no longer emits light, thereby realizing the repair of the bright point and improving the display effect of the display panel.

As shown in fig. 2 and 6, according to other embodiments of the present application, the emission control transistor MF may be a second emission control transistor M7. Specifically, the pixel circuit 200 may include a driving transistor M1, the gate of the second light emission controlling transistor M7 may be electrically connected to the light emission control signal line Emit, the first pole of the second light emission controlling transistor M7 is electrically connected to the second pole of the driving transistor M1, and the second pole of the second light emission controlling transistor M7 is electrically connected to the first pole of the light emitting element. The first electrode of the light emitting element may be an anode of the light emitting element.

It is easy to understand that the first electrode of the second emission control transistor M7 and the second electrode of the driving transistor M1 are in the same film layer, for example, both in the active layer, so the first electrode of the second emission control transistor M7 can be electrically connected to the second electrode of the driving transistor M1 through a connection portion in the active layer. The connection portion of the active layer may be integrally formed with the first electrode of the second emission control transistor M7 and the second electrode of the driving transistor M1. The second electrode of the second light-emitting control transistor M7 is located at a different layer from the first electrode of the light-emitting device, so the second electrode of the second light-emitting control transistor M7 can be electrically connected to the first electrode of the light-emitting device through a via.

In the embodiment shown in fig. 6, the gate of the second light emission controlling transistor M7 in the target pixel circuit 200A may be disconnected from the light emission controlling signal line Emit between the adjacent pixel circuits 200, and/or the gate of the second light emission controlling transistor M7 in the target pixel circuit 200A is electrically connected to the first power supply signal line PVDD through the extension Y1.

In this way, the second light-emitting control transistor M7 of the target pixel circuit is in the off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, and the normally-on abnormal sub-pixel no longer emits light, thereby realizing the repair of the bright point and improving the display effect of the display panel.

In accordance with further embodiments of the present application, as shown in fig. 2 and fig. 3, optionally, the pixel circuit 200 may include two light emission control transistors MF, wherein one light emission control transistor MF is the first light emission control transistor M6, and the other light emission control transistor MF is the second light emission control transistor M7. The connection manner of the first light emitting control transistor M6 and the second light emitting control transistor M7 has been described in detail above, and is not described in detail herein.

In the embodiment shown in fig. 3, the gates of the first and second light emission controlling transistors M6 and M7 in the target pixel circuit 200A may be simultaneously disconnected from the light emission control signal line Emit between the adjacent pixel circuits 200, and/or the gates of the first and second light emission controlling transistors M6 and M7 in the target pixel circuit 200A are electrically connected to the first power supply signal line PVDD through the extension portion Y1.

Therefore, on one hand, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 of the target pixel circuit are both in a cut-off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, and further the normally-on abnormal sub-pixel does not emit light any more, thereby realizing the repair of a bright point and improving the display effect of the display panel; on the other hand, since any one of the first light-emission controlling transistor M6 and the second light-emission controlling transistor M7 is in the off state, the normally-on abnormal sub-pixel does not emit light any more, and at the same time, the first light-emission controlling transistor M6 and the second light-emission controlling transistor M7 are both in the off state, which is equivalent to "double insurance", and it is further ensured that the normally-on abnormal sub-pixel does not emit light.

The following description is given with respect to different overlapping situations of the extensions in connection with some embodiments of the present application.

As shown in fig. 3, according to some embodiments of the present application, optionally, for any one of the pixel circuits 200, the first plate of the storage capacitor Cst of the pixel circuit 20 may include a body portion B1 and an extension portion Y1, the body portion B1 being electrically connected to the first power supply signal line PVDD. In a direction perpendicular to the plane of the display panel, the extension Y1 of the first plate of the storage capacitor Cst and the emission control signal line Emit between the gate of the first emission control transistor M6 of the pixel circuit 200 and the gate of the second emission control transistor M7 of the pixel circuit 200 at least partially overlap. That is, the orthographic projection of the extension Y1 of the first plate of the storage capacitor Cst on the plane of the display panel at least partially overlaps the orthographic projection of the emission control signal line Emit between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the pixel circuit 200. The benefits of this are: when the pixel circuit 200 fails and the light emitting element connected to the pixel circuit 200 is normally on, the extension Y1 of the first plate of the storage capacitor Cst of the pixel circuit 200 may be electrically connected to the emission control signal line Emit between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the pixel circuit 200 by a laser process. In this way, the gate of the first emission control transistor M6 and the second emission control transistor M7 can be electrically connected to the first power supply signal line PVDD sequentially via the emission control signal line Emit between the gate of the transistor M6 and the gate of the transistor M7, the extension portion Y1 of the first plate of the storage capacitor Cst, and the main body portion B1 of the first plate of the storage capacitor Cst, thereby repairing the bright point.

The film layer distribution of the body portion B1 and the extension portion Y1 will be described with reference to the partial cross-sectional view of the display panel shown in fig. 7.

As shown in fig. 7, according to some embodiments of the present application, the display panel 20 may optionally include a substrate 01, a buffer layer 02 on a side of the substrate 01, and a driving device layer 03 disposed on a side of the buffer layer 02 far from the substrate 01. The driving device layer 03 may include a first metal layer M1, a second metal layer MC, and a third metal layer M2 that are stacked in a direction away from the substrate 01. An active layer b is disposed between the first metal layer M1 and the buffer layer 02. Insulating layers are provided between any adjacent metal layers and between the active layer b and the first metal layer M1. Illustratively, a gate insulating layer GI is disposed between the first metal layer M1 and the active layer b, a capacitor insulating layer IMD is disposed between the second metal layer MC and the first metal layer M1, and an interlayer dielectric ILD is disposed between the third metal layer M2 and the second metal layer MC. In addition, the display panel 20 may further include a planarization layer PLN, a pixel defining layer PDL, and the light emitting element may include an anode RE, a light emitting layer OM, and a cathode SE, which are stacked.

As shown in connection with fig. 3, according to some embodiments of the present application, optionally, the light emission control signal line Emit, the gate of the first light emission control transistor M6, and the second light emission control transistor M7 may be located in the first metal layer M1. The body portion B1 of the first plate of the storage capacitor Cst may be located at the second metal layer MC. The first power signal line PVDD may be located in the third metal layer M2. The body portion B1 of the first plate of the storage capacitor Cst and the first power signal line PVDD may be electrically connected through the via h 2. It is noted that, in some embodiments, the extension portion Y1 of the first plate of the storage capacitor Cst may be in the same film layer as the body portion B1 of the first plate of the storage capacitor Cst, for example, both in the second metal layer MC. In this way, since the body portion B1 and the extension portion Y1 of the first plate of the storage capacitor Cst are in the same film, the body portion B1 and the extension portion Y1 of the first plate of the storage capacitor Cst can be simultaneously prepared by one process, which is beneficial to simplifying the production process. On the other hand, in the direction perpendicular to the plane of the display panel, the emission control signal line Emit located in the first metal layer M1 is closer to the extension Y1 of the first plate of the storage capacitor Cst located in the second metal layer MC, so that the implementation of the laser process and the repair of the bright spot are facilitated.

Of course, in other embodiments, the extension Y1 of the first plate of the storage capacitor Cst may be located at a different film layer from the body portion B1 of the first plate of the storage capacitor Cst, for example, the extension Y1 of the first plate of the storage capacitor Cst is located at the third metal layer M2, the body portion B1 of the first plate of the storage capacitor Cst is located at the second metal layer MC, and the extension Y1 of the first plate of the storage capacitor Cst is electrically connected to the body portion B1 of the first plate of the storage capacitor Cst through a via hole. In this way, the extension Y1 of the first plate of the storage capacitor Cst may be electrically connected to the emission control signal line Emit through a laser process, which does not affect the implementation of the embodiment of the present application.

As shown in fig. 8, according to other embodiments of the present application, alternatively, unlike the embodiment shown in fig. 3, the first power supply signal line PVDD may include a body portion B1 and an extension portion Y1, the body portion B1 of the first power supply signal line PVDD may extend in the second direction Y, and the extension portion of the first power supply signal line PVDD may extend in the first direction X. The extension Y1 of the first power supply signal line PVDD and the emission control signal line Emit between the gate of the first emission control transistor M6 of the pixel circuit 200 and the gate of the second emission control transistor M7 of the pixel circuit 200 at least partially overlap in a direction perpendicular to the plane of the display panel. The benefits of this are: when a failure occurs in a certain pixel circuit 200 and the light emitting element connected to the pixel circuit 200 is normally on, the extension Y1 of the first power supply signal line PVDD may be electrically connected to the emission control signal line Emit between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the pixel circuit 200 by a laser process. In this way, the gate of the first light emission controlling transistor M6 and the second light emission controlling transistor M7 can be electrically connected to the main body portion B1 of the first power supply signal line PVDD through the light emission control signal line Emit between the gate of the transistor M6 and the gate of the transistor M7, and the extension portion Y1 of the first power supply signal line PVDD in this order, thereby repairing the bright point.

With continued reference to fig. 8, according to some embodiments of the present application, optionally, the light emission control signal line Emit, the gate of the first light emission control transistor M6, and the second light emission control transistor M7 may be located in the first metal layer M1. The body portion B1 of the first power signal line PVDD may be located at the third metal layer M2. It is noted that in some embodiments, the extension portion Y1 of the first power signal line PVDD may be in the same layer as the body portion B1 of the first power signal line PVDD, such as in the third metal layer M2. Thus, since the body portion B1 and the extension portion Y1 of the first power signal line PVDD are in the same film layer, the body portion B1 and the extension portion Y1 of the first power signal line PVDD can be simultaneously prepared in one process, which is beneficial to simplifying the manufacturing process.

Of course, in other embodiments, extension Y1 of first power signal line PVDD may be in a different layer from body portion B1 of first power signal line PVDD, for example, extension Y1 of first power signal line PVDD may be in second metal layer MC, body portion B1 of first power signal line PVDD may be in third metal layer M2, and extension Y1 of first power signal line PVDD may be electrically connected to body portion B1 of first power signal line PVDD by a via. In this way, the extension Y1 of the first power signal line PVDD and the emission control signal line Emit may also be electrically connected by a laser process, which does not affect the implementation of the embodiment of the present application.

As shown in fig. 9, according to further embodiments of the present application, the emission control signal line Emit may optionally include a body portion B1 and an extension portion Y1, unlike the embodiments shown in fig. 3 and 8. The body portion B1 of the light emission control signal line Emit may extend in the first direction X, and the extension portion Y1 of the light emission control signal line Emit may extend in the second direction Y. The extension Y1 of the emission control signal line Emit is located between the gate of the first emission control transistor M6 of the pixel circuit 200 and the gate of the second emission control transistor M7 of the pixel circuit 200. The extension Y1 of the emission control signal line Emit at least partially overlaps the first plate of the storage capacitor Cst of the pixel circuit 200 in a direction perpendicular to the plane of the display panel.

Specifically, the emission control signal line Emit may include a plurality of extension portions Y1. One extension Y1 may correspond to one pixel circuit 200. Each extension Y1 of the emission control signal line Emit is located between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the corresponding pixel circuit 200. Each extension Y1 of the emission control signal line Emit may at least partially overlap the first plate of the storage capacitor Cst of the corresponding pixel circuit 200 in a direction perpendicular to a plane in which the display panel is located.

The benefits of this are: when a failure occurs in a certain pixel circuit 200 and the light emitting element connected to the pixel circuit 200 is normally on, the extension Y1 of the emission control signal line Emit between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the pixel circuit 200 may be electrically connected to the first plate of the storage capacitor Cst of the pixel circuit 200 by a laser process. In this way, the gate of the first emission control transistor M6 and the second emission control transistor M7 can be electrically connected to the first power signal line PVDD sequentially via the main portion B1 and the extension portion Y1 of the emission control signal line Emit between the gate of the transistor M6 and the gate of the transistor M7, and the first plate of the storage capacitor Cst can be electrically connected to the first power signal line PVDD, thereby repairing the bright point.

With continued reference to fig. 9, according to some embodiments of the present application, optionally, the body portion B1 of the light emission control signal line Emit, the gate of the first light emission control transistor M6, and the second light emission control transistor M7 may be located in the first metal layer M1. The first plate of the storage capacitor Cst may be located at the second metal layer MC. The first power signal line PVDD may be located in the third metal layer M2. The first plate of the storage capacitor Cst and the first power signal line PVDD may be electrically connected through a via hole. It should be noted that the extension Y1 of the emission control signal line Emit may be in the same film layer as the body portion B1 of the emission control signal line Emit, for example, both in the first metal layer M1. Thus, since the body portion B1 and the extension portion Y1 of the emission control signal line Emit are in the same film layer, the body portion B1 and the extension portion Y1 of the emission control signal line Emit can be simultaneously prepared by one process, which is advantageous for simplifying the production process.

Of course, in other embodiments, the extending portion Y1 of the emission control signal line Emit may be in a different film layer from the body portion B1 of the emission control signal line Emit, for example, the extending portion Y1 of the emission control signal line Emit may be in the third metal layer M2, the body portion B1 of the emission control signal line Emit is in the first metal layer M1, and the extending portion Y1 of the emission control signal line Emit is electrically connected to the body portion B1 of the emission control signal line Emit through a via hole. In this way, the extension Y1 of the emission control signal line Emit may be electrically connected to the first plate of the storage capacitor Cst through a laser process, which does not affect the implementation of the embodiment of the present application.

With continued reference to fig. 9, the inventors of the present application have found that when the gate of the driving transistor M1 and the emission control signal line Emit are in the same film layer, the distance between the gate of the driving transistor M1 and the emission control signal line Emit is closer in the second direction Y, which is not favorable for the arrangement of the extension portion Y1 of the emission control signal line Emit. Therefore, the inventors of the present application consider that the recess a1 is provided on the side of the gate of the driving transistor M1 close to the emission control signal line Emit, so that the extension Y1 of at least part of the emission control signal line Emit is located in the recess a1, thereby increasing the overlapping area of the extension Y1 of the emission control signal line Emit and the first plate of the storage capacitor Cst, and facilitating the implementation of the laser process.

Specifically, the gate of the driving transistor M1 and the extension Y1 of the emission control signal line Emit may be in the same film layer, for example, both in the first metal layer M1. A recess a1 is provided on a side of the gate of the driving transistor M1 close to the emission control signal line Emit, and an extension Y1 of at least a part of the emission control signal line Emit is located in the recess a 1. Therefore, the length and/or the width of the extension part Y1 of the emission control signal line Emit can be set to be larger, so that the overlapping area of the extension part Y1 of the emission control signal line Emit and the first plate of the storage capacitor Cst is increased, and the extension part Y1 of the emission control signal line Emit and the first plate of the storage capacitor Cst are conveniently connected in a laser mode through a laser process during subsequent repair.

According to still further embodiments of the present application, optionally, at least two of the first power supply signal line PVDD, the emission control signal line Emit, and the first plate of the storage capacitor Cst may include the body portion B1 and the extension portion Y1, and the extension portions Y1 of the at least two at least partially overlap in a direction perpendicular to a plane in which the display panel is located.

Hereinafter, the first plates of the emission control signal line Emit and the storage capacitor Cst include the body portion B1 and the extension portion Y1.

As shown in fig. 10 and 11, the first plates of the emission control signal line Emit and the storage capacitor Cst may each include a body portion B1 and an extension portion Y1. For the sake of convenience of distinction, the main body portion B1 of the emission control signal line Emit is denoted by Emit (B1), and the extension portion Y1 of the emission control signal line Emit is denoted by Emit (Y1). The body portion B1 of the first plate of the storage capacitor Cst is denoted by Cst (B1), and the extension portion Y1 of the first plate of the storage capacitor Cst is denoted by Cst (Y1). The extension portion exit (Y1) of the emission control signal line exit may at least partially overlap the extension portion Cst (Y1) of the first plate of the storage capacitor Cst in a direction perpendicular to a plane in which the display panel is positioned. Illustratively, for example, the body portion Emit (B1) and the extension portion Emit (Y1) of the emission control signal line Emit are located at the first metal layer M1, and the body portion Cst (B1) and the extension portion Cst (Y1) of the first plate of the storage capacitor Cst are located at the second metal layer MC. The extension portion exit (Y1) of the emission control signal line exit and the extension portion Cst (Y1) of the first plate of the storage capacitor Cst may both extend in the second direction Y or any other direction. An extension portion Emit (Y1) of the emission control signal line Emit may be located between the gate of the first emission control transistor M6 of the pixel circuit 200 and the gate of the second emission control transistor M7 of the pixel circuit 200. The extension portion exit (Y1) of the emission control signal line exit may at least partially overlap the extension portion Cst (Y1) of the first plate of the storage capacitor Cst in a direction perpendicular to a plane in which the display panel is positioned.

In this way, when a failure occurs in a certain pixel circuit 200 and the light emitting element connected to the pixel circuit 200 is normally on, the extension portion init (Y1) of the emission control signal line init between the gate of the first emission control transistor M6 and the gate of the second emission control transistor M7 of the pixel circuit 200 may be electrically connected to the extension portion Cst (Y1) of the first plate of the storage capacitor Cst of the pixel circuit 200 by a laser process. Thus, the gate of the first emission control transistor M6 and the second emission control transistor M7 can be electrically connected to the first power supply signal line PVDD in this order via the main portion Emit (B1) and the extension portion Emit (Y1) of the emission control signal line Emit between the gate of the transistor M6 and the gate of the transistor M7, the extension portion Cst (Y1) of the first plate of the storage capacitor Cst, and the main portion Cst (B1) of the first plate of the storage capacitor Cst.

With continued reference to fig. 3, the inventors of the present application have found that, in the case of single-side driving, if the target pixel circuit 200A is located exactly in the middle of a row of pixel circuits 200, when the emission control signal line Emit between the gate of at least one emission control transistor MT in the target pixel circuit 200A and the adjacent pixel circuit 200 is disconnected, the emission control signal may not be received by other pixel circuits 200 on one side (e.g., the right side) of the target pixel circuit 200A, and a display problem may occur.

In view of the above-mentioned findings, the inventors of the present application consider that the dual-edge driving method is adopted, so that when the emission control signal line Emit between the gate of at least one emission control transistor MT in the target pixel circuit 200A and the adjacent pixel circuit 200 is disconnected, it is ensured that the emission control signals can be received by the other pixel circuits 200 on both sides (for example, left and right sides) of the target pixel circuit 200A, and the display effect of the display panel is ensured.

Specifically, in some embodiments of the present application, at least one row or multiple rows of pixel circuits 200 in which the target pixel circuit 200A is located are driven bilaterally. As shown in fig. 12, the display panel 20 may include N emission control signal lines Emit and a non-display area NA at both sides of the plurality of pixel circuits 200, and the non-display area NA may include a first sub non-display area NA1 and a second sub non-display area NA2 arranged in the first direction X, N being a positive integer. The first sub non-display area NA1 may be provided with a first gate driving circuit 1210, and the first gate driving circuit 1210 may include N first scan shift registers 1210a, and the N first scan shift registers 1210a are electrically connected to the N emission control signal lines Emit in a one-to-one correspondence. The second non-display sub region NA2 may be provided with a second gate driving circuit 1220, and the second gate driving circuit 1220 may include N second scanning shift registers 1220a, and the N second scanning shift registers 1220a are electrically connected to the N emission control signal lines Emit in a one-to-one correspondence.

It is easily understood that, in the case where the emission control signal line Emit between the gate of at least one emission control transistor MT in the target pixel circuit 200A and the adjacent pixel circuit 200 is disconnected, the other pixel circuits 200 on one side (e.g., left side) of the target pixel circuit 200A may receive the emission control signal output from the first gate driving circuit 1210, and the other pixel circuits 200 on the other side (e.g., right side) of the target pixel circuit 200A may receive the emission control signal output from the second gate driving circuit 1220, thereby ensuring the display effect of the display panel.

In order to improve the display effect of the display panel, as shown in fig. 13, according to some embodiments of the present disclosure, optionally, the first power signal line PVDD and the first plate of the storage capacitor Cst of the pixel circuit 200 may form a mesh-shaped trace, so as to reduce a voltage drop of the first power signal line PVDD, ensure the display uniformity of the display panel, and improve the display effect of the display panel.

Specifically, the first power signal line PVDD and the first plate of the storage capacitor Cst may be located at different layers, and the first power signal line PVDD and the first plate of the storage capacitor Cst may be electrically connected through the first via h 2. For example, the first power signal line PVDD is disposed in the third metal layer M3, and the first plate of the storage capacitor Cst is disposed in the second metal layer MC. The display panel 20 may further include a first connection portion 1300 extending in the first direction X, and the first plates of the storage capacitors Cst of the at least two pixel circuits 200 arranged in the first direction X are connected by the first connection portion 1300.

In this way, in the second metal layer MC, the first plates of the storage capacitors Cst of the plurality of pixel circuits 200 arranged along the first direction X are connected by the first connection portion 1300 to form a "transverse trace"; in the third metal layer M3, the first power signal line PVDD extends along the second direction Y to form a "vertical trace", and the "horizontal trace" is electrically connected to the "vertical trace" through the first via hole h2, so as to form a mesh trace of the first power signal line PVDD, thereby reducing the voltage drop of the first power signal line PVDD, ensuring the display uniformity of the display panel, and improving the display effect of the display panel.

In order to facilitate understanding of the display panel provided in the embodiments of the present application, the following description is made in detail with reference to specific application examples as shown in fig. 2 and 14.

As shown in fig. 2 and 14, the display panel 20 may include a scan signal line, a light emission control signal line Emit, a reference voltage signal line Vref, a first power signal line PVDD, and a data signal line Vdata. The scan signal lines may include a first scan signal line S1 and a second scan signal line S2, and each pixel circuit 200 may have at least a first scan signal line S1 and a second scan signal line S2 connected thereto, respectively. The reference voltage signal line Vref is used to transmit a reset voltage signal, which can be used to reset the gate potential of the driving transistor M1 or the anode potential of the light emitting element. The reference voltage signal line Vref is used to provide a negative voltage signal, e.g., -3.5V.

For example, the first scan signal line S1, the second scan signal line S2, and the emission control signal line Emit may be disposed in the first metal layer M1, the reference voltage signal line Vref may be disposed in the second metal layer MC, and the first power signal line PVDD and the data signal line Vdata may be disposed in the third metal layer M2. The first scan signal line S1, the second scan signal line S2, the emission control signal line Emit, and the reference voltage signal line Vref may extend in the first direction X, and the first power signal line PVDD and the data signal line Vdata may extend in the second direction Y.

Taking the 7T1C pixel circuit as an example, the display panel 20 may include a driving transistor M1, a threshold compensation transistor M2, a data writing transistor M3, a first reset transistor M4, a second reset transistor M5, a first light emission control transistor M6, a second light emission control transistor M7, and a storage capacitor Cst. In order to maintain the stability of the potential of the first node N1, the threshold compensation transistor M2 and/or the first reset transistor M4 may be dual-gate transistors, so as to reduce the leakage current of the threshold compensation transistor M2 and/or the first reset transistor M4, maintain the stability of the potential of the first node N1, and further ensure the stability of the display. It is easily understood that the channel region, the source region and the drain region of each of the above transistors may be located at the active layer b, the gate electrode may be located at the first metal layer M1, and the source metal and the drain metal may be located at the third metal layer M2. The first plate of the storage capacitor Cst may be located on the second metal layer MC, and the second plate of the storage capacitor Cst may be located on the first metal layer M1. Illustratively, the second plate of the storage capacitor Cst may multiplex the gate of the driving transistor M1.

The gate of the driving transistor M1 is electrically connected to the first node N1, and the first pole of the driving transistor M1 is electrically connected to the second node N2.

The threshold compensation transistor M2 is a double-gate transistor, a double gate of the threshold compensation transistor M2 is electrically connected to the second scan signal line S2, a first gate of the threshold compensation transistor M2 is electrically connected to the first node N1, and a second gate of the threshold compensation transistor M2 is electrically connected to the second gate of the driving transistor M1. The threshold compensation transistor M2 is used to compensate for the threshold voltage Vth of the driving transistor M1.

The gate of the data writing transistor M3 is electrically connected to the second scanning signal line S2, the first pole of the data writing transistor M3 is electrically connected to the data signal line Vdata, and the second pole of the data writing transistor M3 is electrically connected to the second pole of the driving transistor M1. The data writing transistor M3 is used to write the data signal transmitted by the data signal line Vdata into the second pole of the driving transistor M1.

The first reset transistor M4 is a double-gate transistor, a double gate of the first reset transistor M4 is electrically connected to the first scan signal line S1, a first gate of the first reset transistor M4 is electrically connected to the reference voltage signal line Vref, and a second gate of the first reset transistor M4 is electrically connected to the first node N1. The first reset transistor M4 is used to write a reference voltage signal transmitted from the reference voltage signal line Vref to the first node N1 to reset the first node N1.

The gate of the second reset transistor M5 is electrically connected to the first scanning signal line S1, the first pole of the second reset transistor M5 is electrically connected to the reference voltage signal line Vref, and the second pole of the second reset transistor M5 is electrically connected to the anode of the light emitting element. The second reset transistor M5 is used to write a reference voltage signal transmitted from the reference voltage signal line Vref to the anode of the light emitting element to reset the anode of the light emitting element.

The gate of the first light emission controlling transistor M6 may be electrically connected to the light emission control signal line Emit, the first pole of the first light emission controlling transistor M6 may be electrically connected to the first power signal line PVDD, and the second pole of the first light emission controlling transistor M6 may be electrically connected to the first pole of the driving transistor M1 (i.e., the second node N2).

The gate of the second light emission controlling transistor M7 may be electrically connected to the light emission control signal line Emit, the first pole of the second light emission controlling transistor M7 is electrically connected to the second pole of the driving transistor M1, and the second pole of the second light emission controlling transistor M7 is electrically connected to the anode of the light emitting element.

A first plate of the storage capacitor Cst may be electrically connected to the first power signal line PVDD, and a second plate of the storage capacitor Cst may be electrically connected to the first node N1.

The inventors of the present application have found that, since the data signal line Vdata is responsible for providing a column of pixel circuits with data signals, the data signals transmitted by the data signal line Vdata are constantly changing. In the case where the data signal line Vdata is close to the first node N1, it is inevitable that the potential of the first node N1 is unstable due to the influence of parasitic capacitance or coupling capacitance. For example, the via hole h4 connected to the data signal line Vdata and the via hole h5 at the first node N1 form a coupling capacitor, and the via hole h6 connected to the data signal line Vdata and the via hole h5 at the first node N1 form a coupling capacitor. Thus, when the data signal transmitted by the data signal line Vdata changes, the potential of the first node N1 is pulled high or low by the coupling effect of the capacitor.

In order to maintain the stability of the potential of the first node N1, as shown in fig. 14, the display panel 20 further includes a first partition 1401 and a second partition 1402. The first partition 1401 may be located between the first node N1 and the data signal line Vdata in a direction parallel to the plane of the display panel. Also, the first isolation portion 1401 may at least partially overlap the first power supply signal line PVDD in a direction perpendicular to a plane in which the display panel is located. The second spacer 1402 at least partially overlaps the active layer between the dual gates of the threshold compensation transistor M2 in a direction perpendicular to the plane of the display panel. The first isolation 1401 may be electrically connected to the second isolation 1402, and the first isolation 1401, the second isolation 1402 and the first plate of the storage capacitor Cst are disposed in the same layer. For example, the first isolation 1401, the second isolation 1402, and the first plate of the storage capacitor Cst are disposed on the second metal layer MC.

In this way, since the first isolation portion 1401 and the second isolation portion 1402 are electrically connected to the first power signal line PVDD, and maintain a stable high voltage, and the first isolation portion 1401 and the second isolation portion 1402 are located between the first node N1 and the data signal line Vdata, the influence of the data signal line Vdata on the voltage of the first node N1 can be weakened or even shielded, the stability of the voltage of the first node N1 can be maintained, and the stability of the display can be further ensured.

It should be noted that the display panel 20 provided in the embodiment of the present application includes, but is not limited to, an OLED display panel. In some specific application examples, the display panel 20 may be, for example, an OLED display panel with a larger size, so as to achieve bright spot repair of the OLED display panel with the larger size.

Based on the display panel 20 provided in the foregoing embodiment, correspondingly, the present application also provides a repairing method, which can be applied to the display panel 20 described above. As shown in fig. 15, the repairing method provided by the embodiment of the present application may include the following steps:

s1501, detecting a target pixel circuit where a bright point is located from a plurality of pixel circuits;

s1502, disconnecting a light emission control signal line between a gate of at least one light emission control transistor of a target pixel circuit and an adjacent pixel circuit; and/or the presence of a gas in the gas,

s1503, the gate of at least one light emission control transistor of the target pixel circuit is electrically connected to the first power signal line through the extension portion.

In S1502, the light emission control signal line between the gate of at least one light emission control transistor of the target pixel circuit and the adjacent pixel circuit may be laser-cut, for example. In S1503, the gate of at least one light emission control transistor of the target pixel circuit may be laser-connected to the first power supply signal line through the extension portion, for example, by laser.

The repair method according to the embodiment of the present application disconnects the gate of at least one emission control transistor of the target pixel circuit from the emission control signal line between the adjacent pixel circuits, and/or electrically connects the gate of at least one emission control transistor of the target pixel circuit to the first power signal line through the extension portion, for the target pixel circuit (i.e., the pixel circuit in the normally-on abnormal sub-pixel) in the display panel 20. Therefore, at least one light-emitting control transistor of the target pixel circuit is in a cut-off state, so that the driving current in the target pixel circuit cannot reach the anode of the corresponding light-emitting element, the normally-on abnormal sub-pixel is made not to emit light any more, the repair of a bright point is realized, and the display effect of the display panel is improved.

The specific implementation of the steps in the method shown in fig. 15 has been described in the above description of the display panel 20, and will not be described herein again. It should be noted that the repairing method provided in the embodiment of the present application can achieve the technical effects corresponding to the display panel 20 provided in the foregoing embodiment, and for brevity, no further description is provided herein.

Based on the display panel 20 provided by the above embodiment, correspondingly, the present application further provides a display device, including the display panel provided by the present application. Referring to fig. 16, fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 16 provides a display device 1000 including the display panel 20 according to any of the above embodiments of the present application. The display device 20 in the embodiment of fig. 16 is described by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as wearable products, computers, televisions, and vehicle-mounted display devices, and the present application is not limited thereto. The display device provided in the embodiments of the present application has the advantages of the array substrate provided in the embodiments of the present application, and specific descriptions of the array substrate in the embodiments above may be specifically referred to, and the details of the embodiments are not repeated herein.

It should be understood that the specific structures of the pixel circuit and the layout structure of the display panel provided in the drawings of the embodiments of the present application are only some examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel comprising a plurality of pixel circuits, a light emission control signal line extending in a first direction, and a first power supply signal line extending in a second direction, the pixel circuits including storage capacitances, first plates of the storage capacitances being electrically connected to the first power supply signal line, the first direction and the second direction crossing;

at least one of the first power signal line, the light emission control signal line and the first electrode plate comprises a body part and an extension part which are electrically connected, and in at least partial area where the orthographic projection of the extension part on the light-emitting surface of the display panel is located, in the direction perpendicular to the plane of the display panel, the light emission control signal line and at least one of the first power signal line and the first electrode plate are at least partially overlapped;

the pixel circuit further comprises at least one light-emitting control transistor for controlling the light-emitting element to emit light, the light-emitting control signal line is electrically connected with the gates of the light-emitting control transistors of the M pixel circuits which are sequentially arranged along the first direction, and M is a positive integer; at least one of the pixel circuits is a target pixel circuit, a gate of at least one of the light emission control transistors of the target pixel circuit is disconnected from the light emission control signal line between the adjacent pixel circuits, and/or the gate of at least one of the light emission control transistors of the target pixel circuit is electrically connected to the first power supply signal line through the extension portion.

2. The display panel according to claim 1, wherein the pixel circuit further comprises a driving transistor, wherein the light emission control transistor of the pixel circuit comprises a first light emission control transistor, a gate of the first light emission control transistor is electrically connected to the light emission control signal line, a first pole of the first light emission control transistor is electrically connected to the first power signal line, and a second pole of the first light emission control transistor is electrically connected to the first pole of the driving transistor.

3. The display panel according to claim 1, wherein the pixel circuit further comprises a driving transistor, wherein the light emission control transistor of the pixel circuit comprises a second light emission control transistor, a gate of the second light emission control transistor is electrically connected to the light emission control signal line, a first electrode of the second light emission control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the second light emission control transistor is electrically connected to a first electrode of a light emitting element.

4. The display panel according to claim 1, wherein the pixel circuit further comprises a driving transistor, and the light emission control transistor of the pixel circuit comprises a first light emission control transistor and a second light emission control transistor, wherein:

a gate of the first light emission control transistor is electrically connected to the light emission control signal line, a first pole of the first light emission control transistor is electrically connected to the first power signal line, and a second pole of the first light emission control transistor is electrically connected to the first pole of the driving transistor;

the gate of the second emission control transistor is electrically connected to the emission control signal line, the first electrode of the second emission control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second emission control transistor is electrically connected to the first electrode of the light emitting element.

5. The display panel according to claim 4, wherein the first plate of the storage capacitor of the pixel circuit includes the body portion and the extension portion, the body portion is electrically connected to the first power supply signal line, and in a direction perpendicular to a plane of the display panel, the extension portion of the first plate and the light emission control signal line between the gate of the first light emission control transistor of the pixel circuit and the gate of the second light emission control transistor of the pixel circuit at least partially overlap.

6. The display panel according to claim 4, wherein the first power supply signal line includes the body portion and the extension portion, wherein the body portion of the first power supply signal line extends in the second direction, wherein the extension portion of the first power supply signal line extends in the first direction, and wherein the extension portion of the first power supply signal line and the light emission control signal line between the gate of the first light emission control transistor of the pixel circuit and the gate of the second light emission control transistor of the pixel circuit at least partially overlap in a direction perpendicular to a plane in which the display panel is located.

7. The display panel according to claim 4, wherein the light emission control signal line includes the body portion and the extension portion, the extension portion of the light emission control signal line is located between a gate of a first light emission control transistor of the pixel circuit and a gate of a second light emission control transistor of the pixel circuit, and the extension portion of the light emission control signal line at least partially overlaps with a first plate of a storage capacitor of the pixel circuit in a direction perpendicular to a plane of the display panel.

8. The display panel according to claim 7, wherein the gate of the driving transistor is in the same layer as the light emission control signal line, a side of the gate of the driving transistor close to the light emission control signal line has a recess, and at least a portion of the extension of the light emission control signal line is located in the recess.

9. The display panel according to any one of claims 1 to 8, wherein at least one row or a plurality of rows of pixel circuits in which the target pixel circuit is located are driven bilaterally.

10. The display panel according to claim 1,

the first power signal wire and the first polar plate are positioned on different film layers and are electrically connected through a first through hole;

the display panel further includes a first connection portion extending in the first direction, and the first electrode plates of the storage capacitors of at least two of the pixel circuits arranged in the first direction are connected by the first connection portion.

11. The display panel according to claim 1,

the display panel includes a driving transistor, a threshold compensation transistor, a first isolation portion, a second isolation portion, a scan signal line extending in the first direction, and a data signal line extending in the second direction, wherein:

the grid electrode of the driving transistor is electrically connected with a first node, and the first pole of the driving transistor is electrically connected with a second node;

the threshold compensation transistor is a double-gate transistor, a double gate of the threshold compensation transistor is electrically connected with the scanning signal line, a first electrode of the threshold compensation transistor is electrically connected with the first node, and a second electrode of the threshold compensation transistor is electrically connected with a second electrode of the driving transistor;

the first isolation portion is located between the first node and the data signal line, and at least partially overlaps the first power signal line in a direction perpendicular to a plane of the display panel;

in a direction perpendicular to the plane of the display panel, the second isolation part at least partially overlaps with an active layer between the double gates of the threshold compensation transistor;

the first isolation part is electrically connected with the second isolation part, and the first isolation part, the second isolation part and the first electrode plate of the storage capacitor are arranged on the same layer.

12. The display panel according to claim 1, wherein a gate of the light emission control transistor and the light emission control signal line are provided in a first metal layer, a first plate of the storage capacitor is provided in a second metal layer, and a source and a drain of the light emission control transistor and the first power signal line are provided in a third metal layer.

13. A repair method applied to the display panel according to any one of claims 1 to 12, the repair method comprising:

detecting a target pixel circuit in which a lighting point is located from among the plurality of pixel circuits;

disconnecting the light emission control signal line between the gate of at least one of the light emission control transistors of the target pixel circuit and the adjacent pixel circuit; and/or the presence of a gas in the gas,

a gate of at least one of the light emission control transistors of the target pixel circuit is electrically connected to the first power supply signal line through the extension portion.

14. A display device characterized by comprising the display panel according to any one of claims 1 to 12.