CN114328358A - Method for accessing random-capacity memory by 7-bit addressing mode I2C controller - Google Patents
Method for accessing random-capacity memory by 7-bit addressing mode I2C controller Download PDFInfo
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Abstract
A method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller belongs to the technical field of communication and comprises a memory reading operation and a memory writing operation. The invention can realize the access of the memory with any capacity by only using a 7-bit addressing mode. The I2C controller can be transplanted at will according to the use requirement, does not need to change the hardware circuit, and the flexibility is strong.
Description
Technical Field
The invention discloses a method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller, and relates to the technical field of communication.
Background
The I2C communication protocol (Inter-Integrated Circuit) is developed by Philips corporation, and is now widely used for communication among a plurality of Integrated Circuits (ICs) in a system because of its few pins, simple hardware implementation, high expandability, and no need of external transceiver devices for communication protocols such as UART and CAN. I2C is a two-wire bus including SDA (SerialData-serial data line) and SCL (SerialClock-serial clock line) through which system components can communicate with each other.
The I2C bus is divided into a 7-bit address mode and a 10-bit address mode from the addressing realm. In the process of I2C data transmission, the size of a data frame is fixed to be 8-bit bytes, and the high order bits are sent first. The I2C protocol defines the links of start and stop signaling, data validity, response, arbitration, clock synchronization, and address broadcast for communication.
The common basic read-write process of I2C is as follows:
the writing data includes:
if the configured direction transmission bit is the "write DATA" direction, as shown in fig. 1, after the address is broadcasted, the master starts to formally transmit DATA (DATA) to the slave after receiving the response signal, the size of the DATA packet is 8 bits, the master waits for the response signal (ACK) of the slave every time the master sends one byte of DATA, and the process is repeated, so that N DATA can be transmitted to the slave, where N has no size limitation. When the data transmission is finished, the master sends a transmission stop signal (P) to the slave, which indicates that the data is not transmitted any more.
The data reading is as follows:
if the configured directional transmission bit is in the "read DATA" direction, as shown in fig. 2, after the address is broadcasted, the slave starts to return DATA (DATA) to the host after receiving the response signal, the size of the DATA packet is also 8 bits, and the slave waits for the response signal (ACK) of the host every time the slave sends one DATA, and repeats the process, so that N DATA can be returned, and N has no size limitation. When the master wishes to stop receiving data, a non-acknowledgement signal (NACK) is returned to the slave, and the slave automatically stops data transmission.
Currently, the I2C bus, which employs a 7-bit addressing mode, provides 7-bit address lines for auxiliary devices, which can only access 128 bytes of physical space at most. The I2C bus, which employs a 10-bit addressing mode, provides the auxiliary device with 10-bit address lines, which can only access 1 kbyte of physical space at most. With the increase of the I2C bus application scenarios and the difference of the space size of the memory under different applications, the I2C controller has been unable to meet the requirement. For this reason, for example, patent document CN100416536C discloses "method for accessing mass storage by 10-bit addressing mode I2C controller", which solves the problem that the 10-bit addressing mode accesses physical space over 1 kbyte, but its address is extended to 15bit at most, that is, the access limit is 32 kbyte physical space, and the first 3 bytes of the instruction format are fixed as physical address, which increases the design length of the instruction.
Disclosure of Invention
In order to solve the technical problem that a storage space device with any capacity cannot be addressed due to limitation of an addressing space, the invention discloses a method for accessing a storage with any capacity by a 7-bit addressing mode I2C controller.
The invention is convenient to be transplanted to different application scenes, not only saves the cost, but also enhances the use flexibility.
The detailed technical scheme of the invention is as follows:
a method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller is characterized by comprising the following steps of:
(1-1) the I2C controller sending a start signal to a memory, the memory being a slave;
(1-2) the I2C controller sends a write operation command to the memory and waits for an acknowledgement signal ACK from the slave;
(1-3) after receiving the acknowledgement signal ACK of the slave, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(1-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (1-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (1-3);
if the first bit of the address byte sent in the step (1-3) is 0, the address is sent completely, and the step (1-5) is switched to; specific arbitrary memory capacity variable addresses are shown in fig. 3;
(1-5) waiting for an acknowledgement signal ACK from the slave;
(1-6) after the I2C controller receives the ACK, the I2C controller sends a start signal to the memory;
(1-7) the I2C controller sends a memory address to be read to the target memory, then sends a read operation command again, and waits for a response signal ACK of the slave;
(1-8) after the I2C controller receives the acknowledge signal ACK, the I2C controller reads n bytes of data from the memory, and waits for acknowledge signal ACK from the slave after each byte is read;
(1-9) upon receiving the slave's acknowledge signal ACK for the last byte, the I2C controller sends a stop (stop) command.
Preferably, in the step (1-2), the write operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and an 8 th bit of 0 indicates that the operation is a write operation.
Preferably, in the step (1-7), the read operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and an 8bit of 1 indicates that the operation is a read operation.
A method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller is characterized by comprising the following steps of:
(2-1) the I2C controller sending a start signal to the memory, the memory being a slave;
(2-2) the I2C controller sending a write operation command to the memory and waiting for an acknowledgement signal ACK from the slave;
(2-3) after receiving the acknowledgement signal ACK, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(2-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (2-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (2-3);
if the first bit of the address byte sent in the step (2-3) is 0, the address is sent completely, and the step (2-5) is switched to; specific arbitrary memory capacity variable addresses are shown in fig. 3;
(2-5) waiting for an acknowledgement signal ACK from the slave;
(2-6) after the I2C controller receives the ACK, the I2C controller sends n bytes of write data into the memory, and after each byte is written, the slave waits for an acknowledgement signal ACK to be sent back;
(2-7) upon receiving the slave's ACK for the last byte, the I2C controller sends a stop (stop) command.
Preferably, in the step (2-2), the write operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and an 8 th bit of 0 indicates that the operation is a write operation.
The invention has the beneficial technical effects that:
the invention can realize the access of the memory with any capacity by only using a 7-bit addressing mode. The I2C controller can be transplanted at will according to the use requirement, does not need to change the hardware circuit, and the flexibility is strong.
Drawings
FIG. 1 is a schematic diagram of a basic write flow of a conventional I2C controller;
FIG. 2 is a schematic diagram of a basic read flow of a conventional I2C controller;
FIG. 3 is a schematic table of the address composition format of the 7-bit addressing mode memory of the present invention;
FIG. 4 is a flow chart of the read memory of the controller with 7-bit addressing mode I2C according to the present invention;
FIG. 5 is a flow chart of the controller writing the memory in the 7-bit addressing mode I2C of the invention.
Detailed Description
In order to facilitate a better understanding of the invention for those skilled in the art, the invention will be described in further detail with reference to the accompanying drawings and specific examples, which are given by way of illustration only and do not limit the scope of the invention.
As shown in fig. 3, 4, 5.
Examples 1,
A method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller comprises the following steps:
(1-1) the I2C controller sending a start signal to a memory, the memory being a slave;
(1-2) the I2C controller sends a write operation command to the memory and waits for an acknowledgement signal ACK from the slave;
(1-3) after receiving the acknowledgement signal ACK of the slave, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(1-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (1-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (1-3);
if the first bit of the address byte sent in the step (1-3) is 0, the address is sent completely, and the step (1-5) is switched to; specific arbitrary memory capacity variable addresses are shown in fig. 3;
(1-5) waiting for an acknowledgement signal ACK from the slave;
(1-6) after the I2C controller receives the ACK, the I2C controller sends a start signal to the memory;
(1-7) the I2C controller sends a memory address to be read to the target memory, then sends a read operation command again, and waits for a response signal ACK of the slave;
(1-8) after the I2C controller receives the acknowledge signal ACK, the I2C controller reads n bytes of data from the memory, and waits for acknowledge signal ACK from the slave after each byte is read;
(1-9) upon receiving the slave's acknowledge signal ACK for the last byte, the I2C controller sends a stop (stop) command.
In the step (1-2), the write operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and the 8 th bit is 0, which indicates that the operation is a write operation.
In the step (1-7), the read operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and the 8 th bit is 1, which indicates that the operation is a read operation.
Examples 2,
A method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller is characterized by comprising the following steps of:
(2-1) the II2C controller sending a start signal to the memory, the memory being a slave;
(2-2) the I2C controller sending a write operation command to the memory and waiting for an acknowledgement signal ACK from the slave;
(2-3) after receiving the acknowledgement signal ACK, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(2-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (2-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (2-3);
if the first bit of the address byte sent in the step (2-3) is 0, the address is sent completely, and the step (2-5) is switched to; specific arbitrary memory capacity variable addresses are shown in fig. 3;
(2-5) waiting for an acknowledgement signal ACK from the slave;
(2-6) after the I2C controller receives the ACK, the I2C controller sends n bytes of write data into the memory, and after each byte is written, the slave waits for an acknowledgement signal ACK to be sent back;
(2-7) upon receiving the slave's ACK for the last byte, the I2C controller sends a stop (stop) command.
In the step (2-2), the write operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and the 8 th bit is 0, which indicates that the operation is a write operation.
Application examples 1,
Now, in connection with embodiment 1, an access to a memory having a capacity of 128 bytes or less is performed.
The basic read operation flow comprises the following steps:
the I2C controller sends a starting signal;
the I2C controller sends a write operation command of one byte;
c. after receiving the ACK, the I2C controller sends a byte of address of the memory to be read;
d. after receiving the ACK, the I2C controller sends a start signal;
the I2C controller sends a read operation command;
f. after receiving the ACK, the I2C controller reads n bytes from the memory, and there should be an ACK after each byte is read;
g. after receiving the ACK of the last byte, the I2C controller sends a stop bit;
further, in the step b, the equipment number of the memory corresponding to 1-7 bits is written, and the 8 th bit is 0 to indicate that the writing operation is performed
Further, in step c, with reference to fig. 3, the 1 st bit should be 0, and the addresses of the memories correspond to 2-8 bits, and the access range is 0000000b-1111111 b;
further, in step e, writing 1-7 bits of the device number of the corresponding memory, wherein the 8 th bit is 1, which means that the writing operation is performed
Further, n in step f represents the length of the memory byte to be read by the I2C controller, which is 1 at minimum and 128 at maximum.
Application examples 2,
Now, in connection with embodiment 2, an access to a memory having a capacity of 128 bytes or less is performed.
The basic writing operation flow comprises the following steps:
the I2C controller sends a starting signal;
the I2C controller sends a write operation command of one byte;
c. after receiving the ACK, the I2C controller sends the address of the memory to be written of one byte;
d. after receiving the ACK, the I2C controller sends n bytes of data to the memory, and there should be an ACK after each byte is sent;
e. after receiving the ACK of the last byte, the I2C controller sends a stop bit;
further, in the step b, the equipment number of the memory corresponding to 1-7 bits is written, and the 8 th bit is 1, which indicates that the writing operation is performed
Further, in step c, with reference to fig. 3, the 1 st bit should be 0, and the addresses of the memories correspond to 2-8 bits, and the access range is 0000000b-1111111 b;
further, n in step f represents the length of memory bytes to be written by the I2C controller, which is 1 at minimum and 128 at maximum.
Application examples 3,
Now, in connection with embodiment 1, accesses to memory with a capacity greater than 128 bytes and less than 16 kbytes are made.
The basic read operation flow comprises the following steps:
the I2C controller sends a starting signal;
the I2C controller sends a write operation command of one byte;
c. after receiving the ACK, the I2C controller sends a byte of address of the memory to be read;
d. after receiving the ACK, the I2C controller sends the address of the memory to be read by one byte;
e. after receiving the ACK, the I2C controller sends a start signal;
the I2C controller sends a read operation command;
g. after receiving the ACK, the I2C controller reads n bytes from the memory, and there should be an ACK after each byte is read;
h. after receiving the ACK of the last byte, the I2C controller sends a stop bit;
further, writing the device number of the memory corresponding to 1-7 bits in the step b, wherein the 8 th bit is 0, which indicates that the writing operation is performed;
further, in step c, with reference to fig. 3, the 1 st bit should be 7 bits higher than the address of the memory corresponding to 1,2-8 bits;
further, in step d, with reference to fig. 3, the 1 st bit should be 0, and the address of the memory corresponding to 2-8 bits is 7 bits lower;
further, in connection with steps c, d, the memory address space can be accessed from 14 'h 00 to 14' h3 ff;
further, writing 1-7 bits in the step f corresponding to the device number of the memory, wherein the 8 th bit is 1, which means that the writing operation is performed
Further, n in step g represents the length of the memory byte to be read by the I2C controller, and is 1 at minimum.
Application examples 4,
Now, in connection with embodiment 2, accesses to memory with a capacity of more than 128 bytes and less than 16 kbytes are made.
The basic writing operation flow comprises the following steps:
the I2C controller sends a starting signal;
the I2C controller sends a write operation command of one byte;
c. after receiving the ACK, the I2C controller sends the address of the memory to be written of one byte;
d. after receiving the ACK, the I2C controller sends the address of the memory to be written of one byte;
e. after receiving the ACK, the I2C controller sends n bytes of data to the memory, and there should be an ACK after each byte is sent;
f. after receiving the ACK of the last byte, the I2C controller sends a stop bit;
further, in the step b, the equipment number of the memory corresponding to 1-7 bits is written, and the 8 th bit is 1, which indicates that the writing operation is performed
Further, in step c, with reference to fig. 3, the 1 st bit should be 7 higher bits than the address of the memory corresponding to 1,2-8 bits;
further, in step d, with reference to fig. 3, the 1 st bit should be 0, the 2-8 bits correspond to the lower 7 bits of the address of the memory, and the address space of the accessible memory is 14 'h 00-14' h3 ff;
further, n in step e represents the length of memory bytes to be written by the I2C controller, and is minimum 1.
Application examples 5,
Access to memory with a capacity greater than 16 kbytes. Similarly, when the access memory range exceeds 14 'h 3fff and is less than 21' h1fffff, in conjunction with FIG. 3, the I2C controller needs to use 3 bytes to represent the address of the memory; by analogy, the memory capacity falls in different ranges, and the I2C controller needs to use bytes of different lengths for representation.
The foregoing merely illustrates the principles and preferred embodiments of the invention and many variations and modifications may be made by those skilled in the art in light of the foregoing description, which are within the scope of the invention.
Claims (5)
1. A method for accessing a memory with any capacity by a 7-bit addressing mode I2C controller is characterized by comprising the following steps of:
(1-1) the I2C controller sending a start signal to the memory;
(1-2) the I2C controller sends a write operation command to the memory and waits for an acknowledgement signal ACK from the slave;
(1-3) after receiving the acknowledgement signal ACK of the slave, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(1-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (1-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (1-3);
if the first bit of the address byte sent in the step (1-3) is 0, the address is sent completely, and the step (1-5) is switched to;
(1-5) waiting for an acknowledgement signal ACK from the slave;
(1-6) after the I2C controller receives the ACK, the I2C controller sends a start signal to the memory;
(1-7) the I2C controller sends a memory address to be read to the target memory, then sends a read operation command again, and waits for a response signal ACK of the slave;
(1-8) after the I2C controller receives the acknowledge signal ACK, the I2C controller reads n bytes of data from the memory, and waits for acknowledge signal ACK from the slave after each byte is read;
(1-9) upon receiving the slave's acknowledge signal ACK for the last byte, the I2C controller sends a stop command.
2. The method of claim 1, wherein the write command in step (1-2) is 1 byte, 1-7 bits correspond to the device number of the memory, and 8bit is 0, which means that the operation is a write operation.
3. The method of claim 1, wherein the read operation command in the step (1-7) is 1 byte, 1-7 bits correspond to the device number of the memory, and 8bit is 1, which means this operation is a read operation.
4. The method for accessing any capacity memory by 7-bit addressing mode I2C controller according to claim 1, comprising the following steps:
(2-1) the I2C controller sending a start signal to the memory;
(2-2) the I2C controller sending a write operation command to the memory and waiting for an acknowledgement signal ACK from the slave;
(2-3) after receiving the acknowledgement signal ACK, the I2C controller sends an address to the memory and waits for the acknowledgement signal ACK of the slave;
(2-4) after receiving the acknowledgement signal ACK of the slave,
if the first bit of the address byte sent in the step (2-3) is 1, representing that the memory address is not sent completely, and continuing to carry out the step (2-3);
if the first bit of the address byte sent in the step (2-3) is 0, the address is sent completely, and the step (2-5) is switched to;
(2-5) waiting for an acknowledgement signal ACK from the slave;
(2-6) after the I2C controller receives the ACK, the I2C controller sends n bytes of write data into the memory, and after each byte is written, the slave waits for an acknowledgement signal ACK to be sent back;
(2-7) upon receiving the slave's ACK for the last byte, the I2C controller sends a stop command.
5. The method of claim 4, wherein in the step (2-2), the write operation command is 1 byte, 1-7 bits correspond to the device number of the memory, and 8bit is 0, which indicates that the operation is a write operation.
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Application publication date: 20220412 |