CN114328298A - System and method for mapping addresses of on-chip memories for vector access - Google Patents
System and method for mapping addresses of on-chip memories for vector access Download PDFInfo
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Abstract
An on-chip memory address mapping system for vector access comprises a vector data access unit, a memory address mapping unit, a memory unit block and a configuration register, wherein the vector data access unit accesses vector data to the memory unit block through the memory address mapping unit; the memory address mapping unit is used for dividing the memory cell blocks according to the mapping configuration information of the configuration register and selecting a memory address mapping mode to map memory addresses; the configuration register sends the generated mapping configuration information to the storage address mapping unit. The invention also provides an on-chip memory address mapping method for vector access, when the column addresses of each element of the multi-element vector are the same, the access of a plurality of elements is completed in one clock cycle, different address mappings can be performed on different address spaces according to the needs of a system, and the performance and the flexibility of the system are improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to an on-chip memory address mapping system and method for vector access.
Background
In the vector access process, multi-element concurrent access is a common way to improve the access efficiency. The conventional access adopts linear mapping addresses, so that when the row address of each element is the same, only one element can be accessed in one clock cycle, and the concurrent access operation cannot be completed in one clock cycle. Therefore, it is an urgent problem to improve the efficiency of multi-element concurrent access. The invention adopts an efficient staggered address mapping mode, can ensure that multi-element vector access operation is completed in one clock cycle, and greatly shortens the vector access time.
In the process of vector or matrix operation, a large number of multi-element vector accesses are needed, and how to improve the efficiency of multi-element vector access becomes a problem to be solved urgently. With the development of AI technology in recent years, the amount of vector or matrix operations is increasing, so it is important to improve the efficiency of multi-element vector access. By means of the efficient staggered memory address mapping mode, the problem that multiple-element vector access needs to take multiple clock cycles in the traditional linear memory address mapping mode is solved, and the access efficiency of the element vectors is greatly improved.
It is now common to use linear memory address mapping to increase the access speed by increasing the access clock frequency. Under the traditional linear memory address mapping mode, when the multi-element vector accesses the same column address data, only one element can be accessed in one clock cycle, the performance of the whole system is greatly influenced, and a plurality of clock cycles are required. The problem of multiple clock cycles for accessing the same column address data by multiple element vectors has an increasingly severe impact on the efficiency of vector or matrix operations. Even if the access clock is raised, higher efficiency cannot be achieved.
Disclosure of Invention
In order to solve the drawbacks of the prior art, an object of the present invention is to provide an on-chip memory address mapping system and method for vector access, which solve the problem of consuming multiple clock cycles when multiple element vectors access the same column address data in a programmable interleaving memory address mapping manner, and improve the access efficiency of the element vectors.
In order to achieve the above objects, the present invention provides an on-chip memory address mapping system for vector access, comprising a vector data access unit, a memory address mapping unit, a block of memory cells, and a configuration register, wherein,
the vector data access unit accesses vector data to the memory cell block through the storage address mapping unit;
the memory address mapping unit is used for dividing the memory cell blocks according to the mapping configuration information of the configuration register and selecting a memory address mapping mode to map memory addresses;
the configuration register sends the generated mapping configuration information to the storage address mapping unit.
Further, the memory address mapping unit receives signals of an upper memory mapping address limit, a lower memory mapping address limit and the number of memory unit blocks from the configuration register, divides a memory address space from a memory, and divides the memory address space into a plurality of memory unit blocks; and receiving a mapping mode selection signal from the configuration register, and selecting a corresponding memory address mapping mode to map the memory address.
Further, the mapping configuration information includes an upper memory mapping address limit, a lower memory mapping address limit, a number of memory cell blocks, and a mapping mode selection signal.
Further, the memory address mapping method includes a linear mapping method and an interleaving memory address mapping method.
Furthermore, the memory address mapping unit selects a linear mapping mode to map the memory address when the received mapping mode selection signal is equal to 0; when the received mapping mode selection signal is equal to 1, the interleaving memory address mapping mode is selected to map the memory address.
In order to achieve the above object, the present invention also provides an on-chip memory address mapping method for vector access, comprising the steps of,
1) dividing a memory address space from a memory and dividing the memory address space into a plurality of memory unit blocks;
2) selecting a corresponding memory address mapping mode according to the mapping mode selection signal;
3) storing the write memory vector data to a corresponding memory cell block according to the selected memory address mapping mode;
4) and according to the selected memory address mapping mode, reading memory vector data from the corresponding memory unit block and forwarding the memory vector data to the vector data access unit.
Further, the step 1) includes that the memory address mapping unit receives the memory mapping address upper limit, the memory mapping address lower limit and the memory unit block number signal from the configuration register, divides a memory address space from the memory, and divides the memory address space into a plurality of memory unit blocks.
Further, the step 2) further includes that the memory address mapping unit receives a mapping mode selection signal from the configuration register, and selects a linear mapping manner or an interleaving memory address mapping manner to map the memory address.
To achieve the above object, the present invention also provides a system chip including the on-chip memory address mapping system for vector access described above.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the on-chip memory address mapping method for vector access described above.
Compared with the prior art, the on-chip memory address mapping system and the method for vector access provided by the invention have the following technical effects:
by adopting an interleaving memory address mapping mode, when the column addresses of all elements of the multi-element vector are the same, the access of the elements can be completed in one clock cycle;
different address mapping can be performed on different address spaces according to system requirements, application scenarios of traditional mapping and staggered address mapping are met, and system flexibility is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a block diagram of an on-chip memory address mapping system for vector access according to the present invention;
FIG. 2 is a relationship diagram of a linear address mapping according to the present invention;
FIG. 3 is a relational diagram of interleaved address mapping according to the invention;
FIG. 4 is a flowchart of an on-chip memory address mapping method for vector access according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1
Fig. 1 is a schematic diagram illustrating an on-chip memory address mapping system for vector access according to the present invention, and as shown in fig. 1, the on-chip memory address mapping system for vector access according to the present invention includes a vector data access unit 10, a memory address mapping unit 20, a memory cell block 30, and a configuration register 40, wherein,
a vector data access unit 10 that sends the element address, the write memory signal, and the write memory vector data to the memory address mapping unit 20; sending element addresses and memory reading signals to the storage address mapping unit 20, and receiving memory reading vector data returned by the storage address mapping unit 20.
A memory address mapping unit 20, which divides a memory address space from the memory according to the upper limit and the lower limit of the memory mapping address set by the configuration register 40; dividing the memory address space into a plurality of memory cell blocks according to the number of the memory cell blocks set by the configuration register 40; receiving the element address, the write memory signal and the write memory vector data sent by the vector data access unit 10, and storing the write memory vector data into the corresponding memory cell block according to the mapping mode selection signal configured by the configuration register 40; receiving the element address and the read memory signal sent by the vector data access unit 10, according to the mapping mode selection signal configured by the configuration register 40, fetching the read memory vector data from the corresponding memory cell block and forwarding the read memory vector data to the vector data access unit 10.
In the embodiment of the present invention, the memory address mapping unit 20 selects the memory address mapping mode according to the mapping mode selection signal, including: linear mapping and interleaved memory address mapping. When the mapping mode selection signal is equal to 0, the linear mapping mode is indicated, and when the mapping mode selection signal is equal to 1, the interleaving memory address mapping mode is indicated.
And a memory cell block 30 for reading data based on the memory address and the memory chip select signal transmitted from the memory address mapping unit 20.
The configuration register 40 sets an upper memory mapping address limit, a lower memory mapping address limit, the number of memory cell blocks, and a mapping mode selection signal, so that the storage address mapping unit 20 performs the partition of the memory address space, the partition of the memory cell blocks, and the selection of the memory address mapping mode. When the mapping mode selection signal is equal to 0, the memory address mapping unit 20 is controlled to select the linear mapping mode, and when the mapping mode selection signal is equal to 1, the memory address mapping unit 20 is controlled to select the interleaving memory address mapping mode.
For example, when there are both vector access and operation and processing application for displaying image data in a system, the memory in the chip is usually divided into two different regions according to the upper mapping address limit, the lower memory mapping address limit and the number of memory cell blocks, one region is used for vector access and operation, and the mapping mode selection signal corresponding to the block region should select 1, i.e. the interleaving mapping mode. While the mapping mode selection signal for the memory block applied for the processing of displaying image data should select 0, i.e. the linear mapping mode.
FIG. 2 is a relationship diagram of linear address mapping according to the present invention, as shown in FIG. 2, the memory chip select type is decoded by the memory address [4:0] for example, the number of memory unit blocks is equal to 32. The numbers 1-31 within the boxes in fig. 2 indicate the numbers of memory cell blocks, which correspond to the memory block chip select signals. For example, when the memory address [4:0] =5 and the memory address [ n:5] =5, the number of the memory cell block in the corresponding frame is 5, which means that the memory 5 chip select signal is valid. The memory address [ n:5] corresponds to the address of the block of memory cells in each block. FIG. 3 is a diagram of the mapping of interleaved addresses according to the present invention, as shown in FIG. 3, the memory chip select type is decoded from the memory addresses [4:0] for example, where the number of memory cell blocks is equal to 32. The numbers 1-31 within the boxes in fig. 3 indicate the numbers of memory cell blocks, which correspond to the memory block chip select signals. For example, when the memory addresses [4:0] =5 and the memory addresses [ n:5] =5, the number of the memory cell block in the corresponding frame is 10, which means that the memory 5 chip select signal is valid. The memory address [ n:5] corresponds to the address of the block of memory cells in each block.
Example 2
Fig. 4 is a flowchart of an on-chip memory address mapping method for vector access according to the present invention, and the on-chip memory address mapping method for vector access according to the present invention will be described in detail with reference to fig. 4.
First, in step 401, a memory address space is partitioned from a memory into a plurality of memory cell blocks.
In the embodiment of the present invention, the storage address mapping unit 20 receives the upper limit and the lower limit of the memory mapping address sent by the configuration register 40, divides a memory address space from the memory, and divides the memory address space into a plurality of memory unit blocks according to the number of the memory unit blocks configured by the configuration register 40.
In step 402, a corresponding memory address mapping manner is selected according to the mapping mode selection signal.
In the embodiment of the present invention, the storage address mapping unit 20 selects a linear mapping manner or an interleaved memory address mapping manner according to the mapping mode selection signal from the configuration register 40.
In the embodiment of the invention, when the mapping mode selection signal is equal to 0, the linear mapping mode is indicated, and when the mapping mode selection signal is equal to 1, the interleaving memory address mapping mode is indicated.
In step 403, the write memory vector data is stored in the corresponding memory cell block 30 according to the selected memory address mapping manner.
In the embodiment of the present invention, the storage address mapping unit 20 receives the write memory signal and the pixel address of the vector data access unit 10, and maps the write memory vector data from the vector data access unit 10 to the corresponding memory cell block 30 according to the selected memory address mapping manner.
In step 404, read memory vector data is fetched from the corresponding memory cell block 30 and forwarded to the vector data access unit according to the selected memory address mapping manner.
In the embodiment of the present invention, the storage address mapping unit 20 receives the read memory signal and the pixel address of the vector data access unit 10, reads the read memory vector data in the memory unit block 30 according to the selected memory address mapping manner, and forwards the read memory vector data to the vector data access unit 10.
Example 3
In an embodiment of the present invention, a system chip is further provided, where the system chip includes the on-chip memory address mapping system for vector access in the foregoing embodiment, and an interleaving memory address mapping manner is adopted, so that when column addresses of respective elements of a multi-element vector are the same, access of multiple elements is completed in one clock cycle.
Example 4
In an embodiment of the present invention, a computer readable storage medium is also provided, on which computer instructions are stored, which when executed perform the steps of the on-chip memory address mapping method for vector access in the above-described embodiments.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An on-chip memory address mapping system for vector access, comprising a vector data access unit, a memory address mapping unit, a block of memory cells, and a configuration register, wherein,
the vector data access unit accesses vector data to the memory cell block through the storage address mapping unit;
the memory address mapping unit is used for dividing the memory cell blocks according to the mapping configuration information of the configuration register and selecting a memory address mapping mode to map memory addresses;
the configuration register sends the generated mapping configuration information to the storage address mapping unit.
2. The on-chip memory address mapping system for vector access of claim 1,
the memory address mapping unit receives signals of the upper limit of the memory mapping address, the lower limit of the memory mapping address and the number of the memory cell blocks from the configuration register, divides a memory address space from the memory and divides the memory address space into a plurality of memory cell blocks; and receiving a mapping mode selection signal from the configuration register, and selecting a corresponding memory address mapping mode to map the memory address.
3. The on-chip memory address mapping system of claim 1, wherein the mapping configuration information comprises an upper memory mapping address limit, a lower memory mapping address limit, a number of memory cell blocks, and a mapping mode selection signal.
4. The on-chip memory address mapping system of claim 1, wherein the memory address mapping scheme comprises a linear mapping scheme and an interleaved memory address mapping scheme.
5. The on-chip memory address mapping system of claim 2, wherein the memory address mapping unit selects a linear mapping manner to map the memory address when the received mapping mode selection signal is equal to 0; when the received mapping mode selection signal is equal to 1, the interleaving memory address mapping mode is selected to map the memory address.
6. A method of on-chip memory address mapping for vector access, comprising the steps of,
1) dividing a memory address space from a memory and dividing the memory address space into a plurality of memory unit blocks;
2) selecting a corresponding memory address mapping mode according to the mapping mode selection signal;
3) storing the write memory vector data to a corresponding memory cell block according to the selected memory address mapping mode;
4) and according to the selected memory address mapping mode, reading memory vector data from the corresponding memory unit block and forwarding the memory vector data to the vector data access unit.
7. The method of claim 6, wherein the step 1) further comprises the memory address mapping unit receiving the upper memory mapping address limit, the lower memory mapping address limit, and the number of memory cell blocks signal from the configuration register, dividing a memory address space from the memory, and dividing the memory address space into a plurality of memory cell blocks.
8. The on-chip memory address mapping method for vector access according to claim 6, wherein the step 2) further comprises the memory address mapping unit receiving the mapping mode selection signal from the configuration register, and selecting the linear mapping mode or the staggered memory address mapping mode for memory address mapping.
9. A system-on-chip comprising the on-chip memory address mapping system for vector access of any of claims 1-5.
10. A computer readable storage medium having stored thereon computer instructions, which when executed perform the steps of the method for on-chip memory address mapping for vector access of any of claims 6-8.
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