CN114325414B - Detection circuit and detection method for battery floating state - Google Patents
Detection circuit and detection method for battery floating state Download PDFInfo
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- CN114325414B CN114325414B CN202111647627.2A CN202111647627A CN114325414B CN 114325414 B CN114325414 B CN 114325414B CN 202111647627 A CN202111647627 A CN 202111647627A CN 114325414 B CN114325414 B CN 114325414B
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Abstract
The application discloses a detection circuit and a detection method for a battery floating state, and belongs to the technical field of integrated circuits. The dv/dt detection circuit in the circuit is used for sending a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold value; the capacitor detection circuit is used for controlling the charge management circuit to turn off the power device according to the pulse signal, detecting the capacitor of the battery port, determining that the battery port is in a battery floating state when the capacitor is smaller than or equal to a second threshold value, and controlling the LED to output an LED signal through the LED driving circuit to prompt; when the capacitance is larger than a second threshold value, the battery port is determined not to be in a battery floating state, the charging management circuit is controlled to start the power device, the capacitance of the battery port is stopped to be detected, and the dv/dt detection circuit is controlled to continuously detect dv/dt. The method and the device can effectively and reliably detect the battery floating state in the battery charging process.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a detection circuit and a detection method for a battery floating state.
Background
Currently, new energy technology is paid attention to, and battery applications are becoming more and more widespread, such as batteries for electric vehicles, mobile phones, portable electronic products, etc. Therefore, battery charging technology is becoming more and more important.
Generally, a charging management circuit can be used for controlling the charging of the battery, so that the battery is prevented from being damaged by overlarge current or overlarge voltage and the like, and the purpose of protecting the battery is achieved. In the process of charging the battery, if the port connected with the battery by the charge management circuit is disconnected from the battery, the battery cannot be charged, but the charge management circuit can mistakenly consider that the battery is fully charged, so that the normal use of the electronic product can be affected, and even the charge management circuit can be damaged or the service life of the battery can be affected.
Disclosure of Invention
The embodiment of the application provides a detection circuit and a detection method for a battery floating state, which are used for solving the problem that a charging management circuit can be damaged or the service life of a battery is influenced when a port connected with the battery of the charging management circuit is disconnected with the battery. The technical scheme is as follows:
in one aspect, a detection circuit for a battery float state is provided, the detection circuit for a battery float state including: the LED driving circuit comprises a dv/dt detection circuit, a capacitance detection circuit, an LED driving circuit, a charging management circuit and a power device;
the input end of the dv/dt detection circuit, the detection input end of the capacitance detection circuit, the feedback input end of the charge management circuit and the output end of the power device are respectively connected with a battery port; the output end of the dv/dt detection circuit is connected with the enabling input end of the capacitance detection circuit; the clock input end of the capacitance detection circuit is connected with the clock signal input end; the first output end of the capacitance detection circuit is connected with the input of the LED driving circuit; the second output end of the capacitance detection circuit is connected with the first input end of the charging management circuit; the output end of the LED driving circuit is connected with the LEDs; the output end of the charging management circuit is connected with the control end of the power device;
the dv/dt detection circuit is used for sending a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold value; the capacitor detection circuit is used for controlling the charging management circuit to turn off the power device according to the pulse signal, detecting the capacitor of the battery port, determining that the battery port is in a battery floating state when the capacitor is smaller than or equal to a second threshold value, and controlling the LED to output an LED signal through the LED driving circuit to prompt; and when the capacitance is larger than the second threshold value, determining that the battery port is not in a battery floating state, controlling the charging management circuit to start the power device, stopping detecting the capacitance of the battery port, and controlling the dv/dt detection circuit to continuously detect the dv/dt of the battery port.
In one possible implementation, the dv/dt detection circuit includes: a first comparator, a level shift, a resistor, and a capacitor;
the level-shifted input and one end of the resistor are used as the input end of the dv/dt detection circuit; the other end of the resistor and one end of the capacitor are respectively connected with the inverting input end of the first comparator; the other end of the capacitor is grounded; the output end of the level shift is connected with the non-inverting input end of the first comparator; the output end of the first comparator is used as the output end of the dv/dt detection circuit.
In one possible implementation, the level shifted output voltage is lower than the input voltage of the battery port by a preset positive voltage value.
In one possible implementation, the capacitance detection circuit includes: logic circuit, pulse generator, second comparator, counter, register, first current source, second current source, first switch, second switch, third switch and fourth switch;
the input end of the logic circuit is used as an enabling input end of the capacitance detection circuit; the first feedback end of the logic circuit is respectively connected with the output end of the pulse generator, the zero clearing end of the counter and the clock end of the register; the second feedback end of the logic circuit is connected with the output end of the register; the output end of the logic circuit is respectively connected with the enabling input end of the pulse generator and the enabling input end of the second comparator, and the output end of the logic circuit is used as the second output end of the capacitance detection circuit;
the clock input end of the pulse generator is used as the clock input end of the capacitance detection circuit; one end of the first switch, one end of the second switch and the non-inverting input end of the second comparator are connected and then used as detection input ends of the capacitance detection circuit; two ends of the first current source are respectively connected with a power supply and the other end of the first switch; two ends of the second current source are respectively connected with the other end of the second switch and the ground; a first reference voltage input terminal is connected to an inverting input terminal of the second comparator through the third switch, and a second reference voltage input terminal is connected to an inverting input terminal of the second comparator through the fourth switch; the output end of the second comparator is connected with the clock end of the counter; the output end of the counter is connected with the data input end of the register; the output of the register is used as a first output of the capacitance detection circuit.
In one possible implementation, when the output signal of the logic circuit is at a high level, the pulse generator, the second comparator, the first switch and the second switch are turned on under the control of the output signal; when the output signal of the logic circuit is at a low level, the pulse generator, the second comparator, the first switch and the second switch are closed under the control of the output signal;
if the first reference voltage is greater than the second reference voltage, when the output signal of the second comparator is at a high level, the third switch is turned off under the control of the output signal, and the fourth switch is turned on under the control of the output signal; when the output signal of the second comparator is at a low level, the third switch is turned on under the control of the output signal, and the fourth switch is turned off under the control of the output signal; the first reference voltage is an input voltage of the first reference voltage input end, and the second reference voltage is an input voltage of the second reference voltage input end.
In one possible implementation manner, when the enable signal input by the enable input end of the capacitance detection circuit is a pulse signal, the output signal of the logic circuit is at a high level, and the capacitance detection circuit is used for starting to detect the capacitance;
after the output signal of the logic circuit changes to a high level, when the enable signal input by the enable input end of the capacitance detection circuit is a low level and the input signal of the second feedback end at the negative edge of the input signal of the first feedback end is a low level, the output signal of the logic circuit is a low level, otherwise, the output signal of the logic circuit is a high level.
In one possible implementation, when the enable signal input by the enable input terminal of the pulse generator is at a low level, the output signal of the pulse generator is at a low level;
when the enabling signal input by the enabling input end of the pulse generator is in a high level, the output signal of the pulse generator is a periodic pulse signal, and the period of the pulse signal is M clock signal periods.
In one possible implementation manner, when the input signal of the zero clearing end of the counter is low level, the counter counts the input pulse signals through the clock end under the control of the input signal; if the count value is N, the output signal of the counter is high level; if the count value is smaller than N, the output signal of the counter is in a low level;
when the input signal of the zero clearing end of the counter is high level, the counter carries out zero clearing operation on the count value under the control of the input signal, and the output signal of the counter is low level.
In one possible implementation, at a positive edge of an input signal at a clock end of the register, the register is configured to read, store, and output input data at the data input end;
when the input signal of the LED driving circuit is at a high level, the LED driving circuit sends an indication signal to the LED under the control of the input signal, wherein the indication signal is used for indicating the LED to output a long-bright LED signal or a LED signal flashing according to a preset rule.
In another aspect, there is provided a method for detecting a battery float state, for use in a detection circuit for a battery float state as described above, the method comprising:
the dv/dt detection circuit sends a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold;
the capacitance detection circuit controls the charging management circuit to turn off the power device according to the pulse signal and detects the capacitance of the battery port;
when the capacitance is smaller than or equal to a second threshold value, the capacitance detection circuit determines that the battery port is in a battery floating state, and the LED driving circuit outputs an LED signal for prompting;
and when the capacitance is larger than the second threshold value, the capacitance detection circuit determines that the battery port is not in a battery floating state, controls the charging management circuit to start the power device, stops detecting the capacitance of the battery port, and controls the dv/dt detection circuit to continuously detect the dv/dt of the battery port.
The beneficial effects of the technical scheme provided by the embodiment of the application at least comprise:
the dv/dt detection circuit can send pulse signals to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold, so that the capacitance detection circuit can control the charge management circuit to turn off the power device according to the pulse signals and detect the capacitance of the battery port, when the capacitance is smaller than or equal to a second threshold, the battery port is determined to be in a battery floating state, and the LED driving circuit is used for controlling the LED to output an LED signal for prompting, so that the battery floating state in the battery charging process can be effectively and reliably detected, and the charge management circuit and the battery can be better protected.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a detection circuit for a battery floating state according to the present disclosure;
FIG. 2 is a schematic diagram of a dv/dt detection circuit as proposed herein;
FIG. 3 is a diagram showing waveforms of operation of a dv/dt detection circuit according to the present application;
FIG. 4 is a schematic diagram of a capacitance detection circuit according to the present disclosure;
FIG. 5 is a waveform diagram illustrating the operation of a battery float condition detection circuit according to the present disclosure;
FIG. 6 is a flowchart of a method for detecting a floating state of a battery according to the present disclosure;
fig. 7 is a flowchart of another method for detecting a battery floating state according to the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, a schematic structural diagram of a detection circuit for a battery floating state according to an embodiment of the present application is shown. The detection circuit of the battery floating state may include: the dv/dt detection circuit 100, the capacitance detection circuit 200, the LED driving circuit 300, the charge management circuit 400, and the power device 500 are described below with respect to the connection relationship between the circuits and the devices.
Specifically, the input end of the dv/dt detection circuit 100, the detection input end of the capacitance detection circuit 200, the feedback input end of the charge management circuit 400, and the output end of the power device 500 are respectively connected with a battery port (BAT); the output end of the dv/dt detection circuit 100 is connected with the enabling input end of the capacitance detection circuit 200; the clock input of the capacitance detection circuit 200 is connected to the clock signal input (CLK); a first output of the capacitance detection circuit 200 is connected to an input of the LED driver circuit 300; a second output terminal of the capacitance detection circuit 200 is connected to a first input terminal of the charge management circuit 400; the output end of the LED driving circuit 300 is connected with an LED; an output terminal of the charge management circuit 400 is connected to a control terminal of the power device 500. In addition, the input of the power device 500 is connected to the power supply VDD.
In this embodiment, the dv/dt detection circuit 100 is used to detect the voltage rising speed of the battery port (BAT), i.e., dv/dt. The configuration of the dv/dt detection circuit 100 is described below.
As shown in fig. 2, the dv/dt detection circuit 100 may include: a first comparator 101, a level shift 102, a resistor 103 and a capacitor 104. Wherein the input of the level shift 102 and one end of the resistor 103 are used as the input of the dv/dt detection circuit 100, i.e. connected to a battery port (BAT); the other end of the resistor 103 and one end of the capacitor 104 are respectively connected with the inverting input end of the first comparator 101; the other end of the capacitor 104 is grounded; an output terminal of the level shift 102 is connected to a non-inverting input terminal of the first comparator 101; the output of the first comparator 101 serves as the output of the dv/dt detection circuit 100. Wherein the output voltage of the level shift 102 is lower than the input voltage of the battery port (BAT) by a preset positive voltage value.
Fig. 3 shows an operation waveform diagram of the dv/dt detection circuit 100, in which the non-inverting input voltage of the first comparator 101 in fig. 3 is v+, the inverting input voltage is V-, the BAT terminal voltage minus the v+ terminal voltage is VT, i.e., BAT-v+=vt, VT is a fixed value, v+ varies with BAT, v+ does not vary with BAT, but has a delay, and the delay is related to the resistor 103 and the capacitor 104. Therefore, when BAT changes faster, a situation occurs in which v+ is greater than V-, at which time the output Signal (SEN) of the first comparator 101 is a pulse signal; and when the BAT voltage is not changed or is changed slowly (dv/dt is small), the output Signal (SEN) of the first comparator 101 is low level.
In this embodiment, the capacitance detection circuit 200 is configured to detect a capacitance of a battery port (BAT), and determine whether the battery is in a floating state according to a detection result. The structure of the capacitance detection circuit 200 will be described below.
As shown in fig. 4, the capacitance detection circuit 200 may include: logic circuit 201, pulse generator 202, second comparator 203, counter 204, register 205, first current source 206, second current source 207, first switch 208, second switch 209, third switch 210, and fourth switch 211; the input end of the logic circuit 201 is used as the enabling input end of the capacitance detection circuit 200, namely, the input signal is SEN; the first feedback end of the logic circuit 201 is respectively connected with the output end of the pulse generator 202, the zero clearing end of the counter 204 and the clock end of the register 205; a second feedback terminal of the logic circuit 201 is connected to an output terminal of the register 205; the output end of the logic circuit 201 is respectively connected with the enable input end of the pulse generator 202 and the enable input end of the second comparator 203, and the output end of the logic circuit 201 is used as the second output end of the capacitance detection circuit 200, namely, the output signal is EN; the clock input of the pulse generator 202 is used as the clock input of the capacitance detection circuit 200, i.e. the input signal is CLK; one end of the first switch 208, one end of the second switch 209, and the non-inverting input terminal of the second comparator 203 are connected and then used as the detection input terminal of the capacitance detection circuit 200, i.e. the input signal is BAT; both ends of the first current source 206 are connected to a power source (VDD) and the other end of the first switch 208, respectively; both ends of the second current source 207 are respectively connected with the other end of the second switch 209 and the ground; the first reference voltage input terminal (Vref 1) is connected to the inverting input terminal of the second comparator 203 through the third switch 210, and the second reference voltage input terminal (Vref 2) is connected to the inverting input terminal of the second comparator 203 through the fourth switch 211; the output end of the second comparator 203 is connected with the clock end of the counter 204; the output of the counter 204 is connected to the data input of the register 205; the output of the register 205 is used as the first output of the capacitance detection circuit 200, i.e. the output signal is FLT. The operation states of the respective circuits in the capacitance detection circuit 200 are described below.
(1) Logic circuit 201:
when the output signal (EN) of the logic circuit 201 is at a high level (i.e., an active signal), the pulse generator 202, the second comparator 203, the first switch 208, and the second switch 209 are turned on under the control of the output signal (EN); when the output signal (EN) of the logic circuit 201 is at a low level (i.e., an inactive signal), the pulse generator 202, the second comparator 203, the first switch 208, and the second switch 209 are turned off under the control of the output signal (EN).
If the first reference voltage (Vref 1) is greater than the second reference voltage (Vref 2), when the output signal (CM) of the second comparator 203 is at a high level, the third switch 210 is turned off under the control of the output signal (CM), and the fourth switch 211 is turned on under the control of the output signal (CM); when the output signal (CM) of the second comparator 203 is at a low level, the third switch 210 is turned on under the control of the output signal (CM), and the fourth switch 211 is turned off under the control of the output signal (CM); the first reference voltage (Vref 1) is an input voltage of the first reference voltage input end, and the second reference voltage (Vref 2) is an input voltage of the second reference voltage input end.
When the enable Signal (SEN) input from the enable input terminal of the capacitance detection circuit 200 is a pulse signal, the output signal (EN) of the logic circuit 201 is at a high level (i.e., an active signal), and the capacitance detection circuit 200 is configured to start detecting the capacitance; after the output signal of the logic circuit 201 changes to the high level, when the enable Signal (SEN) input from the enable input terminal of the capacitance detection circuit 200 is at the low level and the input signal of the second feedback terminal (output of the register 205) is at the low level at the negative edge of the input signal of the first feedback terminal (output of the pulse generator 202), the output signal (EN) of the logic circuit 201 is at the low level (i.e., the inactive signal), otherwise the output signal (EN) of the logic circuit 201 is still at the high level.
(2) Pulse generator 202:
when the enable signal input from the enable input terminal of the pulse generator 202 is at a low level, the output signal of the pulse generator 202 is at a low level; when the enable signal input from the enable input terminal of the pulse generator 202 is at a high level, the output signal of the pulse generator 202 is a periodic pulse signal P, the period of the pulse signal P is T, and T is equal to M clock signal CLK periods.
(3) Counter 204:
when the input signal of the zero clearing end of the counter 204 is at a low level, the counter 204 counts the input pulse signals through the clock end under the control of the input signal; if the count value is N, the output signal of the counter 204 is high; if the count value is less than N, the output signal of the counter 204 is low; when the input signal at the zero end of the counter 204 is at a high level, the counter 204 performs zero clearing operation on the count value under the control of the input signal, and the output signal of the counter 204 is at a low level.
That is, when the input signal at the clear end is at the low level, the counter 204 performs the accumulation operation on the input pulse signal P, and when the count value (accumulation operation result) is equal to N before the arrival of the clear signal, the output of the counter 204 is at the high level until the clear signal arrives, the count value of the counter 204 is cleared, and the output becomes the low level; if the count value is less than N, the output of the counter 204 is constantly low.
(4) Register 205:
at the positive edge of the input signal at the clock end of the register 205, the register 205 is used to read, store and output the input data at the data input end.
When the input signal of the LED driving circuit 300 is at a high level, the LED driving circuit 300 emits an indication signal for instructing the LED to output a long-lighted LED signal or an LED signal blinking with a predetermined rule to the LED (light emitting diode) under the control of the input signal.
The following describes the operation principle of the detection circuit for the battery floating state.
A dv/dt detection circuit 100 for sending a pulse signal to the capacitance detection circuit 200 when it is detected that the dv/dt of the battery port exceeds a first threshold value; the capacitance detection circuit 200 is configured to control the charge management circuit 400 to turn off the power device 500 according to the pulse signal, detect a capacitance of the battery port, determine that the battery port is in a battery floating state when the capacitance is less than or equal to a second threshold, and control the LED driving circuit 300 to output an LED signal for prompting; when the capacitance is greater than the second threshold, it is determined that the battery port is not in a battery floating state, the charge management circuit 400 is controlled to turn on the power device 500, the detection of the capacitance of the battery port is stopped, and the dv/dt detection circuit 100 is controlled to continue to detect the dv/dt of the battery port.
Fig. 5 shows an operation waveform diagram of the detection circuit of the battery floating state, when the voltage of the battery port (BAT) rises faster, the dv/dt detection circuit 100 outputs a pulse Signal (SEN), and at this time, the output signal (EN) of the logic circuit 201 becomes high level, and the capacitance detection circuit 200 continuously operates while EN is high level, and continuously detects the capacitance of the battery port (BAT). The voltage of the battery port (BAT) is a triangular wave, the triangular wave is converted into a pulse signal CM, if the pulse number of the pulse signal CM reaches or exceeds a second threshold value N in the time T, the battery port (BAT) is in a battery floating state, and the state signal FLT is changed to a high level to control the LED to give an instruction. If the number of pulses of the pulse signal CM is smaller than the second threshold value N during the period EN is at the high level, it means that the battery is not in the floating state, and the state signal FLT becomes at the low level. The period of the pulse signal P is T, and the high level output by the pulse generator 202 may perform an initializing (clearing) operation on the counter 204, while the positive edge of the pulse signal P operates on the register 205 to load the state signal FLT, and the negative edge of the pulse signal P and the state signal FLT perform a resetting operation on EN (i.e., change from high level to low level). Meanwhile, the power device 500 is turned off during the period in which EN is high, preventing it from interfering with the capacitance detection.
In summary, in the detection circuit for the battery floating state provided in this embodiment, since the dv/dt detection circuit can send a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds the first threshold, the capacitance detection circuit can control the charge management circuit to turn off the power device according to the pulse signal and detect the capacitance of the battery port, and when the capacitance is less than or equal to the second threshold, the battery port is determined to be in the battery floating state, and the LED driving circuit controls the LED to output the LED signal for prompting, the battery floating state in the battery charging process can be effectively and reliably detected, so that the charge management circuit and the battery can be better protected.
Referring to fig. 6, a flowchart of a method for detecting a battery floating state according to an embodiment of the present application is shown, which is used in the detection circuit for a battery floating state as described above. The method for detecting the floating state of the battery can comprise the following steps:
in step 601, the dv/dt detection circuit sends a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold.
Wherein the output Signal (SEN) of the dv/dt detection circuit is high.
In step 602, the capacitance detection circuit controls the charge management circuit to turn off the power device according to the pulse signal, and detects the capacitance of the battery port.
And step 603, when the capacitance is smaller than or equal to the second threshold value, the capacitance detection circuit determines that the battery port is in a battery floating state, and the LED driving circuit outputs an LED signal for prompting.
When the battery is in a floating state, the capacitance detection circuit outputs a high-level FLT to the LED driving circuit, and the LED driving circuit sends an indication signal to the LED under the control of an input signal, wherein the indication signal is used for indicating the LED to output a long-lighting LED signal or a flashing LED signal according to a preset rule.
And step 604, when the capacitance is greater than the second threshold, the capacitance detection circuit determines that the battery port is not in a battery floating state, controls the charge management circuit to start the power device, stops detecting the capacitance of the battery port, and controls the dv/dt detection circuit to continuously detect the dv/dt of the battery port.
Referring to the flowchart shown in fig. 7, after the detection circuit of the battery floating state is started, firstly detecting dv/dt of the battery port, if dv/dt is greater than a first threshold vtx, forcibly turning off the power device, and detecting the capacitance of the battery port; if the capacitance is smaller than or equal to the second threshold cx, determining that the battery is in a floating state, and controlling the LED to prompt; if the capacitance is larger than the second threshold value cx, the capacitance detection is turned off, the forced turn-off of the power device is released, and the battery is charged by the charging management module.
In summary, according to the method for detecting the battery floating state provided by the embodiment, since the dv/dt detection circuit can send the pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds the first threshold, the capacitance detection circuit can control the charge management circuit to turn off the power device according to the pulse signal and detect the capacitance of the battery port, and when the capacitance is smaller than or equal to the second threshold, the battery port is determined to be in the battery floating state, and the LED driving circuit is used for controlling the LED to output the LED signal for prompting, the battery floating state in the battery charging process can be effectively and reliably detected, and therefore the charge management circuit and the battery can be better protected.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description is not intended to limit the embodiments of the present application, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the embodiments of the present application are intended to be included within the scope of the embodiments of the present application.
Claims (10)
1. A detection circuit of a battery float state, characterized in that the detection circuit of a battery float state comprises: the LED driving circuit comprises a dv/dt detection circuit, a capacitance detection circuit, an LED driving circuit, a charging management circuit and a power device;
the input end of the dv/dt detection circuit, the detection input end of the capacitance detection circuit, the feedback input end of the charge management circuit and the output end of the power device are respectively connected with a battery port; the output end of the dv/dt detection circuit is connected with the enabling input end of the capacitance detection circuit; the clock input end of the capacitance detection circuit is connected with the clock signal input end; the first output end of the capacitance detection circuit is connected with the input end of the LED driving circuit; the second output end of the capacitance detection circuit is connected with the first input end of the charging management circuit; the output end of the LED driving circuit is connected with the LEDs; the output end of the charging management circuit is connected with the control end of the power device;
the dv/dt detection circuit is used for sending a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold value; the capacitor detection circuit is used for controlling the charging management circuit to turn off the power device according to the pulse signal, detecting the capacitor of the battery port, determining that the battery port is in a battery floating state when the capacitor is smaller than or equal to a second threshold value, and controlling the LED to output an LED signal through the LED driving circuit to prompt; and when the capacitance is larger than the second threshold value, determining that the battery port is not in a battery floating state, controlling the charging management circuit to start the power device, stopping detecting the capacitance of the battery port, and controlling the dv/dt detection circuit to continuously detect the dv/dt of the battery port.
2. The circuit of claim 1, wherein the dv/dt detection circuit comprises: a first comparator, a level shift, a resistor, and a capacitor;
the level-shifted input and one end of the resistor are used as the input end of the dv/dt detection circuit; the other end of the resistor and one end of the capacitor are respectively connected with the inverting input end of the first comparator; the other end of the capacitor is grounded; the output end of the level shift is connected with the non-inverting input end of the first comparator; the output end of the first comparator is used as the output end of the dv/dt detection circuit.
3. The circuit of claim 2, wherein the level shifted output voltage is lower than the input voltage of the battery port by a predetermined positive voltage value.
4. A circuit according to any one of claims 1 to 3, wherein the capacitance detection circuit comprises: logic circuit, pulse generator, second comparator, counter, register, first current source, second current source, first switch, second switch, third switch and fourth switch;
the input end of the logic circuit is used as an enabling input end of the capacitance detection circuit; the first feedback end of the logic circuit is respectively connected with the output end of the pulse generator, the zero clearing end of the counter and the clock end of the register; the second feedback end of the logic circuit is connected with the output end of the register; the output end of the logic circuit is respectively connected with the enabling input end of the pulse generator and the enabling input end of the second comparator, and the output end of the logic circuit is used as the second output end of the capacitance detection circuit;
the clock input end of the pulse generator is used as the clock input end of the capacitance detection circuit; one end of the first switch, one end of the second switch and the non-inverting input end of the second comparator are connected and then used as detection input ends of the capacitance detection circuit; two ends of the first current source are respectively connected with a power supply and the other end of the first switch; two ends of the second current source are respectively connected with the other end of the second switch and the ground; a first reference voltage input terminal is connected to an inverting input terminal of the second comparator through the third switch, and a second reference voltage input terminal is connected to an inverting input terminal of the second comparator through the fourth switch; the output end of the second comparator is connected with the clock end of the counter; the output end of the counter is connected with the data input end of the register; the output of the register is used as a first output of the capacitance detection circuit.
5. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
when the output signal of the logic circuit is high level, the pulse generator, the second comparator, the first switch and the second switch are turned on under the control of the output signal; when the output signal of the logic circuit is at a low level, the pulse generator, the second comparator, the first switch and the second switch are closed under the control of the output signal;
if the first reference voltage is greater than the second reference voltage, when the output signal of the second comparator is at a high level, the third switch is turned off under the control of the output signal, and the fourth switch is turned on under the control of the output signal; when the output signal of the second comparator is at a low level, the third switch is turned on under the control of the output signal, and the fourth switch is turned off under the control of the output signal; the first reference voltage is an input voltage of the first reference voltage input end, and the second reference voltage is an input voltage of the second reference voltage input end.
6. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
when the enabling signal input by the enabling input end of the capacitance detection circuit is a pulse signal, the output signal of the logic circuit is high level, and the capacitance detection circuit is used for starting to detect the capacitance;
after the output signal of the logic circuit changes to a high level, when the enable signal input by the enable input end of the capacitance detection circuit is a low level and the input signal of the second feedback end at the negative edge of the input signal of the first feedback end is a low level, the output signal of the logic circuit is a low level, otherwise, the output signal of the logic circuit is a high level.
7. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
when the enabling signal input by the enabling input end of the pulse generator is in a low level, the output signal of the pulse generator is in a low level;
when the enabling signal input by the enabling input end of the pulse generator is in a high level, the output signal of the pulse generator is a periodic pulse signal, and the period of the pulse signal is M clock signal periods.
8. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
when the input signal of the zero clearing end of the counter is low level, the counter counts the input pulse signals through the clock end under the control of the input signal; if the count value is N, the output signal of the counter is high level; if the count value is smaller than N, the output signal of the counter is in a low level;
when the input signal of the zero clearing end of the counter is high level, the counter carries out zero clearing operation on the count value under the control of the input signal, and the output signal of the counter is low level.
9. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
at the positive edge of the input signal of the clock end of the register, the register is used for reading, storing and outputting the input data of the data input end;
when the input signal of the LED driving circuit is at a high level, the LED driving circuit sends an indication signal to the LED under the control of the input signal, wherein the indication signal is used for indicating the LED to output a long-bright LED signal or a LED signal flashing according to a preset rule.
10. A method for detecting a battery float condition according to any one of claims 1 to 9, the method comprising:
the dv/dt detection circuit sends a pulse signal to the capacitance detection circuit when detecting that the dv/dt of the battery port exceeds a first threshold;
the capacitance detection circuit controls the charging management circuit to turn off the power device according to the pulse signal and detects the capacitance of the battery port;
when the capacitance is smaller than or equal to a second threshold value, the capacitance detection circuit determines that the battery port is in a battery floating state, and the LED driving circuit outputs an LED signal for prompting;
and when the capacitance is larger than the second threshold value, the capacitance detection circuit determines that the battery port is not in a battery floating state, controls the charging management circuit to start the power device, stops detecting the capacitance of the battery port, and controls the dv/dt detection circuit to continuously detect the dv/dt of the battery port.
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| US10353013B2 (en) * | 2015-02-27 | 2019-07-16 | Fujitsu Ten Limited | Voltage detection device, voltage detection method, abnormality determination device, abnormality determination method, and battery pack system |
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