CN114296993A - Data verification method, equipment and medium based on cache - Google Patents
Data verification method, equipment and medium based on cache Download PDFInfo
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- CN114296993A CN114296993A CN202111660878.4A CN202111660878A CN114296993A CN 114296993 A CN114296993 A CN 114296993A CN 202111660878 A CN202111660878 A CN 202111660878A CN 114296993 A CN114296993 A CN 114296993A
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Abstract
A data verification method based on cache comprises the following steps: establishing second preset byte check data by using each first preset byte data in the cache; responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction; according to the data verification method based on the cache, when data are stored in the cache, verification data are creatively established for the data with a certain size, the data are verified according to the verification data when the data enter or exit the cache, meanwhile, a verification bit field is added in a system bus, the data are verified according to the verification data corresponding to the data when the data are transmitted to other terminals through the system bus, and if the data are abnormal, the mode and the reason of the abnormal data can be accurately positioned. Even in some cases, the abnormal condition can be compensated by means of data reloading. The stability of system operation is improved.
Description
Technical Field
The invention belongs to the field of computers, and particularly relates to a data verification method, data verification equipment and a data verification medium based on cache.
Background
In the high-end embedded field, with the continuous progress of the manufacturing process, the cpu main frequency of an SOC (System-on-a-Chip) is continuously increased, but the main memory is limited to cost and capacity and cannot meet the speed of the cpu, so that adding a cache between the cpu and the main memory is a basic method of the existing processor. However, in the conventional implementation mode, when data has an error, it is impossible to determine which specific addresses have problems, and it is impossible to determine whether the cache has an error or the memory has an error, so that it is difficult to locate the data of the chip. Even the operating states and results of the same program on different devices appear to be different. However, when tracing back the problem, it is difficult to find out whether the problem is caused by the data abnormality stored in the memory during the program operation, or the problem is caused by the data abnormality after the system bus sends the data to the cache, or even the problem of the failure during the system bus transmission. Even when testing the memory and the cache by other memory testing tools or other detection tools, it is difficult to restore the scene when the problem occurs, that is, when the abnormal problem occurs due to randomness, the problem of which storage device or terminal device occurs when the data error or abnormality occurs cannot be accurately judged in time by the subsequent testing means.
Therefore, an effective solution to the above problems is needed.
Disclosure of Invention
In order to solve the above problems, the present invention provides a data verification method based on a cache, including:
establishing second preset byte check data by using each first preset byte data in the cache;
and responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction.
In some embodiments of the invention, the method further comprises:
and adding a check bit field in a system bus, and transmitting the check data through the check bit field.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction includes:
in response to the data being written into the cache, verifying the written data according to the verification data of the written data;
writing the data into the cache in response to a verification success;
and responding to the verification failure, and sending a data source error report to the system according to the source of the data.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction, further includes:
responding to the reading of data from the cache, verifying the data according to the corresponding verification data of the data in the cache, and judging the verification result;
responding to the verification result that the verification result is passed, reading the data and sending the data to a corresponding data reading end through a system bus;
and responding to the result of the verification as failure, and sending a cache error report to the system.
In some embodiments of the invention, the method further comprises
In response to the data being written into the cache by the CPU, calculating, by the CPU, check data of a second predetermined byte size corresponding to the first predetermined byte data for every first predetermined byte of the data, and sending the written data and the check data corresponding thereto to the cache through a system bus.
In some embodiments of the invention, the method further comprises:
responding to the data written into the cache by the memory, and verifying according to the data in the memory and the verification data corresponding to the data;
responding to the verification result that the data and the corresponding verification data are sent to the cache through a system bus;
and sending a memory data error report to the system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the CPU to read data from the cache, and verifying the read data and the corresponding verification data through the CPU;
and sending a system bus error report to an operating system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the memory to read data from the cache, and verifying the data read by the memory and the corresponding verification data through a memory controller of the memory;
and sending a system bus error report to an operating system in response to the verification result being failure.
Another aspect of the present invention further provides a computer device, including:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of the above embodiments.
Yet another aspect of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program realizes the steps of the method of any one of the above embodiments when executed by a processor.
According to the data verification method based on the cache, when data are stored in the cache, verification data are creatively established for the data with a certain size, the data are verified according to the verification data when the data enter or exit the cache, meanwhile, a verification bit field is added in a system bus, the data are verified according to the verification data corresponding to the data when the data are transmitted to other terminals through the system bus, and if the data are abnormal, the mode and the reason of the abnormal data can be accurately positioned. Even in some cases, the abnormal condition can be compensated by means of data reloading. The stability of system operation is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method according to an embodiment of a data checking method based on a cache according to the present invention;
FIG. 2 is a schematic structural diagram of a computer device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a computer storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
As shown in fig. 1, the present invention provides a data checking method based on a cache, including:
step S1, establishing second predetermined byte check data in the buffer memory according to the first predetermined byte data;
and step S2, responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction.
In step S1, a data storage manner is defined in the cache, the data stored in the cache is grouped, each 64 bytes is used as a group, meanwhile, corresponding 8-bit, i.e., 1-byte, check data is established for each group of data, and the check data and each corresponding group of data are calculated by a corresponding check algorithm, so as to ensure unique correlation.
In step S2, when the CPU or the memory reads data from or writes data into the cache, the CPU or the memory writes data into the cache in the format in which the data is stored in the cache in step S1 (i.e., an extra 1-byte check data is added to each 64-byte data), the write data corresponding to the 1-byte check data is checked by the 1-byte check data, and if the check is successful, the data is written into the cache. Similarly, when data is read from the buffer, the read data is also verified according to verification data corresponding to the read data. And if the verification result is passed, allowing the reading from the buffer.
It should be noted that, in the embodiments of the present invention, data is written into or read from the buffer, that is, data is written into or read from a group of 64 bytes and check data of 1 byte (8 bits) corresponding to the group of 64 bytes. The data is transmitted and stored (stored in a buffer) after being grouped according to a mode of establishing 1 byte check data by 64 bytes. That is, there are cases of grouping and complementing data, that is, when a transmission task is normal, the data is transmitted and stored in a group of 64 bytes (when the amount of data is small, the amount of data is rarely small), when the amount of data is very small, and the amount of data is less than 64 bytes, 64 bytes are complemented by filling predetermined content, and then the data after 64 bytes are complemented is calculated to obtain 1-byte check data.
In some embodiments of the invention, the method further comprises:
and adding a check bit field in a system bus, and transmitting the check data through the check bit field.
In this embodiment, in order to facilitate the storage of data according to the predetermined format, the invention adds a check bit field in the system bus, that is, the transmitter checks data while transmitting data. When data is transmitted in the system bus, check data needs to be transmitted at the same time, namely, the completion of data transmission does not represent the completion of one transmission request every time. Specifically, when data is transmitted on the system bus, if a transmission request of a data address in a cache or a memory is involved, a corresponding address of check data needs to be attached, and the data transmission is considered to be completed only when the data transmission on the data address and the data transmission on the address of the check data are completed.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction includes:
in response to the data being written into the cache, verifying the written data according to the verification data of the written data;
writing the data into the cache in response to a verification success;
and responding to the verification failure, and sending a data source error report to the system according to the source of the data.
In this embodiment, when data is written into the cache, the data to be written is acquired through the system bus, before the data is stored in the cache, the acquired write data and the corresponding check data are verified, if the verification is passed, the data is written into the cache, and if the verification is not passed, a data error report is reported to the system (operating system), and address information on the system bus is reported to the system together. To identify that a data error has not occurred in the cache.
Specifically, data is obtained from the system bus by taking 64 bytes as a unit, check data corresponding to the 64 bytes of data is obtained at the same time, the 64 bytes of data are calculated according to a check data generation algorithm to generate new check data, whether the newly generated check data is the same as the received check data is judged, and if the newly generated check data is the same as the received check data, the check-passed data can be sent to the cache. If the data is different, reporting the failure of data verification acquired from the system bus to the operating system, and attaching traceable information such as address information of the data on the bus.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction, further includes:
responding to the reading of data from the cache, verifying the data according to the corresponding verification data of the data in the cache, and judging the verification result;
responding to the verification result that the verification result is passed, reading the data and sending the data to a corresponding data reading end through a system bus;
and responding to the result of the verification as failure, and sending a cache error report to the system.
In this embodiment, similar to the above embodiments, if data is read from the buffer, the data is verified according to the verification data corresponding to the data before being sent to the bus. And calculating new check data of the data according to a check data generation algorithm, comparing the check data read from the cache, if the check data are the same, if the check data pass the check, if the check data do not pass the check, the check fails, and reporting that the data read from the cache have errors to the system in time.
In some embodiments of the present invention, the operating system reports the address of the cache with the error while reporting the error in the cache. The operating system may mask the cache space where the error occurred as needed.
In some embodiments of the present invention, the operating system sends the masked cache address to the cache controller to send the address space to be masked, and when data is written into the corresponding address space, the corresponding data is written into other cache space addresses in a backup manner.
In some embodiments of the invention, the method further comprises
In response to the data being written into the cache by the CPU, calculating, by the CPU, check data of a second predetermined byte size corresponding to the first predetermined byte data for every first predetermined byte of the data, and sending the written data and the check data corresponding thereto to the cache through a system bus.
In this embodiment, if the data is written from the CPU into the cache, 1-byte check data is generated by the CPU as a group of 64-byte data, and then the 64-byte data and the corresponding data check are transmitted to the system bus. In particular, the check bit field established in the system bus according to the present invention always transmits 1 byte of check data.
In some embodiments of the invention, the method further comprises:
responding to the data written into the cache by the memory, and verifying according to the data in the memory and the verification data corresponding to the data;
responding to the verification result that the data and the corresponding verification data are sent to the cache through a system bus;
and sending a memory data error report to the system in response to the verification result being failure.
In this embodiment, if data is written from the memory to the cache, the data is verified when the data is read from the memory. And if the check is successful, the data is sent to the cache through the system bus together with the corresponding check data. And if the data is over-checked, sending a report of data errors in the memory to the system.
In some embodiments of the present invention, if the memory type is a self-verified memory, the read of the corresponding data in the memory may be verified directly by an existing verification method of the memory controller. For example, an ECC memory, when data is read from the memory, the data can be checked according to a memory checking method of the ECC.
In some embodiments of the present invention, the check algorithm used by the present invention for the 64 bytes of data corresponding to the 1 byte of check data is a CRC check algorithm. If the memory is an ECC memory, after the ECC memory is checked according to the ECC memory check method, a new CRC check code (according to the 64-byte data 1-byte check data method) is generated by the memory controller and sent to the system bus.
In some embodiments of the present invention, if the memory also adopts the CRC check algorithm, before sending data to the cache terminal on the system bus, the memory controller directly performs CRC check on corresponding data in the memory, and after the check is passed, the 64-byte data and the 1-byte check data are directly sent to the cache through the system bus at the same time.
In some embodiments of the invention, the method further comprises:
responding to the CPU to read data from the cache, and verifying the read data and the corresponding verification data through the CPU;
and sending a system bus error report to an operating system in response to the verification result being failure.
In this embodiment, if only the CPU reads data from the cache, after the CPU reads corresponding data, the CPU performs verification according to the received data and verification data corresponding to the data, and if the verification fails, sends an error report for sending a system bus to the operating system. Since no error occurs in the data when the data is buffered, the data can be considered as a data error occurred in the transmission.
In some embodiments of the invention, the method further comprises:
responding to the memory to read data from the cache, and verifying the data read by the memory and the corresponding verification data through a memory controller of the memory;
and sending a system bus error report to an operating system in response to the verification result being failure.
In this embodiment, if the data is read from the memory and the data read from the memory is sent to the cache side through the system bus, the cache checks the received data according to the check data of the data, and if the check fails, a report that the data transmission by the system bus is in error is sent to the operating system.
In addition, if the verification is successful, the data and the verification data corresponding to the data can be directly stored in the cache.
According to the data verification method based on the cache, provided by the invention, when data is stored in the cache, verification data is creatively established for the data with a certain size, the data is verified according to the verification data when the data enters or exits the cache, meanwhile, a verification bit field is added in a system bus, the data is verified according to the verification data corresponding to the data when the data is transmitted to other terminals through the system bus, and if the data is abnormal, the mode and reason of the abnormal data can be accurately positioned. Even in some cases, the abnormal condition can be compensated by means of data reloading. The stability of system operation is improved.
As shown in fig. 2, another aspect of the present invention further provides a computer device, including:
at least one processor 21; and
a memory 22, said memory 22 storing computer instructions 23 executable on said processor, said instructions when executed by said processor implementing
A data verification method based on cache comprises the following steps:
establishing second preset byte check data by using each first preset byte data in the cache;
and responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction.
In some embodiments of the invention, the method further comprises:
and adding a check bit field in a system bus, and transmitting the check data through the check bit field.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction includes:
in response to the data being written into the cache, verifying the written data according to the verification data of the written data;
writing the data into the cache in response to a verification success;
and responding to the verification failure, and sending a data source error report to the system according to the source of the data.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction, further includes:
responding to the reading of data from the cache, verifying the data according to the corresponding verification data of the data in the cache, and judging the verification result;
responding to the verification result that the verification result is passed, reading the data and sending the data to a corresponding data reading end through a system bus;
and responding to the result of the verification as failure, and sending a cache error report to the system.
In some embodiments of the invention, the method further comprises
In response to the data being written into the cache by the CPU, calculating, by the CPU, check data of a second predetermined byte size corresponding to the first predetermined byte data for every first predetermined byte of the data, and sending the written data and the check data corresponding thereto to the cache through a system bus.
In some embodiments of the invention, the method further comprises:
responding to the data written into the cache by the memory, and verifying according to the data in the memory and the verification data corresponding to the data;
responding to the verification result that the data and the corresponding verification data are sent to the cache through a system bus;
and sending a memory data error report to the system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the CPU to read data from the cache, and verifying the read data and the corresponding verification data through the CPU;
and sending a system bus error report to an operating system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the memory to read data from the cache, and verifying the data read by the memory and the corresponding verification data through a memory controller of the memory;
and sending a system bus error report to an operating system in response to the verification result being failure.
As shown in fig. 3, a further aspect of the present invention also provides a computer-readable storage medium 401, where the computer-readable storage medium 401 stores a computer program 402, and the computer program 402, when executed by a processor, implements a cache-based data checking method, including:
establishing second preset byte check data by using each first preset byte data in the cache;
and responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction.
In some embodiments of the invention, the method further comprises:
and adding a check bit field in a system bus, and transmitting the check data through the check bit field.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction includes:
in response to the data being written into the cache, verifying the written data according to the verification data of the written data;
writing the data into the cache in response to a verification success;
and responding to the verification failure, and sending a data source error report to the system according to the source of the data.
In some embodiments of the present invention, in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction, further includes:
responding to the reading of data from the cache, verifying the data according to the corresponding verification data of the data in the cache, and judging the verification result;
responding to the verification result that the verification result is passed, reading the data and sending the data to a corresponding data reading end through a system bus;
and responding to the result of the verification as failure, and sending a cache error report to the system.
In some embodiments of the invention, the method further comprises
In response to the data being written into the cache by the CPU, calculating, by the CPU, check data of a second predetermined byte size corresponding to the first predetermined byte data for every first predetermined byte of the data, and sending the written data and the check data corresponding thereto to the cache through a system bus.
In some embodiments of the invention, the method further comprises:
responding to the data written into the cache by the memory, and verifying according to the data in the memory and the verification data corresponding to the data;
responding to the verification result that the data and the corresponding verification data are sent to the cache through a system bus;
and sending a memory data error report to the system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the CPU to read data from the cache, and verifying the read data and the corresponding verification data through the CPU;
and sending a system bus error report to an operating system in response to the verification result being failure.
In some embodiments of the invention, the method further comprises:
responding to the memory to read data from the cache, and verifying the data read by the memory and the corresponding verification data through a memory controller of the memory;
and sending a system bus error report to an operating system in response to the verification result being failure.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
In addition, the apparatuses, devices and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal device, such as a server and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Claims (10)
1. A data verification method based on cache is characterized by comprising the following steps:
establishing second preset byte check data by using each first preset byte data in the cache;
and responding to the data interaction with the cache, and performing data verification according to the data related to the data interaction and the verification data corresponding to the data interaction.
2. The method of claim 1, further comprising:
and adding a check bit field in a system bus, and transmitting the check data through the check bit field.
3. The method of claim 1, wherein, in response to the data interaction with the cache, performing a data check according to the data involved in the data interaction and the check data corresponding to the data interaction comprises:
in response to the data being written into the cache, verifying the written data according to the verification data of the written data;
writing the data into the cache in response to a verification success;
and responding to the verification failure, and sending a data source error report to the system according to the source of the data.
4. The method of claim 1, wherein in response to a data interaction with the cache, performing a data check according to data involved in the data interaction and check data corresponding to the data interaction, further comprising:
responding to the reading of data from the cache, verifying the data according to the corresponding verification data of the data in the cache, and judging the verification result;
responding to the verification result that the verification result is passed, reading the data and sending the data to a corresponding data reading end through a system bus;
and responding to the result of the verification as failure, and sending a cache error report to the system.
5. The method of claim 3, further comprising
In response to the data being written into the cache by the CPU, calculating, by the CPU, check data of a second predetermined byte size corresponding to the first predetermined byte data for every first predetermined byte of the data, and sending the written data and the check data corresponding thereto to the cache through a system bus.
6. The method of claim 3, further comprising:
responding to the data written into the cache by the memory, and verifying according to the data in the memory and the verification data corresponding to the data;
responding to the verification result that the data and the corresponding verification data are sent to the cache through a system bus;
and sending a memory data error report to the system in response to the verification result being failure.
7. The method of claim 4, further comprising:
responding to the CPU to read data from the cache, and verifying the read data and the corresponding verification data through the CPU;
and sending a system bus error report to an operating system in response to the verification result being failure.
8. The method of claim 4, further comprising:
responding to the memory to read data from the cache, and verifying the data read by the memory and the corresponding verification data through a memory controller of the memory;
and sending a system bus error report to an operating system in response to the verification result being failure.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 8.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
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