CN114296767A - Firmware updating method and system - Google Patents

Abstract

The invention provides a firmware updating method and a firmware updating system, wherein the method is applied to an embedded controller chip, and the embedded controller chip comprises the following steps: the embedded controller chip is in communication connection with the host through a system bus; the method comprises the following steps: acquiring a base address and a default decoding address of a system bus, and obtaining a mapping address according to the base address and the default decoding address; mapping the default decoding port to a host storage device through the mapping address so as to enable the default decoding address and the port address of the host storage device to form a mapping relation, and enabling the host to be in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device; acquiring an update command by monitoring the first memory device; and updating the firmware according to the updating instruction. The invention can improve the efficiency of firmware updating.

Description

Firmware updating method and system

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a firmware updating method and system.

Background

Firmware is a program written in EPROM (erasable programmable read-only memory) or EEPROM (electrically erasable programmable read-only memory). Generally, software which serves as the most basic and bottom layer of a system is called firmware, and flash memory in the system is used as a carrier, and the flash memory and other hardware parts of the system exist at the same time to support the operation of the system.

Some existing firmware is updated under certain platforms, and the firmware can only be updated in an off-line burning mode due to the limitation of ports, so that the time cost for updating the firmware is high, and the firmware updating efficiency is reduced.

Disclosure of Invention

In order to solve the above problems, the firmware updating method and system provided by the present invention map the default decoding port to the host storage device through the mapping address, so that the host sends the related firmware updating command to the embedded controller chip through the mapping address to the default decoding port, and updates the firmware on line, thereby improving the firmware updating efficiency.

In a first aspect, the present invention provides a firmware updating method applied to an embedded controller chip, where the embedded controller chip includes: the embedded controller chip is in communication connection with a host through a system bus;

the method comprises the following steps:

acquiring a base address and the default decoding address of the system bus, and acquiring a mapping address according to the base address and the default decoding address;

mapping the default decoding port to a host storage device through a mapping address so as to enable the default decoding address and the port address of the host storage device to form a mapping relation, wherein the host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device;

acquiring an update command by monitoring the first memory device;

and updating the firmware according to the updating instruction.

Optionally, the embedded controller chip further includes: a target decoding port;

before the fetching of the update command by snooping the first memory device, the method further comprises:

acquiring a target decoding address corresponding to a target decoding port;

and replacing the default decoding address in the mapping address with the target decoding address.

Optionally, the embedded controller chip further includes: a second storage device and a control device;

the obtaining of the update command by snooping the first memory device includes:

and storing the update instruction transmitted by the system bus in a second storage device through the mapping address and the target decoding port, and generating an interrupt to the control device to request the control device to process the update instruction so as to update the firmware.

Optionally, the firmware is stored in a third storage device, and the embedded controller chip further includes: an interface bridge;

before the fetching of the update command by snooping the first memory device, the method further comprises:

acquiring a driving instruction according to the mapping address, and sending the driving instruction to the interface bridge to set up a first flag bit and indicate the interface bridge to take a byte received next time as an updating instruction for updating the firmware;

the updating the firmware according to the update instruction comprises:

and receiving an update instruction after the first flag bit is set, and sending the update instruction to the third storage device through the interface bridge so that the third storage device updates the firmware.

Optionally, the third memory device comprises a plurality of memory cells, each memory cell corresponding to a memory address;

the update instruction includes: control instructions and data instructions;

the data instruction is used for providing a storage address corresponding to a storage unit needing to be operated;

the control instruction is used for providing the content of the operation on the storage unit;

the receiving an update instruction after setting the first flag bit and sending the update instruction to the third storage device through the interface bridge to update the firmware by the third storage device includes:

after the first zone bit is set, receiving data sent by a host to the interface bridge, and forwarding the data received by the interface bridge to the third storage device as a control command;

executing the following steps at least once, receiving a set-up instruction sent by a host to an interface bridge to set up a second flag bit, indicating the interface bridge to use the bytes received at one time or more later as access data, receiving the data sent by the host to the interface bridge after the second flag bit is set up, and using the data received by the interface bridge as the access data;

taking access data as the data instruction;

the data instructions and the control instructions are sent to a third storage device through the interface bridge to cause the third storage device to update the firmware.

In a second aspect, the present invention provides a firmware update system, which is applied to an embedded controller chip, where the embedded controller chip includes: the embedded controller chip is in communication connection with a host through a system bus;

the system comprises:

the first acquisition module is configured to acquire a base address and the default decoding address of the system bus and obtain a mapping address according to the base address and the default decoding address;

the mapping module is configured to map the default decoding port to a host storage device through a mapping address so that the default decoding address and the port address of the host storage device form a mapping relation, and the host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device;

a second obtaining module configured to obtain the update instruction by listening to the first storage device;

and the updating module is configured to update the firmware according to the updating instruction.

Optionally, the embedded controller chip further includes: a target decoding port;

the system further comprises:

the third acquisition module is configured to acquire a target decoding address corresponding to the target decoding port before the update instruction is acquired by monitoring the first storage device;

a first replacement module configured to replace a default decoded address in the mapped addresses with a target decoded address.

Optionally, the embedded controller chip further includes: a second storage device and a control device;

the second obtaining module is further configured to store the update instruction transmitted by the system bus in the second storage device through the mapped address and the target decoding port, and generate an interrupt to the control device to request the control device to process the update instruction to update the firmware.

Optionally, the firmware is stored in a third storage device, and the embedded controller chip further includes: an interface bridge;

the system further comprises:

the first setting module is configured to acquire a driving instruction according to a mapping address before the updating instruction is acquired by monitoring the first storage device, and send the driving instruction to the interface bridge to set a first flag bit to indicate the interface bridge to use a byte received next time as an updating instruction for updating the firmware;

the update module is further configured to receive an update instruction after the first flag bit is set, and send the update instruction to the third storage device through the interface bridge, so that the third storage device updates the firmware.

Optionally, the third memory device comprises a plurality of memory cells, each memory cell corresponding to a memory address;

the update instruction includes: control instructions and data instructions;

the data instruction is used for providing a storage address corresponding to a storage unit needing to be operated;

the control instruction is used for providing the content of the operation on the storage unit;

the update module includes:

the forwarding submodule is configured to receive data sent by a host to the interface bridge after the first flag bit is set, and forward the data received by the interface bridge to the third storage device as a control instruction;

the second setting submodule is configured to receive a setting instruction sent by the host to the interface bridge, set a second flag bit and indicate the interface bridge to use the bytes received one or more times later as access data;

the receiving submodule is configured to receive data sent by a host to the interface bridge after the second mark position starts, and take the data received by the interface bridge as the access data;

an instruction integration submodule configured to take access data as the data instruction;

a sending submodule configured to send the data command and the control command to a third storage device through the interface bridge to cause the third storage device to update the firmware.

According to the firmware updating method and system provided by the embodiment of the invention, the base address and the default decoding address form the mapping address, the default decoding port is mapped to the host storage device through the mapping address, and the default decoding address in the mapping address is replaced by the target decoding address, so that the host can send the related firmware updating instruction to the embedded controller chip through the target decoding port, the firmware can be updated online, and the firmware updating efficiency is improved.

Drawings

Fig. 1 is an internal structure diagram of an embedded controller chip according to an embodiment of the present application;

FIG. 2 is a schematic flow chart diagram of a firmware update method according to an embodiment of the present application;

FIG. 3 is a timing diagram illustrating a method for reading Flash data according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a firmware update system according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

First, the proper nouns to which the present invention relates will be explained.

EC: an embedded controller, i.e., an embedded controller chip;

PMC: and the power management channel module is used for a communication module between the HOST (HOST computer) and the EC.

Flash: a non-volatile memory.

SMFI: a Flash interface bridge of a shared memory provides a method for a host to access Flash.

8032 controller: and the controller inside the embedded controller chip is used for processing programs and instructions.

Scratch SRAM: and the SRAM (static random access memory) of the external equipment of the embedded controller chip is used for storing an interface operation function (FlashECCode SPI).

0x62/0x66 port: and the EC is at the peripheral IO port corresponding to the HOST end.

And (3) address mapping: the logical addresses in the user program are converted into physical addresses directly addressed by a machine during operation, namely the process of mapping the addresses, so that the corresponding storage units can be correctly accessed when the processor executes the instructions.

LPC Bus: the LPC bus, i.e., the system bus, is used to connect the embedded controller chip with the bus of the host.

M Bus: namely SPI Bus, and a serial peripheral interface Bus for connecting SMFI and Flash.

In a first aspect, the present invention provides a firmware updating method applied to an embedded controller chip. With reference to fig. 1, the embedded controller chip includes: the embedded controller chip is in communication connection with a host through a system bus. Wherein, LPC bus hangs the IO port, and the IO port is the address that the host computer acquiescence allocated to the EC of hanging on LPC bus, and the IO port includes: default and target decoding ports, e.g., 0x62 port, 0x66 port, 0x22 port, and 0x26 port, etc.; the PMC is in communication connection with the SMFI and 8032 controller through an I Bus (Internal Bus) and is used for monitoring addresses and data on the LPC Bus; 8032 the controller is connected with the Scratch SRAM through EC BUS (embedded controller BUS) communication; and the SMFI is in communication connection with the Flash through the SPI Bus.

In the embodiment, the method is applied to an embedded controller chip under an ARM platform Linux system; the system bus is a public data channel for information transmission between the host and the embedded controller chip; a host storage device is arranged in the host, and in the embodiment, the host storage device is a host memory; the firmware is EC firmware and is stored in Flash, namely a third storage device; 8032 the controller is a control device; the first storage device is a register pair of IOBAD0/IOBAD1 arranged inside the embedded controller; default decoding ports are 0x62 port and 0x66 port; the target decoding ports are 0x22 ports and 0x26 ports.

With reference to fig. 2, the method includes steps S101 to S104:

step S101: and acquiring a base address and the default decoding address of the system bus, and acquiring a mapping address according to the base address and the default decoding address.

Step S102: and mapping the default decoding port to a host storage device through a mapping address so as to enable the default decoding address and the port address of the host storage device to form a mapping relation, wherein the host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device.

Under the ARM architecture, host IO access to the 0x62/0x66 ports is not supported, so before the host accesses the two ports, the control device maps the two ports to the memory of the host, and the host indirectly accesses the two ports of 0x62/0x66 by accessing the memory of the host. Taking the FT CPU as an example, the mapping address is the bus address (e.g. LPC bus base address is 0x80000000) + offset. The offset corresponds to a conventional port number, the offset of the port 0x62 is 0x62, and the offset of the port 0x66 is 0x66, so the memory addresses corresponding to the two ports, i.e., the mapping addresses are 0x80000062 and 0x80000066, and the port 0x62/0x66 can be accessed by accessing the two memory addresses.

Step S103: the update command is obtained by snooping the first memory device.

The step S103 is implemented as follows: and monitoring the address and data on the LPC bus by the PMC in the EC, and when the address is 0x62/0x66, taking the data on the LPC bus by the EC and storing the data into a register PMDIR inside the PMC. And then the 8032 controller takes out data from the PMDIR of the PMC through the internal bus and stores the data into a corresponding register in the SMFI according to the data.

In an optional embodiment, the embedded controller chip further includes: a second memory device. In this alternative embodiment, the second memory device is an input register PMDIR.

The obtaining of the update command by snooping the first memory device includes: and storing the update instruction transmitted by the system bus in a second storage device through the mapping address and the target decoding port, and generating an interrupt to the control device to request the control device to process the update instruction so as to update the firmware.

Step S104: and updating the firmware according to the updating instruction.

Specifically, the PMC is hung on an LPC bus to serve as a main bridge for communication between an embedded controller chip and a host, and the host changes a decoding port of the PMC through a register pair of IOBAD0/IOBAD 1. When decoding addresses on the LPC bus are 0x62 and 0x66, the PMC stores data on the LPC bus into an input register PMDIR inside the EC in a data clock period section, generates an interrupt to an 8032 controller, and requests the 8032 controller to process input data, wherein the input data include an updating instruction for acquiring system bus transmission according to the mapping address.

The default decoding port is mapped to the host storage device through the mapping address, specifically, the host indirectly accesses the IO port of the EC through a mode of accessing a bus address + an offset address, and therefore interaction between the host and the relevant register of the EC is achieved. And finally, realizing the function of operating Flash by operating a register provided by SMFI in the EC to finish updating the firmware. In this embodiment, the IO port of the embedded controller chip is mapped to the Memory of the host through an MMIO (Memory-mapped I/O) mode.

In an alternative embodiment, prior to the fetching of the update command by snooping the first memory device, the method further comprises: acquiring a target decoding address corresponding to a target decoding port; and replacing the default decoding address in the mapping address with the target decoding address.

Before updating the firmware in the Flash, the program fills 0x22 into the IOBAD0 register of the EC, and fills 0x26 into the IOBAD1, namely, the mapping addresses 0x80000062 and 0x80000066 are modified into 0x80000022 and 0x80000026, so that the decoding ports of the EC are changed from 0x62 and 0x66 into 0x22 and 0x26, and thus the updating tool adopts the 0x22 port and the 0x26 port for data transmission, so that the problem of port communication conflict when the default decoding port is occupied can be avoided, and the firmware updating failure is caused.

In an optional embodiment, the embedded controller chip further includes: an interface bridge. In this alternative embodiment, the interface bridge is the SMFI.

Before fetching the update command by snooping the first memory device, the method further comprises: and acquiring a driving instruction according to the mapping address, and sending the driving instruction to the interface bridge to set up a first flag bit and indicate the interface bridge to take the next received byte as an updating instruction for updating the firmware.

The updating the firmware according to the update instruction comprises: and receiving an update instruction after the first flag bit is set, and sending the update instruction to the third storage device through the interface bridge so that the third storage device updates the firmware.

In this alternative embodiment, the smfi (share memory Flash Interface bridge) provides 5 registers to support the EC side to access the SPI Interface of Flash. The 5 registers include: EC-INDIRECT Memory Address Registers (ECINDAR3-0, 4 Registers) and EC-INDIRECT Memory Data Registers (ECINDDDR). Wherein ECINDAR3-0 is used as a control register for accessing Flash, and ECINDDR is used as a data register for accessing Flash. The EC end can directly read and write ECINDAR3-0 and ECINDDDR registers through the Internal BUS, control the chip selection signal of Flash through reading and writing 4 registers of ECINDAR3-0 and carry out data transmission with the Flash through reading and writing the ECINDDR registers.

In an alternative embodiment, the driving instructions include: the chip selection circuit comprises a first chip selection driving instruction and a second chip selection driving instruction, wherein the first chip selection driving instruction is used for driving a high chip selection signal, and the second chip selection driving instruction is used for driving a low chip selection signal.

In this optional embodiment, when the host sends the first chip select driving instruction to the interface bridge through the corresponding decoding port, the interface bridge drives the chip select signal high; and then when the host sends the second chip selection driving instruction to the interface bridge through the corresponding decoding port, the interface bridge drives the chip selection signal low. When the chip select signal changes from high to low, that is, the host starts data transmission with the third storage device through the embedded controller chip, the first flag bit is set, and the first flag bit is set to indicate the interface bridge to use the byte received next time through the corresponding decoding port as an update instruction for updating the firmware.

In the optional embodiment, the condition for starting data transmission is set through the first chip selection driving instruction and the second chip selection driving instruction, and the data can be started to be transmitted by marking the data with the first flag bit, so that the data can be stably and orderly transmitted, and the stability of firmware updating is improved.

In an alternative embodiment, the third memory device includes a plurality of memory cells, each memory cell corresponding to a memory address. The update instruction includes: control instructions and data instructions. The data instruction is used for providing a storage address corresponding to a storage unit needing to be operated; the control instructions are used for providing content of the operation on the storage unit. In accordance with the last alternative embodiment, the ECINDAR3-0 register is used to store control instructions; the ECINDDR register is used to store data instructions.

The receiving an update instruction after setting the first flag bit and sending the update instruction to the third storage device through the interface bridge to update the firmware by the third storage device includes:

step a: after the first zone bit is set, receiving data sent by a host to the interface bridge, and forwarding the data received by the interface bridge to the third storage device as a control command;

step b: performing steps b1 to b2 at least once, step b 1: receiving a set-up instruction sent by a host to an interface bridge to set up a second flag bit and indicate the interface bridge to use the bytes received for one or more times later as access data; step b 2: after the second mark position is started, receiving data sent by a host to the interface bridge, and taking the data received by the interface bridge as the access data;

step c: taking access data as the data instruction;

step d: the data instructions and the control instructions are sent to a third storage device through the interface bridge to cause the third storage device to update the firmware.

In this alternative embodiment, the data instruction consists of three bytes and, when the second flag is set, instructs the interface bridge to take as access data the next byte or bytes received. In this case, step b is executed repeatedly three times from step b1 to step b2, so that the access data obtained by the respective three times is used as a data command to update the firmware in the third storage device.

If the data command consists of one byte, step b is performed by repeating steps b1 through b2 once. If the second flag bit is set to indicate that the interface bridge uses the byte received at the specified number of times as the access data before clearing the second flag bit, then step b1 can be executed once, and step b2 needs to be executed for the specified number of times, which in this embodiment may be determined by the number of bytes actually occupied by the data instruction, and in this embodiment, the specified number is not specifically limited.

In the optional embodiment, the firmware is updated by dividing the update instruction into the control instruction and the data instruction, so that the stability of firmware update can be further ensured, and meanwhile, the integrity of the data instruction can be ensured by setting the second flag bit, and the firmware update can be smoothly performed.

In an alternative embodiment, the step a may be performed after modulating the step b or the step c, and is not specifically described in this alternative embodiment.

In an optional embodiment, the method further comprises: and after the firmware is updated by the third storage device, replacing the target decoding address in the mapping address with the default decoding address. After the firmware is updated by the third storage device, the target decoding address in the mapping address is replaced by the default decoding address, so that the host can continue to communicate with the embedded controller chip through the default decoding port after the firmware in the third storage device is updated.

In a second aspect, the present embodiment provides an EC firmware updating method, which is applied to the embedded controller chip.

The host sends 0xDC to the EC, the EC is indicated to enter an SPI interface operation function FlashECCode through a Scratch SRAM, the EC enters the operation function FlashECCode and responds to the host end 0x33 after receiving 0xDC, the host end sends 0x01 to the EC after receiving 0x33, and the EC enters a Follow mode after receiving 0x01, so that the SMFI operates the Flash. The host then sends a set of commands to the 0x22 port of the EC in turn. The EC end circularly reads the command sent from the host end in the input register PMDIR in the FlashECCode function, the command received circularly for two times is used as a group of Flash operation, the data received for the first time is used as the EC command, and the EC internal code can analyze and respond to the command according to a corresponding command table, such as the first table; the Data received for the second time is used as a Flash operation command and is respectively written into an EC-index Memory Address Registers (ECINDAR3-0) register and an EC-index Memory Data Registers (ECINDDDR) register of the SMFI and is simultaneously forwarded to Flash. And after receiving the forwarded command, the Flash analyzes and responds according to the second table. After the host operates Flash, the host sends 0x05 to the EC end, which instructs the EC to exit from Follow mode. After exiting the Follow mode, the host end finally sends 0xFC to the EC end, indicating that the EC exits the FlashECode function. And at this point, after the Flash is updated, restarting the EC chip.

In this embodiment, taking reading one byte data of Flash as an example, the specific process is as follows:

the host sends 0xDC to the EC indicating that the EC enters the SPI interface operation function FlashECCode.

After receiving 0xDC, the EC enters the operation function FlashECode and responds to the host 0x 33.

The host side sends 0x01 to the EC side after receiving 0x33, after the EC side receives 0x01, the EC side writes 0x0FFF _ FExx to ECINDAR3-0 according to the content of table one, and drives a chip selection signal CS # high, wherein the chip selection signal CS # is a chip selection signal of Flash.

The HOST end sends 0x02 to the EC end, and after the EC end receives 0x02, the EC end writes 0x0FFF _ FExx into ECINDAR3-0 by the content of table one to drive the Flash chip selection signal CS # low. Thus, the chip select signal CS # goes from high to low to indicate that a data transfer can be started, and the first flag bit is set to indicate that the next byte received is to be used as a Flash command.

And the HOST end sends 0x03 to the EC end, and after the EC end receives 0x03, the EC end writes 0x03 into an ECINDDR register according to the content of the table two, forwards the ECINDDR register as an instruction to Flash, and clears the first flag bit. In FIG. 3, the bits of the CLK clock lines 0-7 correspond to DI line data 03 h.

And the HOST end sends 0x03 to the EC end, and after the EC end receives 0x03, the EC end sets a flag bit according to the content of the table I and indicates that the byte received next time is used as Flash data.

The HOST end sends high bytes of Flash addresses (3-byte data) needing to be accessed to the EC end, after the EC end receives the high bytes, the high bytes are written into an ECINDDR register and forwarded to the Flash, and the high bytes of the Flash addresses are 23-16 bits of data corresponding to 8-15 bits of CLK clock lines in the picture 3.

And repeating the two steps twice, writing the rest two byte addresses of the Flash address into ECINDDR in sequence, and sending the ECINDDR to the Flash, wherein the rest two byte addresses are 15-0 bit data of the DI line corresponding to 16-31 bit of the CLK clock line in the picture 3.

After receiving the 0x03 and the three-byte address in the second read instruction table, the Flash sends the data in the corresponding address to the ECINDDR of the EC end, and waits for HOST reading, wherein the data in the corresponding address is 15-0 bit data of a DO line corresponding to 32-39 bits of a CLK clock line in FIG. 3.

The HOST end sends 0x04 in the table I to the EC end, and after the EC end receives 0x04, the data in ECINDDR is written into the PMDOR register. After the data is stored in the PMDOR register, the OBF flag in the PMSTR register is set.

And after the HOST end reads the OBF position of the PMSTR register, reading the data in the PMDOR register and clearing the OBF zone bit. And finishing the operation of reading the Flash data once.

Watch 1

Watch two

FLASH instruction meaning	Flash instruction
		Writing state	0x01
Page programming	0x02
		Reading data	0x03
Write inhibit	0x04
		Read status	0x05
Write enable	0x06
		Fast reading	0x0B
Write state enable	0x50
		JEDEC ID	0x9F
Sector/block erase	0x20,0x52,0xD7,0xD8
		Debug instruction	0x86,0x87

Wherein, the command modes of operating the SPI interface are as follows: and the EC command + SPI interface operation command indicates a command response table for interaction between the EC and the host computer in the burning mode. Table 2.2 is the SPI interface operating instruction table.

The EC firmware updating method improves the EC burning mode under the ARM64 platform in the industry, and improves the EC developing and testing efficiency of testers.

In a third aspect, with reference to fig. 4, this embodiment provides a firmware update system 300, which is applied to an embedded controller chip in the foregoing method, where the firmware update system 300 includes:

a first obtaining module 301, configured to obtain a base address of the system bus and the default decoding address, and obtain a mapping address according to the base address and the default decoding address;

the mapping module 302 is configured to map the default decoding port to a host storage device through a mapping address, so that the default decoding address forms a mapping relation with the port address of the host storage device, and a host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device;

a second obtaining module 303 configured to obtain the update instruction by snooping the first storage device;

an update module 304 configured to update the firmware according to the update instruction.

In an alternative embodiment, the firmware update system 300 further comprises:

the third acquisition module is configured to acquire a target decoding address corresponding to the target decoding port before the update instruction is acquired by monitoring the first storage device;

a first replacement module configured to replace a default decoded address in the mapped addresses with a target decoded address.

In an optional embodiment, the embedded controller chip further includes: a second storage device and a control device;

the second obtaining module 303 is further configured to store the update instruction transmitted by the system bus in the second storage device through the mapped address and the target decoding port, and generate an interrupt to the control device to request the control device to process the update instruction to update the firmware.

In an alternative embodiment, the firmware is stored in a third memory device, and the embedded controller chip further comprises: an interface bridge;

the firmware update system 300 further comprises:

the first setting module is configured to acquire a driving instruction according to a mapping address before the updating instruction is acquired by monitoring the first storage device, and send the driving instruction to the interface bridge to set a first flag bit to indicate the interface bridge to use a byte received next time as an updating instruction for updating the firmware;

the update module 304 is further configured to receive an update command after setting the first flag bit, and send the update command to the third storage device through the interface bridge, so that the third storage device updates the firmware.

In an alternative embodiment, the third memory device includes a plurality of memory cells, each memory cell corresponding to a memory address;

the update instruction includes: control instructions and data instructions;

the data instruction is used for providing a storage address corresponding to a storage unit needing to be operated;

the control instruction is used for providing the content of the operation on the storage unit;

the update module 304 includes:

the forwarding submodule is configured to receive data sent by a host to the interface bridge after the first flag bit is set, and forward the data received by the interface bridge to the third storage device as a control instruction;

the second setting submodule is configured to receive a setting instruction sent by the host to the interface bridge, set a second flag bit and indicate the interface bridge to use the bytes received one or more times later as access data;

the receiving submodule is configured to receive data sent by a host to the interface bridge after the second mark position starts, and take the data received by the interface bridge as the access data;

an instruction integration submodule configured to take access data as the data instruction;

a sending submodule configured to send the data command and the control command to a third storage device through the interface bridge to cause the third storage device to update the firmware.

In an alternative embodiment, the firmware update system 300 further comprises:

and the second replacement module is configured to replace the target decoding address in the mapping address with the default decoding address after the third storage device finishes updating the firmware.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A firmware updating method is applied to an embedded controller chip, and the embedded controller chip comprises the following steps: the embedded controller chip is in communication connection with a host through a system bus;

the method comprises the following steps:

acquiring a base address and the default decoding address of the system bus, and acquiring a mapping address according to the base address and the default decoding address;

mapping the default decoding port to a host storage device through a mapping address so as to enable the default decoding address and the port address of the host storage device to form a mapping relation, wherein the host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device;

acquiring an update command by monitoring the first memory device;

and updating the firmware according to the updating instruction.

2. The firmware updating method according to claim 1, wherein the embedded controller chip further comprises: a target decoding port;

before the fetching of the update command by snooping the first memory device, the method further comprises:

acquiring a target decoding address corresponding to a target decoding port;

and replacing the default decoding address in the mapping address with the target decoding address.

3. The firmware update method according to claim 2, wherein the embedded controller chip further comprises: a second storage device and a control device;

the obtaining of the update command by snooping the first memory device includes:

and storing the update instruction transmitted by the system bus in a second storage device through the mapping address and the target decoding port, and generating an interrupt to the control device to request the control device to process the update instruction so as to update the firmware.

4. The firmware updating method according to claim 2, wherein the firmware is stored in a third storage device, the embedded controller chip further comprising: an interface bridge;

before the fetching of the update command by snooping the first memory device, the method further comprises:

acquiring a driving instruction according to the mapping address, and sending the driving instruction to the interface bridge to set up a first flag bit and indicate the interface bridge to take a byte received next time as an updating instruction for updating the firmware;

the updating the firmware according to the update instruction comprises:

and receiving an update instruction after the first flag bit is set, and sending the update instruction to the third storage device through the interface bridge so that the third storage device updates the firmware.

5. The firmware updating method according to claim 4, wherein the third storage device comprises a plurality of storage locations, each storage location corresponding to a storage address;

the update instruction includes: control instructions and data instructions;

the data instruction is used for providing a storage address corresponding to a storage unit needing to be operated;

the control instruction is used for providing the content of the operation on the storage unit;

the receiving an update instruction after setting the first flag bit and sending the update instruction to the third storage device through the interface bridge to update the firmware by the third storage device includes:

after the first zone bit is set, receiving data sent by a host to the interface bridge, and forwarding the data received by the interface bridge to the third storage device as a control command;

executing the following steps at least once, receiving a set-up instruction sent by a host to an interface bridge to set up a second flag bit, indicating the interface bridge to use the bytes received at one time or more later as access data, receiving the data sent by the host to the interface bridge after the second flag bit is set up, and using the data received by the interface bridge as the access data;

taking access data as the data instruction;

the data instructions and the control instructions are sent to a third storage device through the interface bridge to cause the third storage device to update the firmware.

6. A firmware update system is applied to an embedded controller chip, and the embedded controller chip comprises: the embedded controller chip is in communication connection with a host through a system bus;

the system comprises:

the first acquisition module is configured to acquire a base address and the default decoding address of the system bus and obtain a mapping address according to the base address and the default decoding address;

the mapping module is configured to map the default decoding port to a host storage device through a mapping address so that the default decoding address and the port address of the host storage device form a mapping relation, and the host is in communication connection with the default decoding port corresponding to the default decoding address through the mapping address stored in the host storage device;

a second obtaining module configured to obtain the update instruction by listening to the first storage device;

and the updating module is configured to update the firmware according to the updating instruction.

7. The firmware update system of claim 6, wherein the embedded controller chip further comprises: a target decoding port;

the system further comprises:

the third acquisition module is configured to acquire a target decoding address corresponding to the target decoding port before the update instruction is acquired by monitoring the first storage device;

a first replacement module configured to replace a default decoded address in the mapped addresses with a target decoded address.

8. The firmware update system of claim 7, wherein the embedded controller chip further comprises: a second storage device and a control device;

the second obtaining module is further configured to store the update instruction transmitted by the system bus in the second storage device through the mapped address and the target decoding port, and generate an interrupt to the control device to request the control device to process the update instruction to update the firmware.

9. The firmware update system of claim 7, wherein the firmware is stored in a third storage device, the embedded controller chip further comprising: an interface bridge;

the system further comprises:

the first setting module is configured to acquire a driving instruction according to a mapping address before the updating instruction is acquired by monitoring the first storage device, and send the driving instruction to the interface bridge to set a first flag bit to indicate the interface bridge to use a byte received next time as an updating instruction for updating the firmware;

the update module is further configured to receive an update instruction after the first flag bit is set, and send the update instruction to the third storage device through the interface bridge, so that the third storage device updates the firmware.

10. The firmware update system of claim 9, wherein the third storage device comprises a plurality of storage locations, each storage location corresponding to a storage address;

the update instruction includes: control instructions and data instructions;

the data instruction is used for providing a storage address corresponding to a storage unit needing to be operated;

the control instruction is used for providing the content of the operation on the storage unit;

the update module includes:

the forwarding submodule is configured to receive data sent by a host to the interface bridge after the first flag bit is set, and forward the data received by the interface bridge to the third storage device as a control instruction;

the second setting submodule is configured to receive a setting instruction sent by the host to the interface bridge, set a second flag bit and indicate the interface bridge to use the bytes received one or more times later as access data;

the receiving submodule is configured to receive data sent by a host to the interface bridge after the second mark position starts, and take the data received by the interface bridge as the access data;

an instruction integration submodule configured to take access data as the data instruction;

a sending submodule configured to send the data command and the control command to a third storage device through the interface bridge to cause the third storage device to update the firmware.

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