CN102122269B - Writing timeout control method of flash memory and memory device thereof - Google Patents

Writing timeout control method of flash memory and memory device thereof Download PDF

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Publication number
CN102122269B
CN102122269B CN201010004561A CN201010004561A CN102122269B CN 102122269 B CN102122269 B CN 102122269B CN 201010004561 A CN201010004561 A CN 201010004561A CN 201010004561 A CN201010004561 A CN 201010004561A CN 102122269 B CN102122269 B CN 102122269B
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block
female
data
blocks
target
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CN102122269A (en
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梁嘉旂
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Silicon Motion Inc
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Silicon Motion Inc
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Abstract

The invention relates to a writing timeout control method of a flash memory. The flash memory comprises a plurality of standby blocks and a data block, wherein the data block is provided with a plurality of mother blocks. The writing timeout control method comprises the steps of: receiving a writing command and an initial logical block address; determining an updating mode according to a target mother block interlinked with the initial logical block address; judging whether a first mother block is pre-cleaned; if yes, post-cleaning the first mother block in a first time period; resetting the first mother block as a stand block; writing a data programming procedure for the execution of the target mother block; judging whether the number of the mother blocks exceeds a first critical value; pre-cleaning a second mother block in a second time period when the number of mother blocks exceeds the first critical value; and marking the first mother block and the second mother block as blocks to be cleaned. The invention also relates to a memory device. The writing timeout control method and the memory device, provided by the invention, can solve the problem of writing timeout of the flash memory, and further can improve the overall access effect of the memory device.

Description

Flash memory write overtime control method and memory storage thereof
Technical field
The present invention relates to flash memory (flash memory) correlative technology field, more particularly, relate to a kind of be applicable to flash memory write overtime (write timeout) control method and memory storage thereof.
Background technology
Flash memory is a kind of non-loss property internal memory; Need not rely on electric power and can keep its stored data; Size is little, height is remembered density, low power consumption reaches advantage cheaply owing to have, and therefore is widely used in the various consumption electronic products such as mobile phone, digital camera, PDA(Personal Digital Assistant).
Flash memory generally includes a plurality of blocks (block), and each block has the plural page (page) in order to storage data.Further, flash memory is that unit carries out data programing (program) with the page, and is that unit carries out data erase (erase) with the block.In other words, when flash memory carries out data when erasing to a block, the stored data of all pages of this block all can be erased together.
In addition, each page of flash memory only allows to be programmed once.When the stored data of the partial page of a block need be upgraded,, and can't directly be programmed in these pages Updating Information because these pages have had legacy data.That is to say, if desire is upgraded these pages, this block of must erasing earlier, what can Update Information writing or programming.This extra erasing and programming operation again except causing the delay of execution time, also can produce the odd word burden, causes the decline of whole access usefulness.
Moreover, be the trend that cooperates the flash memory memory capacity to increase, can increase the page quantity of each block; For example: increase to 256 pages from 128 pages; Perhaps increase the memory capacity of each page, for example: (bytes) increases to the 8K byte from the 4K byte, uses so that flash memory possesses bigger memory capacity.Yet this is also meaning to Update Information and is more erasing and programme the time expending, even causes surpassing the busy record time of programming that the flash memory specification is allowed, for example: 250 milliseconds (millisecond, ms).Generally speaking, the block of 128 pages needs 200 milliseconds to accomplish erase operation for use.Therefore, need 400 milliseconds of ability to accomplish the block erase operation for use of 256 pages, add the time of programming again that Updates Information, just can write the situation of overtime, cause whole access usefulness seriously to descend.
Therefore, need a kind of be applicable to flash memory write the overtime control method, in programming data or when Updating Information, can avoid writing overtime, thereby promote the whole access usefulness of flash memory.
Summary of the invention
The technical matters that the present invention will solve is, to the above-mentioned defective of prior art, provide a kind of be used for flash memory write overtime control method and memory storage thereof.
One of the technical solution adopted for the present invention to solve the technical problems is: that constructs a kind of flash memory writes the overtime control method, and this flash memory comprises a plurality of block and a plurality of spare blocks, and further, these block comprise a plurality of female blocks.This method comprises: the write command and the corresponding initial logical block addresses that receive a main frame; According to the female block of a target that this initial logical block addresses linked, in order to determine a new model more; Judge one first female block whether operate by executed one pre cleaning, and wherein, this first female block is marked as a block to be removed; When this pre cleaning operation of this first female block executed,, carry out a back clear operation of this first female block in the cycle very first time; This first female block is reset to a spare blocks; According to this new model more, on the female block of this target that this initial logical block addresses linked, carry out and write the data programing program corresponding to one of this write command; Whether the quantity of judging these female blocks surpasses one first critical value; And when the quantity of these female blocks surpasses this first critical value,, carry out this pre cleaning operation of one second female block in one second time cycle, wherein, this second female block is marked as this block to be removed.
Of the present invention be used for flash memory write the overtime control method, wherein, after receiving this initial logical block addresses, more comprise:
Receive in regular turn in order to represent that this writes a series of data cell of data.
Of the present invention be used for flash memory write the overtime control method, wherein, after receiving this a series of data cell, more comprise:
Reception one stops to transmit order by what this main frame sent, in order to expression to should write command this write data and transmitted completion.
Of the present invention be used for flash memory write the overtime control method, wherein, this cycle very first time is in order to after representing that one first data cell receives, to the preceding a period of time that receives one second data cell.
Of the present invention be used for flash memory write the overtime control method, wherein, after this second time cycle should set order receives in order to expression, to time order a period of time before that receives main frame.
Of the present invention be used for flash memory write the overtime control method, more comprise:
When this first female block is not carried out this pre cleaning operation as yet,, carry out this pre cleaning operation of this first female block in this cycle very first time; And
In one the 3rd time cycle, carry out this back clear operation of this first female block,
Wherein, the 3rd time cycle and before this second time cycle, received an interval time of two continuous data unit in order to expression after this cycle very first time.
Of the present invention be used for flash memory write the overtime control method, wherein, these block more comprise a plurality of update blocks, each update blocks has one or more in order to upgrade the renewal page of a corresponding female block.
Of the present invention be used for flash memory write the overtime control method, wherein, the step of this pre cleaning operation and this back clear operation comprises:
This that obtain that this waits to remove block be new model more;
When this was waited to remove this of block more new model is a sub-block pattern, this waited to remove in the pairing update blocks of block certainly, seeks a final updating page;
According to this final updating page, this waits to remove in the block certainly, with the data-moving behind this final updating page to this update blocks; And
This block to be removed of erasing.
Of the present invention be used for flash memory write the overtime control method, wherein, the step of this pre cleaning operation and this back clear operation comprises:
This that obtain that this waits to remove block be new model more;
When this is waited to remove this of block more new model is a FAT block mode, obtain a set spare blocks;
Wait to remove in the pairing update blocks of block from this, read a look-up table, this look-up table record this one or more upgrades the page and waits to remove the corresponding renewal position of block with this;
According to this look-up table, with this wait to remove the stored data of block and this one or more upgrade the stored data of the page and integrate, integrate and write data in order to obtain one;
This integration is write data programing to this set spare blocks; And
Erasing, this waits to remove block and this update blocks.
Of the present invention be used for flash memory write the overtime control method, more comprise:
When the quantity of these female blocks surpassed this first critical value, whether this that judge the female block of this target more new model was a FAT block mode;
When this of the female block of this target when more new model is this FAT block mode, obtain the data length that this writes data;
According to this initial logical block addresses and this data length, in order to calculate the pairing update blocks of the female block of this target, the end logical block addresses after carrying out this to write the data programing program;
Finish the size of logical block addresses and this update blocks according to this, in order to obtain a free Page quantity of this update blocks;
Judge that whether this free Page quantity is less than one second critical value;
When this free Page quantity during, the female block of this target is labeled as this block to be removed less than this second critical value; And
In this second time cycle, carry out this pre cleaning operation of the female block of this target.
Two of the technical solution adopted for the present invention to solve the technical problems is: construct a kind of memory storage, be coupled to a main frame, and comprise a flash memory and a controller.This flash memory comprises a flash memory, comprises a plurality of block and a plurality of spare blocks, and wherein, these block comprise a plurality of female blocks.This controller is coupled to this flash memory; In order to the write command that receives this main frame and a corresponding initial logical block addresses, according to the female block determining one of the target that this initial logical block addresses linked more new model, judge be marked as one wait to remove the whether executed one pre cleaning operation of one first female block of block, when this pre cleaning of this first female block executed is operated; In the cycle very first time carry out this first female block a back clear operation, with this first female block reset to a spare blocks, according to this new model more; In carry out on this initial logical block addresses linked the female block of this target corresponding to one of this write command write the data programing program, whether the quantity of judging these female blocks surpasses one first critical value and when the quantity of these female blocks during above this first critical value; In one second time cycle, to being marked as this pre cleaning operation of one second female onblock executing that this waits to remove block.
Memory storage of the present invention, wherein, this controller receives in order to represent that this writes a series of data cell of data after receiving this initial logical block addresses in regular turn.
Memory storage of the present invention wherein, after this controller receives this a series of data cell, receives by what this main frame sent and one stops to transmit order, in order to represent to should write command this write data and transmitted completion.
Memory storage of the present invention, wherein, this cycle very first time is in order to after representing that one first data cell receives, to the preceding a period of time that receives one second data cell.
Memory storage of the present invention, wherein, this second time cycle is ordered a period of time before in order to after representing this set order reception to inferior one of reception main frame.
Memory storage of the present invention; Wherein, when this first female block was not carried out this pre cleaning operation as yet, this controller was carried out this pre cleaning operation of this first female block in this cycle very first time; And in this back clear operation of this first female block of one the 3rd time cycle execution
Wherein, the 3rd time cycle and before this second time cycle, received an interval time of two continuous data unit in order to expression after this cycle very first time.
Memory storage of the present invention, wherein, these block more comprise a plurality of update blocks, and each update blocks has one or more in order to upgrade the renewal page of a corresponding female block.
Memory storage of the present invention; Wherein, This controller obtain that this waits to remove block this more new model, when this is waited to remove this of block more new model is a sub-block pattern; Wait to remove in pairing this update blocks of block from this and to seek a final updating page, according to this final updating page, this waits to remove in the block with data-moving to this update blocks and this block to be removed of erasing after this final updating page, in order to carry out this pre cleaning operation and this back clear operation certainly.
Memory storage of the present invention; Wherein, This controller obtain that this waits to remove block this more new model, when this is waited to remove this of block more new model is a FAT block mode; Obtain a set spare blocks, this waits to remove in the pairing update blocks of block certainly; Read a look-up table, this look-up table this one or more upgrade the page with this wait to remove block corresponding renewal position, table look-up according to this, this is waited to remove the stored data of block and this one or more stored data of renewal page are integrated; Integrate and to write data, this integration is write data programing to this set spare blocks and erases that this waits to remove block and this update blocks in order to obtain one, reach this back clear operation in order to carry out this pre cleaning operation.
Memory storage of the present invention; Wherein, When the quantity of these female blocks does not surpass this first critical value; This controller judge the female block of this target this more new model whether be a FAT block mode, when this of the female block of this target when more new model is for this FAT block mode; Obtain this data length that writes data, this initial logical block addresses of basis and this data length; In order to calculating the pairing update blocks of the female block of this target, after carrying out this to write the data programing program one finish logical block addresses, according to the size of this end logical block addresses and this update blocks, obtain this update blocks a free Page quantity, judge this free Page quantity whether less than one second critical value, when this free Page quantity during less than this second critical value; The female block of this target is labeled as this block to be removed and in this second time cycle, carries out this pre cleaning operation of the female block of this target.
Embodiment of the present invention be used for flash memory write overtime control method and memory storage thereof; Have following beneficial effect: controller receives from main frame and writes in the process of data; Perhaps; From main frame receive stop to transmit order after in the latent period before receive a time order, can the integrated operation of pairing block group be divided in regular turn the pre cleaning operation and after clear operation.Therefore, each order the term of execution, controller can integrate simultaneously one or many assembly to the block group, in order to save pairing block group spent time when integrating, can solve the problem that writes overtime, thereby promote the whole access usefulness of memory storage.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
Fig. 1 is the memory storage calcspar of the embodiment of the invention;
Fig. 2 is the synoptic diagram of a female block of a target of the embodiment of the invention and a update blocks;
Fig. 3 be the embodiment of the invention be used for flash memory write overtime control method process flow diagram;
Fig. 4 is the write command of the embodiment of the invention, corresponding initial logical block addresses, and data cell sequential chart;
Fig. 5 is the synoptic diagram of the female block of a target and a update blocks in the sub-block pattern of another embodiment of the present invention;
Fig. 6 is the synoptic diagram of the female block of a target and a update blocks in the FAT block mode of another embodiment of the present invention.
[primary clustering symbol description]
10～memory storage; 12～main frame;
102～controller; 104～flash memory;
106～data field; 108～spare area;
D0～DI～block; S0～SJ～spare blocks;
202,502, the female block of 602～target; And
204,504,604～update blocks.
Embodiment
Hereinafter is explained preferred embodiments of the present invention.Following explanation is not in order to restriction the present invention in order to be easier to understand the present invention.Protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Fig. 1 is memory storage 10 calcspars of the embodiment of the invention.
As shown in Figure 1, memory storage 10 is coupled to main frame 12, and comprises controller 102 and flash memory 104.In an embodiment, flash memory 104 is Sheffer stroke gate (NAND) type flash memory, and memory storage 10 comprises the various memory cards relevant with flash memory, for example: secure digital (SD) card.In Fig. 1, flash memory 104 comprises a plurality of blocks, and each block comprises a plurality of pages.
Further, can flash memory 104 be divided into data field (data pool) 106 and spare area (spare pool) 108, comprise a plurality of block and a plurality of spare blocks separately.By way of example, in data field 106, block D 0～D IFor there being the block of data, and in spare area 108, block S 0～S JThe spare blocks of having erased for not storage data or data.I and J can be numerical value identical or inequality.
As previously mentioned, because data only allow to be written into not the page of storage data (that is, not programmed or erased), when a block, for example: block D 0A plurality of pages as yet not during storage data, controller 102 can be with these pages of data programing to this block.
Yet, when main frame 12 desires to this block in, when the page of storage data carried out Data Update, controller 102 also can't be with data programing to the page of storage data.In in the case, according to embodiments of the invention, the spare blocks S of controller 102 spare areas 108 capable of using 0～S J, in order to carry out Data Update.
Fig. 2 is the synoptic diagram of a female block 202 of a target of the embodiment of the invention and a update blocks 204.
With reference to the 1st and 2 figure.Particularly, suppose that main frame 12 requires controller 102 to write data #DATA with one and upgrades a block, for example: block D 0A plurality of desires upgrade the pages.Had data because the desire of this block is upgraded the page, therefore, controller 102 also can't write these desires renewal pages that data #DATA directly is programmed to this block with this.In in the case, controller 102 can be set at the female block of target (mother block) 202 with this block.Secondly, from spare area 108, select a spare blocks, for example: block S 0, in order to update blocks 204 as the female block 202 of fresh target more.Afterwards, again this is write the renewal page that data #DATA is programmed to this update blocks 204.
In the foregoing description, a plurality of because update blocks 204 has in order to upgrade the renewal page of the female block 202 of corresponding target, therefore, can female block 202 of target and update blocks 204 be called a pairing block group.
In addition, under the prerequisite that does not influence memory storage 10 normal runnings, controller 102 can dispose both pairing block group of determined number according to the demand of access usefulness, thereby utilizes female blocks of a plurality of targets and corresponding update blocks to carry out the Data Update operation.In an embodiment; When an established condition meets; By way of example, when update blocks 204 has been filled with the data in order to the female block 202 of fresh target more, perhaps; When having reached the quantity of the pairing block group that memory storage 10 allowed, controller 102 needs further to integrate female block 202 of target and update blocks 204.
In an embodiment, controller 102 is labeled as a block to be removed with the female block 202 of target, in order to data integration to the update blocks 204 that the female block of target 202 is stored.Afterwards, the female block 202 of the target of erasing, and the female block 202 of the target after will erasing reset (reconfigure) be a spare blocks, for follow-up use.
In another embodiment, controller 102 is labeled as a block to be removed with the female block 202 of target.Then, controller 102 is selected a spare blocks in spare area 108, for example: block S 1, more female block 202 of target and update blocks 204 are integrated into block S 1Afterwards, female block 202 of the target of erasing and update blocks 204, and the female block 202 of the target after will erasing and update blocks 204 reset to spare blocks, for follow-up use.More specifically, take place, can the integration process of female block 202 of above-mentioned target and update blocks 204 be divided at least twice completion for fear of the situation that causes along with the memory capacity of block writing overtime.The flow process of Data Update and integration will specify as follows with reference to the embodiment of 3-6 figure.
Fig. 3 be the embodiment of the invention be used for flash memory write overtime control method 30 process flow diagrams.
With reference to the 1st to 3 figure, suppose that main frame 12 requires controller 102 to upgrade a block, for example: block D 0Controller 102 receives a write command and a corresponding initial logical block addresses (logical block address, LBA) (the step S302) that comes from main frame 12.Afterwards, controller 102 should initial logical block addresses links to desires the block that Updates Information, i.e. block D 0Therefore, controller 102 is with block D 0Be set at the female block 202 of target that desire is upgraded, and from spare area 108, (for example: block S select a spare blocks 0), as the corresponding update blocks 204 of the female block 202 of target.
Then, controller 102 is obtained from main frame 12 and is write data #DATA, upgrades pages in order to these desires of the female block 202 of fresh target more.Particularly, each page can be divided into 4 canned paragraphs (sector) further.Therefore, in an embodiment, can canned paragraphs be unit, but be not limited thereto, this write data #DATA be divided into a series of data cell.In other words, after controller 102 receives this initial logical block addresses, receive in regular turn immediately in order to represent that this writes a succession of data cell of data #DATA, data cell U as shown in Figure 4 0～U K
Fig. 4 is the write command CMD of the embodiment of the invention N, corresponding initial logical block addresses LBA N, and data cell U 0～U KSequential chart.
As shown in Figure 4, controller 102 receives write command CMD NAnd corresponding initial logical block addresses LBA NAfter, receive a series of data cell U immediately 0～U KFurther, receive these data cells U 0～U KAfter, controller 102 receives by what 12 main frames sent and one stops to transmit order STOP_TRAN, in order to expression data cell U 0～U KTransmitted completion.In an embodiment, between two continuous data unit, for example: data cell U 0And U 1, the cycle at interval, i.e. the busy record time of programming, be 250 milliseconds (ms), perhaps shorter.In addition, receive stop to transmit order STOP_TRAN after, to receiving a time order CMD N+1Before, also cycle of 250 milliseconds at interval.Therefore, the 102 above-mentioned time cycles capable of using of controller, the integrated operation of the pairing block group that need are carried out is divided at least twice and carries out.By way of example, the 102 above-mentioned time cycles capable of using of controller, the integrated operation of pairing block group is divided into pre cleaning operation and twice completion of back clear operation.
In addition, controller 102 is according to initial logical block addresses LBA NThe female block 202 of the target that linked is in order to determine a new model (step S304) more.In an embodiment, when main frame 12 was desired the continuous page of the female block 202 of fresh target more, the more new model of the female block 202 of target was sub-block pattern (mother-child mode).In another embodiment, when main frame 12 was desired the scattered page of the female block 202 of fresh target more, the more new model of the female block 202 of target was FAT (file allocation table, FAT) block mode (mother-FAT mode).
Fig. 5 is the synoptic diagram of the female block 502 of a target and a update blocks 504 in the sub-block pattern of another embodiment of the present invention.
As shown in Figure 5, the female block 502 of target comprises N page 502_0～502_N-1, has data P502_0～P502_N-1 respectively.Accordingly, update blocks 504 also comprises that N is upgraded page 504_0～504_N-1.Because update blocks 504 is a spare blocks, therefore, these N are upgraded page 504_0～504_N-1 and are not stored any data.
In this embodiment, suppose that main frame 12 requires more stored data P502_0～P502_4 among the continuous page 502_0～502_4 of the female block 502 of fresh target of controller 102.Therefore, the more new model of the female block 502 of controller 102 decision targets is the sub-block pattern.That is to say that controller 102 is made as a sub-block (child block) with update blocks 504, in order to carry out the Data Update operation of sub-block pattern.
Embodiment according to Fig. 5; When controller 102 during with the pairing renewal page 504_0 that is stored to update blocks 504 of Updating Information of the page 502_0～502_4 of the female block 502 of target～504_4, controller 102 is further integrated female block 502 of target and update blocks 504.At first, controller 102 is labeled as a block to be removed with the female block 502 of target.Next, controller 102 is sought a final updating page in the female block 502 pairing update blocks 504 of target, promptly upgrade page 504_4.Therefore; In the pre cleaning operation; According to final updating page 504_4, controller 102 is not moved the renewal page 504_5～504_N-1 to update blocks 504 earlier with upgrading the stored data P502_5 of page 502_5～402_N-1～P502_N-1 in the female block 502 of target.Further, in the clear operation of back, the controller 102 female block 502 of target of erasing.
Fig. 6 is the synoptic diagram of the female block 602 of a target and a update blocks 604 in the FAT block mode of another embodiment of the present invention.
As shown in Figure 6, the female block 602 of target comprises N page 602_0～602_N-1, has data P602_0～P602_N-1 respectively.Accordingly, update blocks 604 also comprises that N is upgraded page 604_0～604_N-1.Because update blocks 604 is a spare blocks, therefore, these N are upgraded page 604_0～604_N-1 and are not stored any data.
In this embodiment, suppose that main frame 12 requires more stored data P602_2, P602_3, P602_4, P602_7 and P602_8 among discontinuous page 602_2,602_3,602_4,602_7 and the 602_8 of the female block 602 of fresh target of controller 102.Therefore, the more new model of the female block 602 of controller 102 decision targets is the FAT block mode.In other words, controller 102 is made as a FAT block (FAT block) with update blocks 604, in order to carry out the Data Update operation of FAT block mode.
For instance; When main frame 12 requires with the P2 that Updates Information, P3, P4, P7 and P8 more during page 602_2,602_3,602_4,602_7 and the 602_8 of the female block 602 of fresh target, will Update Information earlier P2, P3 and P4 of controller 102 is stored in renewal page 604_0,604_1 and the 604_2 of update blocks 604.Afterwards, controller 102 utilizes look-up table TABLE_1, in order to the renewal page of record update blocks 604 and the corresponding desire renewal page of the female block 602 of target.That is to say that look-up table TABLE_1 is writing down page 602_2,602_3 and the 602_4 of the female block 602 of target, with renewal page 604_0,604_1 and the 604_2 of update blocks 604, corresponding relation between the two.Then, controller 102 is programmed to look-up table TABLE_1 the renewal page 604_3 of update blocks 604.Further, will Update Information P7 and P8 of controller 102 is stored in the renewal page 604_4 and the 604_5 of update blocks 604.Likewise, controller 102 utilizes look-up table TABLE_2 writing down the page 602_7 and the 602_8 of the female block 602 of target once again, with the renewal page 604_4 and the 604_5 corresponding relation between the two of update blocks 604.Then, controller 102 is operated the renewal page 604_6 that look-up table TABLE_2 is programmed to update blocks 604 in order to the Data Update that finishes the FAT block mode.
According to the embodiment of Fig. 6, when update blocks 604 was filled with the data in order to the female block 602 of fresh target more, controller 102 needed to integrate female block 602 of target and update blocks 604.Controller 102 is labeled as a block to be removed with the female block 602 of target earlier.Then, controller 102 is selected a spare blocks in spare area 108, for example: block S 1Therefore, in pre cleaning operation, according to look-up table TABLE_1 and TABLE_2, the data that controller 102 is stored with the female block of target 602 and stored the Updating Information of the renewal page of update blocks 604 are integrated, and integrate and write data in order to obtain one.At length; Controller 102 is with the not renewal page of the female block 602 of target; Similarly be 602_0,602_1,602_5,602_6, the stored data of 602_9～602_N-1; And the renewal page 602_0～602_2 of update blocks 604 and the stored data of 602_4～602_5 integrate, and write data in order to produce this integration.Afterwards, controller 102 writes data programing to block S with this integration 1Further, in the clear operation of back, controller 102 erase female block 602 of target and update blocks 604.
Further, with reference to the 3rd and 4 figure, after the more new model decision of the female block of target, controller 102 from main frame 12 obtain be used to upgrade write data #DATA, i.e. data cell U 0～U KParticularly, controller 102 is received the first stroke data cell U 0Back (the step S306 of Fig. 3) is judged at last subcommand CMD immediately N-1The term of execution, whether uncompleted integrated operation is arranged.That is controller 102 judges whether to be marked as a specific female block executed of waiting to remove block and crosses pre cleaning operation (the step S308 of Fig. 3).
When pre cleaning when operation spent in this specific female block executed, in 250 milliseconds of very first time cycle T 1, controller 102 is carried out the back clear operation (the step S310 of Fig. 3) of these specific female blocks.
If this specific female block is not in last subcommand CMD N-1The term of execution when carrying out the pre cleaning operation, in very first time cycle T 1, controller 102 is carried out the pre cleaning operation of this specific female block earlier.Afterwards, controller 102 can be in another time cycle, for example: data cell U 1And U 2In the cycle at interval, carry out the back clear operation (the step S312 of Fig. 3) of this specific female block.
Further, after this specific female block was erased, controller 102 reset to a spare blocks (the step S314 of Fig. 3) with this specific female block.
Next, controller 102 continues to receive remaining data cell, upgrades the FAT block mode Data Update operation of operation or Fig. 6 in order to the sub-block mode data that carries out Fig. 5.Particularly, controller 102 is carried out corresponding to write command CMD NAnd initial logical block addresses LBA NWrite data #DATA program (the step S316 of Fig. 3).That is according to the more new model of the female block 502 of target or 602, controller 102 is with all data cell U 0～U KThe correspondence that is programmed to update blocks 504 or 604 is in regular turn upgraded the page.
After controller 102 is received and stopped to transmit order STOP_TRAN, judge immediately whether the quantity of pairing block group surpasses both determined number (the step S318 of Fig. 3).
When the pairing block group quantity that is disposed when controller 102 had both reached determined number, the normal running of memory storage 10 may be affected.Therefore, controller 102 from present pairing block group, selects a wherein assembly that the block group is carried out integrated operation earlier.Afterwards, after receiving that stopping transmission ordering STOP_TRAN, order CMD to receiving inferior one N+1Before a period of time in, that is in 250 milliseconds of second period of time T 2 as shown in Figure 4, the pairing block group of 102 pairs of this selection of controller is carried out the integrated operation of part, promptly aforesaid pre cleaning is operated (the step S320 of Fig. 3).Further, but controller 102 Yu Ciyi order CMD N+1The term of execution, for example: in receiving time one order CMD N+1The first stroke data cell after 250 milliseconds in, the pairing block group of this selection is carried out remaining integrated operation, the clear operation of promptly aforesaid back.Thus, can effectively solve the problem that flash memory writes overtime.
When the quantity of pairing block group both surpassed determined number as yet, controller 102 judged further whether the more new model of target mother block is FAT block mode (the step S322 of Fig. 3).
With reference to the 3rd, 4 and 6 figure, when the more new model of the female block 602 of target is judged as the FAT block mode, controller 102 is obtained and is write data #DATA, i.e. data cell U in order to the female block 602 of fresh target more 0～U K, data length.Afterwards, according to initial logical block addresses LBA NAnd data length, controller 102 calculates the end logical block addresses of corresponding update blocks 604 after execution writes data #DATA program of the female block 602 of target, renewal page 604_6 as shown in Figure 6.Then, controller 102 is according to the size that finishes logical block addresses and update blocks 604, in order to obtain the free Page quantity of update blocks 604.Particularly, according to the embodiment of Fig. 6, update blocks 604 has N and upgrades the page, and finishes logical block addresses for upgrading page 604_6.In in the case, the free Page quantity of update blocks 604 is (N-7).Then, controller 102 judge update blocks 604 free Page quantity (N-7) whether less than a preset critical (the step S324 of Fig. 3).
When the free Page quantity (N-7) of update blocks 604 than preset critical for a long time, the free Page quantity (N-7) of expression update blocks 604 is enough to keep follow-up Data Update operation.In other words, female block 602 of target and update blocks 604 still need not carried out integrated operation.
Otherwise when the free Page quantity (N-7) of update blocks 604 during less than preset critical, expression controller 102 needs further to integrate female block 602 of target and update blocks 604.Particularly, controller 102 is labeled as block to be removed with the female block 602 of target earlier.Afterwards, in second period of time T 2 shown in Figure 4, female block 602 of 102 pairs of targets of controller and update blocks 604 are carried out pre cleaning operation (the step S326 of Fig. 3).Moreover Yu Ciyi orders CMD N+1The term of execution, for example: in receiving time one order CMD N+1The first stroke data cell after 250 milliseconds in, female blocks 602 of the 102 pairs of targets of controller and update blocks 604 are carried out the back clear operation.The pre cleaning operation and the back clear operation mode of female block 602 of target and update blocks 604 have been specified in Fig. 6 and the related embodiment thereof, do not add in this and give unnecessary details.
In sum, according to embodiments of the invention, write the situation of overtime for fear of memory storage, configurable pairing block group with the female block of target and corresponding update blocks is carried out the Data Update operation.Further, can the integrated operation of pairing block group be divided at least twice completion.That is to say that controller receives from main frame and writes in the process of data, perhaps, from main frame receive stop to transmit order after in the latent period before receive a time order, can the integrated operation of pairing block group be divided in regular turn the pre cleaning operation and after clear operation.Therefore, each order the term of execution, controller can integrate simultaneously one or many assembly to the block group, in order to save pairing block group spent time when integrating, can solve the problem that writes overtime, thereby can promote the whole access usefulness of memory storage.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Anyly have the knack of this art; Do not breaking away from the spirit and scope of the present invention, when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (14)

  1. One kind be used for flash memory write the overtime control method; This flash memory comprises a plurality of block and a plurality of spare blocks; Wherein, these block comprise a plurality of female blocks and a plurality of update blocks, and each update blocks has one or more in order to upgrade the renewal page of a corresponding female block; It is characterized in that this method comprises:
    Receive a write command and a corresponding initial logical block addresses of a main frame;
    According to the female block of a target that this initial logical block addresses linked, in order to determine a new model more;
    Judge one first female block whether operate by executed one pre cleaning, and wherein, this first female block is marked as a block to be removed;
    When this pre cleaning operation of this first female block executed,, carry out a back clear operation of this first female block in the cycle very first time;
    This first female block is reset to a spare blocks;
    According to this new model more, on the female block of this target that this initial logical block addresses linked, carry out and write the data programing program corresponding to one of this write command;
    Whether the quantity of judging these female blocks surpasses one first critical value; And
    When the quantity of these female blocks surpasses this first critical value, in one second time cycle, carry out this pre cleaning operation of one second female block, wherein, this second female block is marked as this block to be removed;
    Wherein, the step of this pre cleaning operation and this back clear operation comprises:
    This that obtain that this waits to remove block be new model more;
    When this was waited to remove this of block more new model is a sub-block pattern, this waited to remove in the pairing update blocks of block certainly, seeks a final updating page; According to this final updating page, this waits to remove in the block certainly, with the data-moving behind this final updating page to this update blocks; And this block to be removed of erasing;
    Wherein, when main frame was desired the continuous page of the female block of fresh target more, the more new model of the female block of target was the sub-block pattern;
    When this is waited to remove this of block more new model is a FAT block mode, obtain a set spare blocks; Wait to remove in the pairing update blocks of block from this, read a look-up table, this look-up table record this one or more upgrades the page and waits to remove the corresponding renewal position of block with this; According to this look-up table, with this wait to remove the stored data of block and this one or more upgrade the stored data of the page and integrate, integrate and write data in order to obtain one; This integration is write data programing to this set spare blocks; And erase that this waits to remove block and this update blocks;
    Wherein, when main frame was desired the scattered page of the female block of fresh target more, the more new model of the female block of target was the FAT block mode.
  2. 2. according to claim 1 be used for flash memory write the overtime control method, it is characterized in that, wherein, after receiving this initial logical block addresses, more comprise:
    Receive in regular turn in order to represent that this writes a series of data cell of data.
  3. 3. according to claim 2 be used for flash memory write the overtime control method, it is characterized in that, wherein, after receiving this a series of data cell, more comprise:
    Reception one stops to transmit order by what this main frame sent, in order to expression to should write command this write data and transmitted completion.
  4. 4. according to claim 3 be used for flash memory write the overtime control method, it is characterized in that wherein, this cycle very first time is in order to after representing that one first data cell receives, to the preceding a period of time that receives one second data cell.
  5. 5. according to claim 4 be used for flash memory write the overtime control method, it is characterized in that, wherein, after this second time cycle should set order receives in order to expression, to time order a period of time before that receives main frame.
  6. 6. according to claim 5 be used for flash memory write the overtime control method, it is characterized in that, more comprise:
    When this first female block is not carried out this pre cleaning operation as yet,, carry out this pre cleaning operation of this first female block in this cycle very first time; And
    In one the 3rd time cycle, carry out this back clear operation of this first female block,
    Wherein, the 3rd time cycle and before this second time cycle, received an interval time of two continuous data unit in order to expression after this cycle very first time.
  7. 7. according to claim 1 be used for flash memory write the overtime control method, it is characterized in that, more comprise:
    When the quantity of these female blocks surpassed this first critical value, whether this that judge the female block of this target more new model was a FAT block mode;
    When this of the female block of this target when more new model is this FAT block mode, obtain the data length that this writes data;
    According to this initial logical block addresses and this data length, in order to calculate the pairing update blocks of the female block of this target, the end logical block addresses after carrying out this to write the data programing program;
    Finish the size of logical block addresses and this update blocks according to this, in order to obtain a free Page quantity of this update blocks;
    Judge that whether this free Page quantity is less than one second critical value;
    When this free Page quantity during, the female block of this target is labeled as this block to be removed less than this second critical value; And
    In this second time cycle, carry out this pre cleaning operation of the female block of this target.
  8. 8. a memory storage is coupled to a main frame, it is characterized in that, comprising:
    One flash memory comprises a plurality of block and a plurality of spare blocks, and wherein, these block comprise a plurality of female blocks and a plurality of update blocks, and each update blocks has one or more in order to upgrade the renewal page of a corresponding female block; And
    One controller; Be coupled to this flash memory; In order to the write command that receives this main frame and a corresponding initial logical block addresses, according to the female block determining one of the target that this initial logical block addresses linked more new model, judge be marked as one wait to remove the whether executed one pre cleaning operation of one first female block of block, when this pre cleaning of this first female block executed is operated; Carry out a back clear operation of this first female block in the cycle very first time; With this first female block reset to a spare blocks, according to this new model more; In carry out on this initial logical block addresses linked the female block of this target corresponding to one of this write command write the data programing program, whether the quantity of judging these female blocks surpasses one first critical value and when the quantity of these female blocks during above this first critical value; In one second time cycle, to being marked as this pre cleaning operation of one second female onblock executing that this waits to remove block;
    Wherein, The operation of this pre cleaning and this back clear operation comprise obtain that this waits to remove block this more new model, when this is waited to remove this of block more new model is a sub-block pattern; Wait to remove in pairing this update blocks of block from this and to seek a final updating page, according to this final updating page, this waits to remove in the block with data-moving to this update blocks and this block to be removed of erasing after this final updating page certainly; Wherein, when main frame was desired the continuous page of the female block of fresh target more, the more new model of the female block of target was the sub-block pattern;
    When this is waited to remove this of block more new model is a FAT block mode; Obtain a set spare blocks, this waits to remove in the pairing update blocks of block certainly; Read a look-up table; This look-up table this one or more upgrade the page with this wait to remove block corresponding renewal position, table look-up according to this; With this wait to remove the stored data of block and this one or more upgrade the stored data of the page and integrate, integrate and write data, this integration is write data programing to this set spare blocks and erases that this waits to remove block and this update blocks in order to obtain one; Wherein, when main frame was desired the scattered page of the female block of fresh target more, the more new model of the female block of target was the FAT block mode.
  9. 9. memory storage according to claim 8 is characterized in that, wherein, this controller receives in order to represent that this writes a series of data cell of data after receiving this initial logical block addresses in regular turn.
  10. 10. memory storage according to claim 9 is characterized in that, wherein, after this controller receives this a series of data cell, receive by what this main frame sent and one stop to transmit order, in order to represent to should write command this write data and transmitted completion.
  11. 11. memory storage according to claim 10 is characterized in that, wherein, this cycle very first time is in order to after representing that one first data cell receives, to the preceding a period of time that receives one second data cell.
  12. 12. memory storage according to claim 11 is characterized in that, wherein, this second time cycle is ordered a period of time before in order to after representing this set order reception to inferior one of reception main frame.
  13. 13. memory storage according to claim 12; It is characterized in that; Wherein, when this first female block was not carried out this pre cleaning operation as yet, this controller was carried out this pre cleaning operation of this first female block in this cycle very first time; And in this back clear operation of this first female block of one the 3rd time cycle execution
    Wherein, the 3rd time cycle and before this second time cycle, received an interval time of two continuous data unit in order to expression after this cycle very first time.
  14. 14. memory storage according to claim 8; It is characterized in that; Wherein, When the quantity of these female blocks does not surpass this first critical value; This controller judge the female block of this target this more new model whether be a FAT block mode, when this of the female block of this target when more new model is for this FAT block mode, obtain this data length that writes data, according to this initial logical block addresses and this data length, in order to calculate the pairing update blocks of this target mother's block; After carrying out this to write the data programing program one finish logical block addresses, according to the size of this end logical block addresses and this update blocks; Obtain this update blocks a free Page quantity, judge this free Page quantity whether less than one second critical value, when this free Page quantity during less than this second critical value, the female block of this target is labeled as this block to be removed and in this second time cycle, carries out this pre cleaning operation of the female block of this target.
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CN1567476A (en) * 2003-06-24 2005-01-19 群联电子股份有限公司 High speed big block data writing method for flash memory
CN101458956A (en) * 2007-12-14 2009-06-17 慧荣科技股份有限公司 Memory apparatus and method of evenly using the blocks of a flash memory

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Publication number Priority date Publication date Assignee Title
CN1567476A (en) * 2003-06-24 2005-01-19 群联电子股份有限公司 High speed big block data writing method for flash memory
CN101458956A (en) * 2007-12-14 2009-06-17 慧荣科技股份有限公司 Memory apparatus and method of evenly using the blocks of a flash memory

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