CN114285407A - MAGIC-based nonvolatile counter and counting method - Google Patents

Abstract

The application provides a MAGIC-based nonvolatile counter and a counting method, wherein the counter comprises the following steps: a delay line and a plurality of counting units arranged and connected in sequence; each counting unit includes: a MAGIC logic gate circuit; each count unit other than the most significant bit includes: two control signal generating circuits connected to the logic gate circuit of the MAGIC; the delay line is used for outputting an initial signal corresponding to a specific step to each control signal generation circuit so that each control signal generation circuit outputs a control signal corresponding to the specific step to the logic gate circuit of the MAGIC in the next bit counting unit; the delay line is also used for outputting control signals corresponding to other steps except the specific step to each MAGIC logic gate circuit; and each counting unit executes each step corresponding to the counting unit according to the control signal and the applied voltage corresponding to each step through the MAGIC logic gate circuit so as to realize binary counting and storage of counting results. According to the method and the device, nonvolatile counting can be realized, and the counting step is simple.

Description

MAGIC-based nonvolatile counter and counting method

Technical Field

The present application relates to the field of circuit and system technologies, and in particular, to a MAGIC-based nonvolatile counter and a counting method.

Background

Memristors are basic circuit elements that characterize the relationship between electrical charge and magnetic flux, whose resistance state changes in accordance with an applied stimulus (voltage or current), and remains unchanged when the stimulus is withdrawn. According to the properties, a plurality of methods for realizing logic operation by using memristors are designed. Memristor logic can be roughly divided into two categories according to the representation of inputs and outputs in a logic cell: a non-state Logic including Resistance Threshold Logic (RTL), Memristor Ratio Logic (MRL), etc., at least one of the input and output being represented by a voltage; the other is a state LoGIC, which includes a substantial implication LoGIC (imly, IMP), a Memristor-assisted LoGIC (MAGIC), etc., and the input and output of the LoGIC gate are stored in the form of resistance states in the Memristor, respectively. Thus, stateful logic is more advantageous in terms of logic cascading and non-volatility.

A counter is a basic circuit in a digital system, and a conventional counter based on a Complementary Metal Oxide Semiconductor (CMOS) cannot maintain count data after power is turned off, but in some important occasions, it is desirable to maintain count data, such as power cycle, operating time, and the like. To solve this problem, designing CMOS based counters using EEPROMS requires a large amount of area and power. The design of a counter based on a memristor is another important scheme for realizing the non-volatility of the output result of the counter, and reducing the area and the power consumption of the counter.

There are currently two different approaches to designing memristor-based counters. One is a counter based MRL design that has advantages in power consumption and area, but still does not achieve output result non-volatility. The other is an IMP based counter whose output is non-volatile, but whose operation is very complex.

Disclosure of Invention

The application aims to provide a MAGIC-based nonvolatile counter and a counting method, which can realize nonvolatile output of a result through fewer operation steps and a relatively simple structure, and can effectively reduce the cost of external resources compared with the traditional solution.

In a first aspect, an embodiment of the present application provides a MAGIC-based nonvolatile counter, where the counter includes: a delay line and a plurality of counting units arranged and connected in sequence; each counting unit includes: a MAGIC logic gate circuit; each count unit other than the most significant count unit includes: two control signal generating circuits connected to the logic gate circuit of the MAGIC; the delay line is respectively connected with each control signal generating circuit and each MAGIC logic gate circuit; the delay line is used for outputting an initial signal corresponding to a specific step to each control signal generating circuit, so that each control signal generating circuit converts the initial signal into a control signal corresponding to the specific step and outputs the control signal to the logic gate circuit of the MAGIC in the next bit counting unit; the delay line is also used for outputting control signals corresponding to other steps except the specific step to each MAGIC logic gate circuit; and each counting unit executes each step corresponding to the counting unit according to the control signal and the applied voltage corresponding to each step through the MAGIC logic gate circuit so as to realize binary counting and storage of counting results.

Further, each of the control signal generating circuits described above includes: an intermediate state memristor and a peripheral circuit; one end of the intermediate state memristor is connected with the output end of the delay line; the other end of the intermediate state memristor is connected with a peripheral circuit; and each counting unit except the highest counting unit outputs control signals respectively corresponding to the first two steps of the next counting unit through an intermediate state memristor and a peripheral circuit in the two control signal generating circuits.

Further, the peripheral circuit includes: the resistor, the MOS tube and the inverter; the grid electrode of the MOS tube is connected with one end of the intermediate state memristor connected with the delay line; the source electrode of the MOS tube is respectively connected with the other end of the intermediate state memristor and one end of the resistor; the other end of the resistor is grounded; the drain electrode of the MOS tube is connected with the input end of the phase inverter; the output end of the inverter is used as the output end of the peripheral circuit and is used for outputting a control signal of a specific step of the next bit counting unit.

Further, in the above-described highest-order bit count unit, the logic gate circuit of the MAGIC includes: a 1T1R cell with three bottom electrodes connected together; each 1T1R cell is connected in series by a memristor and a MOS tube.

Further, the logic gate circuit of the logic gate of each counting unit except the most significant counting unit comprises: five 1T1R units and five MOS tubes.

Further, the counter further includes: a voltage supply unit; and the voltage supply unit is connected with each counting unit and is used for supplying different voltages to the MAGIC logic gate circuit in each counting unit.

In a second aspect, an embodiment of the present application further provides a counting method of a counter, where the method is applied to a MAGIC-based nonvolatile counter as described in the first aspect, and the method includes: determining a target counting mode; the target counting mode comprises an up-counting mode or a down-counting mode; determining a voltage application scheme corresponding to each step of each counting unit in a target counting mode; inputting a pulse signal in a MAGIC-based nonvolatile counter to generate a control signal corresponding to each step of each counting unit; and voltage is switched in according to a voltage application scheme, so that each counting unit passes through the MAGIC logic gate circuit, and a plurality of steps corresponding to the counting unit are executed according to the control signal corresponding to each step and the applied voltage, so that binary counting and storage of counting results are realized.

Further, if the number of the counting units of the counter is a first number, the number of the executing steps corresponding to the counter is a second number; the second number is the first number + 9.

Further, each counting unit performs a second number of steps within one counting period; the first four steps are used for overturning the output end of each counting unit; the fifth step is used for reading the operation result of the counting period of each counting unit; a number of steps are left for performing logic operations to update the resistance state of the intermediate state memristor in preparation for the toggling of the output terminal in the next counting cycle.

Further, the first five steps include: initializing the output memristor corresponding to each counting unit into a low-resistance state according to the requirement of a MAGIC NAND gate; overturning the output value corresponding to each counting unit; the result memristor is initialized to a high resistance state according to the requirement of a replica logic gate; copying the output value of each counting unit to a result memristor; the resistance state of the result memristor is read.

The embodiment of the application brings the following beneficial effects:

the application provides a non-volatile counter based on MAGIC and a counting method, wherein the counter comprises: a delay line and a plurality of counting units arranged and connected in sequence; each counting unit includes: a MAGIC logic gate circuit; each count unit other than the most significant count unit includes: two control signal generating circuits connected to the logic gate circuit of the MAGIC; the delay line is respectively connected with each control signal generating circuit and each MAGIC logic gate circuit; the delay line is used for outputting an initial signal corresponding to a specific step to each control signal generating circuit, so that each control signal generating circuit converts the initial signal into a control signal corresponding to the specific step and outputs the control signal to the logic gate circuit of the MAGIC in the next bit counting unit; the delay line is also used for outputting control signals corresponding to other steps except the specific step to each MAGIC logic gate circuit; and each counting unit executes each step corresponding to the counting unit according to the control signal and the applied voltage corresponding to each step through the MAGIC logic gate circuit so as to realize binary counting and storage of counting results. The counter and the counting method can correctly convert the counting result into binary number, store the result in the state memristor, realize the non-volatility of the output result through relatively simplified design and simple structure, and can effectively reduce the cost of external resources compared with the traditional solution.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a block diagram of a MAGIC-based non-volatile counter according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memristor symbol and a relationship between each voltage and resistance state in the symbol provided by an embodiment of the present application;

fig. 3 is a schematic diagram of a control signal generating circuit m-N according to an embodiment of the present application (if an N bit counter is designed according to this example, m is 1,2 … N-2, and N-1.N is 1, 2);

FIG. 4 is a circuit diagram of a most significant bit counting unit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a 1T1R cell and an inverter according to an embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a counting Unit (Unit 0 is taken as an example) except the most significant bit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of connection lines in a circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a structure and related operations of 1T1R according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a MAGIC logic gate according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating the generation of a Unit 0 control signal according to an embodiment of the present application;

fig. 11 is a schematic diagram of a Unit m according to an embodiment of the present application (if an Nbit counter is designed according to this example, m is 1,2 … N-2, N-1.);

fig. 12 is a flowchart of a counting method of a counter according to an embodiment of the present application;

fig. 13 is a flowchart of a 4-bit counter according to an embodiment of the present application.

Detailed Description

The technical solutions of the present application will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, there are two types of counters based on memristor design: one is a counter based on MRL design, which has advantages in power consumption and area, but still does not achieve output result non-volatility; the other is an IMP based counter whose output is non-volatile, but whose operation is very complex.

Based on this, embodiments of the present application provide a MAGIC-based nonvolatile counter and a counting method, which can implement nonvolatile output of a result with fewer operation steps and a relatively simple structure.

For the understanding of the present embodiment, first, a detailed description will be given of a MAGIC-based nonvolatile counter disclosed in the embodiments of the present application.

An embodiment of the present application provides a MAGIC-based nonvolatile counter, as shown in fig. 1, where the counter includes: a delay line 11 and a plurality of sequentially arranged and connected counting units 12; each counting unit 12 comprises: a MAGIC logic gate circuit 121; each count unit other than the most significant count unit includes: two control signal generating circuits 122 connected to the logic gate circuit 121 of MAGIC; the delay line 11 is connected to each control signal generation circuit 122 and each logic gate circuit 121 of the MAGIC, respectively; the delay line 11 is used for outputting an initial signal corresponding to a specific step to each control signal generation circuit 122, so that each control signal generation circuit 122 converts the initial signal into a control signal corresponding to the specific step and outputs the control signal to the logic gate circuit of the logic gate in the next bit counting unit; a delay line 11 for outputting a control signal corresponding to each of the logic gate circuits 121 except for the specific step; each counting unit 12 executes each step corresponding to the counting unit according to the control signal and the applied voltage corresponding to each step through the logic gate circuit 121 of the MAGIC, so as to realize binary counting and storage of counting results.

To implement non-volatility, counters should be designed using stateful logic, which has two main types: one is IMP and the other is MAGIC. The ways they implement complex logic are: and (4) decomposing the complex logic into basic logic and realizing the basic logic step by step. However, the MAGIC has a plurality of basic logics, and the IMP has only one basic logic, so that the design for realizing complex logic based on the MAGIC tends to have smaller time delay. In addition, the output of the IMP may overwrite an input, making reconstruction of the logic difficult. The present application therefore employs MAGIC to implement the proposed counter.

Generally, in a stateful logic, a High Resistance State (HRS) represents a logic "0", and a Low Resistance State (LRS) represents a logic "1"; set operation is defined as the memristor switching from a high resistive state to a low resistive state; v_readIs a small voltage that keeps the state of the memristor unchanged; the read operation is defined as applying a voltage V across the memristor_readAnd obtains a current through it, with a large current corresponding to LRS and logic "1" and a small current corresponding to HRS and logic "0". The memristor symbols employed in the embodiments of the present application, and the relationship between each voltage and resistance state in this symbol, are shown with reference to fig. 2.

The logic gate of the MAGIC is designed according to the resistance coupling principle and the 1T1R array structure, and the counter is determined according to the binary addition and subtraction principle. The logic gate circuit of the MAGIC comprises a plurality of 1T1R units, an MOS tube used as a switch, a constant value resistor and an inverter. For the characteristics of the counting Pulse, the present application uses a Clock Pulse (CP) and a delay line to generate the control signal of each step. In each operation period, the driving voltage is applied according to an up or down counting driving voltage application scheme to operate the counter to complete one up or down counting.

The MAGIC-based nonvolatile counter provided by the embodiment of the application can correctly convert the counting result into binary number, stores the result in the state memristor, and realizes nonvolatile output of the result through a relatively simple structure.

The embodiment of the application also provides another MAGIC-based nonvolatile counter, which is realized on the basis of the counter in the embodiment; this embodiment focuses on the detailed composition and corresponding functionality of the MAGIC-based non-volatile counter.

In an embodiment of the present application, each of the control signal generating circuits includes: an intermediate state memristor and a peripheral circuit; one end of the intermediate state memristor is connected with the output end of the delay line; the other end of the intermediate state memristor is connected with a peripheral circuit; and each counting unit except the highest counting unit outputs control signals respectively corresponding to the first two steps of the next counting unit through an intermediate state memristor and a peripheral circuit in the two control signal generating circuits.

Referring to fig. 3, the peripheral circuit includes: the resistor, the MOS tube and the inverter; the grid electrode of the MOS tube is connected with one end of the intermediate state memristor connected with the delay line; the source electrode of the MOS tube is respectively connected with the other end of the intermediate state memristor and one end of the resistor; the other end of the resistor is grounded; the drain electrode of the MOS tube is connected with the input end of the phase inverter; the output end of the inverter is used as the output end of the peripheral circuit and is used for outputting a control signal of a specific step of the next bit counting unit. In order to gate the memristor and avoid interference with other memristors, the memristors in the design are all in the form of 1T1R units. In order to more intuitively show the schematic diagram, the MOS transistor and its control signal which are connected in series with the memristor to form the 1T1R unit are not shown in fig. 3.

Referring to fig. 4, in the above-mentioned highest bit counting unit, the logic gate circuit of MAGIC includes: 1T1R cell with three bottom electrodes connected together, e.g. Q_N、A_N、B_N-1(ii) a Each 1T1R cell is connected in series by a memristor and a MOS tube. The symbol description of the 1T1R cell and inverter is shown in FIG. 5.

The logic gate circuit of each counting unit except the highest counting unit comprises: five 1T1R units and five MOS tubes. FIG. 6 is a schematic diagram of units except the highest-order counting Unit, taking Unit 0 as an example; the logic gate circuit of the MAGIC realizes different logic functions according to different voltages and different control signals. Each control signal generating circuit is composed of an intermediate state memristor and a peripheral circuit connected with the intermediate state memristor. The peripheral circuit comprises an inverter, a constant value resistor and a MOS tube used as a switch. Each counting unit comprises two control signal generating circuits, which are respectively outlined and illustrated in fig. 6 by dashed lines. The identification of each connecting line is shown in fig. 7.

The following design principles are introduced:

the MAGIC logic gates can be implemented using a 1T1R array of 1T1R cells. Each 1T1R unit comprises a memristor and a MOS tube as a switch, which are connected in series. Gating the memristor is defined as: applying a high voltage turns on the MOS transistor in series with the memristor. Thus, the memristor can be connected with other devices through the top electrode and the bottom electrode, and the resistance state changes according to the divided voltage. According to this principle, if one wants to perform a set, reset or read operation on the memristor M while avoiding affecting other memristors, a voltage as shown in FIG. 8(a), (b) or (c) may be applied.

The logic gate of MAGIC is constructed by adopting the resistance coupling principle, and can be summarized as follows: by controlling the connection of memristors and the drive voltage V₀And controlling the voltage across the memristor representing the output to enable the memristor to generate set or reset operation under certain resistance state combinations and change the resistance states into resistance states according with a truth table.

According to the logic gate design principle of the MAGIC, a "replica" logic gate can be designed, as shown in FIG. 9 (a). There are 3 steps to design a logic gate of MAGIC: (1) initializing; (2) applying a driving voltage; (3) and reading the result. In the replica logic gate, a is initialized, the resistance state of a is the input of the replica logic gate, and R is initialized to HRS. Then a voltage is applied as shown in fig. 8(d), and then memristors R and a are connected into a structure as shown in fig. 9 (a). When A is 1, on RVoltage drop of about V_copy. When a is "0", the voltage drop over R is about 0.5V_copy. Set at 0.5V_copy<V_set<V_copyAnd can realize that: if a is "1", R will change from "0" to "1"; if a is "0", R will remain unchanged; this enables the copying of a to R. Finally, the resistance state of R is read as a result of the "replica" logic gate.

Fig. 9(a) shows how two top-electrode connected memristors form a "replica" logic gate, and two bottom-electrode connected memristors may form a "replica" logic gate as shown in fig. 9 (b). It is exactly the same as fig. 9(a) for each memristor voltage division at various inputs.

According to the same principle, a MAGIC OR gate and a NAND gate can be designed, and a MAGIC NAND gate schematic diagram is shown in FIGS. 9(c) and (d); FIG. 9(e), (f) shows the schematic diagram of the MAGIC OR gate.

The five 1T1R units in Unit m are Q_m、A_m、B_m-1、P_m、B_m-2(for an N bit counter designed according to this method, m is 0,1,2 … N-2). The connection of Unit 0 is taken as an example for explanation, and the connection of other N-2 counting units is similar to the above. Q₀、A₀、B_0-1The gates are connected together and the bottom electrodes are connected together. Q₀、A₀And B_0-1The connecting line of the bottom electrode is connected with the Q in the Unit 1 through an MOS tube as a switch₁、A₁、B₁Are connected together. P₀And intermediate state memristor M_0-1Intermediate state memristor M_0-2The gates of the first and second memristors are connected together, and the bottom electrodes are connected together (in order to gate the memristors and avoid interfering with other memristors, the memristors in the design are all in the form of 1T1R units). P₀、M_0-1And M_0-2The bottom electrode is connected with the P through a MOS tube as a switch₁、M_1-1、M_1-2Are connected together. B is_0-2、P₀Is connected with the top electrode of the transistor through a MOS tube as a switch and a Q₀The top electrodes are connected. M_0-1At one end of the top electrodeConnected with peripheral circuit, the other end of which is connected with A through a MOS tube as a switch₀Is connected to the top electrode. M_0-2One end of the top electrode is connected with a peripheral circuit, and the other end of the top electrode is connected with a switch B through an MOS tube serving as a switch_0-1Is connected to the top electrode.

Furthermore, M_0-1A control signal generating circuit 1-1 composed of another MOS transistor as switch, a constant value resistor and an inverter, its input and output are respectively CP_0-1、CP_1-1。

M_0-2A control signal generating circuit 1-2 consisting of another MOS transistor as switch, a constant value resistor and an inverter, the input and output of which are CP_0-2、CP_1-2。

The time interval between two adjacent CP pulses is uncertain, and to cope with this, the method adopted in CMOS structures is: and designing a peripheral programmable system, and generating a control signal when detecting that the CP comes, and controlling a related structure to execute operation. In the present application, as shown in fig. 10 and 11, the CP is placed in the delay line and the control signal generation circuit to generate the control signal, so that the design is simplified, and the design can effectively reduce the cost of the external resource.

FIG. 10 shows a CP generated by the CP and delay line_0-n(ii) a FIG. 11 shows a CP_0-nCP Generation by control Signal Generation Circuit m-n_m-nTo control the operation of Unit m ( m 1,2 …, N-2, N-1) in step N (N1, 2).

The input of the delay line is a clock signal CP, and the output is CP_0-1，CP_0-2，…，CP_0-n(ii) a Wherein, CP_0-1Is the output at a delay time of tau, CP_0-2Is the output at a delay time of 2 τ, … …. Each Unit has two control signal generating circuits, the inputs of which are connected to specific output ports of the delay line. For Unit 0, control signal generation circuit 1-1, input is CP_0-1An input of which is connected to a particular output port of the delay line; its output is CP_1-1And controlling the operation of Unit 1 (next Unit) in step 1. A control signal generating circuit 1-2 with an input of CP_0-2Its outputIs CP_1-2And controlling the operation of Unit 1 (next Unit) in step 2. For Unit 1, control signal generation circuit 2-1, input is CP_0-1Its output is CP_2-1And controlling the operation of Unit 2 (next Unit) in step 1. A control signal generating circuit 2-2 with an input of CP_0-2Its output is CP_2-2And controlling the operation of Unit 2 (the next Unit) in the step 2. For an N-bit counter, the following units are similar except for the most significant count Unit Unit (N-1).

The counter further comprises: a voltage supply unit; and the voltage supply unit is connected with each counting unit and is used for supplying different voltages to the MAGIC logic gate circuit in each counting unit.

Each of the above steps completes the corresponding operation by using a voltage to open the switch during this cycle, thereby establishing a specific connection between the different memristors and the peripheral circuitry.

The minimum operating time required to complete the different steps varies. All control signals have the same pulse width by the delay of the CP. This also ensures that the system can properly execute the steps as long as the pulse width is greater than the minimum operating time to complete each step. This design greatly reduces external resources compared to conventional solutions.

In the control signal generating circuit, one end of the constant value resistor is grounded, the other end of the constant value resistor is connected with a top electrode of the memristor, the connecting point is connected with an MOS (metal oxide semiconductor) tube serving as a switch, and the other end of the MOS tube is connected with the input of the phase inverter.

Control Unit 0 Signal CP at step n (n is 1,2)_0-nConnecting the bottom electrode of the memristor as input and the gate of the MOS transistor as switch to make the switch in CP_0-nWhen the current reaches the switch-on state, the switch-off state is switched on, and the switch-off state is switched off at the rest time. The output of the inverter is the signal CP controlling Unit m (m is 1,2 … N-2, N-1) in the nth step (N is 1,2)_m-n。

And setting the resistance value of the constant-value resistor according to the conditions of high and low resistance states of the memristor. The 3 constraints are:

the high level of the inverter is set according to the magnitude of the voltage required to turn on the MOS transistor as a switch.

HfO based design may be used in the present application₂The low resistance of the w/DET memristor is about 235K, the high resistance is about 150M, and the on-state voltage V can be selected_GS(th)-PAnd V_GS(th)-NThe MOS tube of about 0.3V builds an inverter (the MOS tube in 1T1R is designed according to AP2301BI in size, because the switch opening time and the buffering time are considered to be matched with the memristor set and reset time, the MOS tube in the inverter is different in selection, only the output of the inverter is ensured to be high when the memristor in the control signal generating circuit is HRS, the SI2301 can be adopted, the constraint conditions 2 and 3 are easily met, the first constraint condition is the key, and the reset is prevented when the memristor is LRS). Thus, R is set to 3.3M Ω, and the inverter is at high level V₀Is 5V.

The embodiment of the application provides a non-volatile counter based on MAGIC, based on the resistance coupling principle and 1T1R array structure design MAGIC logic gate, based on binary system adds the principle of subtracting and confirms the counter, on this basis to the characteristics of count pulse, application clock pulse and delay line produce each step control signal, through the design of simplifying relatively and simple structure, just realized the nonvolatile of output result, compare with traditional solution, can effectively reduce the cost of external resources.

The embodiment of the present application further provides a counting method of a counter, which is applied to the MAGIC-based nonvolatile counter described in the above embodiment, as shown in fig. 12, the method includes the following steps:

step S702, determining a target counting mode; the target counting mode includes an up-counting mode or a down-counting mode.

Defining an operation cycle as follows: the counter performs n steps of operation, outputs a binary number as a counting result and stores the counting result in the result memristor, and the up-counting or the down-counting of one pulse is completed.

Step S704, determining a voltage application scheme corresponding to each step of each counting unit in the target counting mode.

In step S706, a pulse signal is input into the MAGIC-based nonvolatile counter to generate a control signal corresponding to each step of each counting unit.

In each operation period, the driving voltage is applied according to an up or down counting driving voltage application scheme to operate the counter to complete one up or down counting.

Step S708, switching in voltage according to the voltage application scheme, so that each counting unit passes through the logic gate of MAGIC, and executing a plurality of steps corresponding to the counting unit according to the control signal corresponding to each step and the applied voltage, so as to implement binary counting and storage of counting results.

The counting method of the counter provided by the embodiment of the application is applied to a MAGIC-based nonvolatile counter, can control the counter to complete binary counting by applying a clock pulse and voltage application scheme after a target counting mode is determined, realizes nonvolatile output of a result through fewer operation steps, and can effectively reduce the cost of external resources compared with the traditional solution.

The embodiment of the present application further provides another counting method for a counter, which is implemented based on the above counting method embodiment, and this embodiment mainly describes specific steps of the counting method in one counting period.

In the counting method of the embodiment of the application, if the number of the bit counting units of the counter is a first number, the number of the execution steps corresponding to the counter is a second number; the second number is the first number + 9. If the 4-bit counter is taken as an example and the number of bit counting units is 4, 4+9 steps, i.e. 13 steps, are required for one counting cycle of the 4-bit counter.

Each counting unit performs a second number of steps in one counting cycle; the first four steps are used for overturning the output end of each counting unit; the fifth step is used for reading the operation result of the counting period of each counting unit; leaving multiple steps for logic operations to update intermediate state memristorsThe state of the device provides for the toggling of the output terminal in the next counting cycle. If a 4-bit counter is taken as an example, in one counting period, the next 8 steps execute some logic operations to update the intermediate state memristor M_m-1、M_m-2State (m is 0,1,2,3) in preparation for the next cycle of output flipping.

Intermediate state memristor M_m-1And a connected peripheral circuit connected with the control circuit to form a control signal generation circuit (M +1) -1 and an intermediate state memristor M_m-2And a connection peripheral circuit connected to them, constituting a control signal generating circuit (m +1) -2. When CP arrives in the next counting period, according to M_m-1、M_m-2Generates signals to control the respective modules. When M is obtained by calculation in 8 steps after the period_m-1、M_m-2Is in a high resistance state (M)_m-1＝M_m-20), the control signal generated when the next period CP arrives will cause Uint (m +1) to perform an inversion.

In the counting period, the first five steps specifically include:

initializing the output memristor corresponding to each counting unit into a low-resistance state according to the requirement of a MAGIC NAND gate; overturning the output value corresponding to each counting unit; the result memristor is initialized to a high resistance state according to the requirement of a replica logic gate; copying the output value of each counting unit to a result memristor; the resistance state of the result memristor is read.

The counter in the embodiment of the application is designed to meet the following three points:

(1) each output performs a flip at a particular cycle. This means that each output is executed in a specific cycle

And remain unchanged for the rest of the time.

(2) Implementation with MAGIC

The method can be divided into two steps: the first step is completed

The value of Q is then copied to a.

(3) And designing a rule for controlling the turnover of each output of the upper counter (the lower counter) according to a binary addition (subtraction) principle.

By Q₀，Q₁，Q₂，Q₃…Q_nThe 1 st, 2 nd, 3 rd and 4 rd bits (4 … n) output of the counter from low to high is shown, when a CP pulse comes, the counter performs several steps to complete one counting.

According to the binary addition principle, the rule of inversion in the up-counting scheme can be designed: when Q is₀＝Q₁＝…＝Q _n1, the next period Q_n+1And performing the overturning.

According to this principle, expression (2) is obtained in combination with three points of counter design. When M is₀＝M₁＝…＝M_nWhen 0, the next period Q_n+1And performing the overturning.

Similarly, according to the principle of binary subtraction, the rule of inversion in the up-counting scheme can be designed: when Q is₀＝Q₁＝…＝Q _n0, next period Q_n+1And performing the overturning.

According to this principle, expression (3) is obtained in combination with three points of counter design. When M is₀＝M₁＝…＝M_nWhen 0, the next period Q_n+1And performing the overturning.

Therefore, the control conditions for the flipping of each output end in the counting-up and counting-down schemes can be summarized according to expressions (2) and (3): when M is₀＝M₁＝…＝M_nWhen 0, the next period Q_n+1And performing the overturning. Designing the control signal generating circuit can be developed in accordance with this.

The implementation principle and the generated technical effects of the counting method of the counter provided by the embodiment of the present application are the same as those of the embodiment of the counter, and for the sake of brief description, no mention is made in the embodiment of the counting method of the present application, and reference may be made to the corresponding contents in the embodiment of the counter.

The embodiment of the application also provides another MAGIC-based nonvolatile counter and a counting method, and the embodiment takes the design of a 4-bit counter as an example to describe in detail the design idea and the design steps of the MAGIC-based nonvolatile counter and the counting method.

Referring to fig. 13, the design idea of the 4-bit counter is as follows:

construct Unit m (m is 0,1,2,3), and output Q_m，CP_m-nAnd executing control signals related to the operation at the nth step for the operation Unit m. If CP_m-nAt a high level, the delay time τ is CP_m-nAnd CP_m-(n+1)The time therebetween, which is set according to the following expression (4):

τ＝T_pulse+T_buffer (4)

wherein, T_pulseFor CP high level time, T_pulseShould be large enough to ensure that any step in the counting operation is completed, as determined by the memristor used. T is_bufferIs the buffering time. In the 1T1R array, the switch opening and the transmission of the control signal take time, so there is a buffer time between each operation, which should be greater than the sum of the switch opening time, the switch closing time, and the delay time of the control signal. T is_minIs CP_m-nThe time between two adjacent pulses, which should be greater than the time of one operating cycle. From the definition of the operating period and the scheme of generating the control signal through the delay line, expression (5) is obtained:

T_min>n×τ (5)

in the design of a 4-bit counter, memristors in a 1T1R array are based on HfO₂w/DET ofMemristor, the sizing of the MOS transistor is referenced to AP2301 BI. According to the test result, the set operation can be successfully carried out by applying the 150ns and 1.65V pulses, the reset operation can be successfully carried out by applying the 150ns and-0.4V pulses, and the reading operation can be successfully carried out by applying the 150ns and 0.2V pulses. So set up T_pulse150ns, CP high level bit 5V. According to the manual of AP2301BI, the on delay time, the on rise time, the off delay time, and the off decay time are 10ns, 5ns, 21ns, and 7ns, respectively, so T is set_buffer50 ns. Thus, it is calculated that: τ is 200 ns.

The driving voltage application scheme is as follows:

table 1 is a count-up drive voltage application scheme for a 4bit counter. One operating cycle was 2.6 mus in duration and there were 13 operating steps. Wherein, the 1 st to 4 th steps realize the turnover of each output end, and the 5 th step is to read the operation result of the operation period.

The steps 6 to 13 are based on the expression (2) to design the requirement when M₀＝M₁＝…＝M_nWhen 0, the next operating period Q_n+1And performing the overturning.

The specific mode is as follows: when M is_0-1＝M_0-2When the next operation cycle Unit 1 is equal to 0, the 1 st and 2 nd steps in the table 1 are executed, and the operation is completed

(completion Q)₁Flip of (d); when M is_1-1＝M_1-2When the next operation cycle Unit 2 is equal to 0, the 1 st and 2 nd steps in table 1 are executed, and the operation is completed

(completion Q)₂Flip of (d); when M is_2-1＝M_2-2When the next operation cycle Unit 3 is equal to 0, the 1 st and 2 nd steps in table 1 are executed, and the operation is completed

(completion Q)₃Flip of (d).

In any operation cycle, if the up-counting is performed, for Unit m (m is 0,1,2,3), in the nth step (n is 1,2,3,4,5,6,7,8,9,10,11, 1)2,13), if CP_m-nWith a high time of 150ns, Unit m will perform the operations listed in Table 1, Table 1 for the up-count drive voltage application scheme of the 4-bit counter.

TABLE 1

Table 2 is a count-down drive voltage application scheme for a 4-bit counter. It differs from the up-count drive voltage application scheme in that: steps 6 to 13 are designed according to expression (3).

In any operation cycle, if count-down is performed, for Unit m (m is 0,1,2,3), in the nth step (n is 1,2,3,4,5,6,7,8,9,10,11,12,13), if CP is present_m-nWith a high time of 150ns, Unit m will perform the operations listed in Table 2.

TABLE 2

The design scheme of the control signal generating circuit is as follows:

the expressions (2) and (3) can be summarized as follows: when M is₀＝M₁＝…＝M_nWhen 0, the next period Q_n+1And performing the overturning. Steps 6 to 13 of the up and down driving voltage application scheme are designed according to this principle: when M is_0-1＝M_0-2When the next operation cycle Unit 1 is equal to 0, the 1 st and 2 nd steps in the table 1 are executed, and the operation is completed

(completion Q)₁Flip of (d). When M is_1-1＝M_1-2When the next operation cycle Unit 2 is equal to 0, the 1 st and 2 nd steps in table 1 are executed, and the operation is completed

(completion Q)₂Flip of (d). When M is_2-1＝M_2-2When the next operation cycle Unit 3 is equal to 0, the 1 st and 2 nd steps in table 1 are executed, and the operation is completed

(completion Q)₃Flip of (d).

Based on the above analysis, a control signal generation circuit is designed. Fig. 3 is a schematic diagram of a control signal generating circuit m-n (m is 1,2, 3. n is 1, 2). In the design of a CP high-level amplitude 5V, 4bit counter, HfO-based counter is adopted₂The low resistance of the w/DET memristor is about 235K omega, the high resistance is about 150M omega, and the on-state voltage V can be selected_GS(th)-PAnd V_GS(th)-NThe MOS transistor of about 0.3V builds an inverter, so the design R is 3.3M Ω. If in the ith cycle, M_m-10 (corresponding to HRS), when CP_0-1And CP_0-2At the occurrence of i +1 cycles, U_RThe high level amplitude of the inverter output is about 0, and the high level amplitude of the inverter output is 5V. M_m-1When CP is not equal to LRS_0-1And CP_0-2At the occurrence of i +1 cycles, U_RThe high level amplitude of the inverter output is 0 if the high level amplitude of the inverter output is about 5V. Thus, a CP can be generated_m-1And CP_m-2And controlling Unit m to execute step 1 and step 2 in the (i +1) th cycle.

The counter structure and implementation are as follows:

the foregoing has described: CP (CP)_m-nIs a signal for controlling the operation of Unit m ( m 1,2,3) in step n (n 1, 2). The relationship between the various control signals in fig. 9 is: first, an input clock signal CP is passed through a delay line to generate CP_0-n(n-1, 2,3,4,5,6,7,8,9,10,11,12, 13); second, CP_0-1CP is generated by a control signal generating circuit 1-1_1-1CP is generated by a control signal generating circuit 2-1_2-1Via a control signal generating circuit3-1 Generation of CP_3-1，CP_0-2CP is generated by a control signal generating circuit 1-2_1-2CP is generated by a control signal generating circuit 2-2_2-2Generates CP through a control signal generating circuit 3-2_3-2(ii) a Third, for x, 3,4,5,6,7,8,9,10,11,12,13, CP_0-xIs the CP_1-xIs also CP_2-xIs also CP_3-x。

Table 3 shows a specific method for Unit 0 to apply the driving voltage at each step when the 4-bit counter counts up during one counting period. The specific method for applying the driving voltage to Unit 1, Unit 2, and Unit 3 in each step when the 4-bit counter counts up is similar, and is not described herein again.

The analysis is performed by taking as an example the Unit 0 in the first cycle (output changed from 0000 to 0001) counted up.

Unit 0 consists of three parts: 1. MAGIC logic gate circuit comprising 1T1R cell Q₀、A₀、B_0-1、B_0-2、P₀. 2. Intermediate state memristor comprising 1T1R cell M_0-1And M_0-2. 3. And M_0-1And M_0-2Two peripheral circuits connected. Before CP appeared, A₀、A₁、A₂And A₃Is initialized to HRS because the counter output is 0 (corresponding to binary number 0000) when CP is not present. B is to be_0-1、B_0-2、B_1-1、B_1-2、B_2-1、B_2-2、B_3-1、B_3-2Initialized to LRS.

When the CP comes, the operations in table 1 are started to be performed.

In step 1, CP_0-1Connection G_0-1Strobing memristor Q₀、A₀、B_0-1，WL_0-1Is connected with V_set，BL_0-1Is grounded to Q₀The LRS is initialized as required by the MAGIC NAND gate.

In step 2, CP_0-2Connection G_0-1Strobing memristor Q₀、A₀、B_0-1，WL_0-1And WL_0-2Is connected with V_NAND，WL_0-3Ground, Q₀、A₀And B_0-1Forming MAGIC NAND doors, finish

I.e., Unit 0 completes Q₀And (6) turning over.

In step 3, CP_0-3Connection G_0-1Strobing memristor Q₀、A₀、B_0-1，WL_0-1Ground, BL_0-1To | V_reset|，A₀The HRS is initialized as required by the "duplicate" logic gate.

In step 4, CP_0-4Connection G_0-1Strobing memristor Q₀、A₀、B_0-1，WL_0-1Ground, WL_0-1Is connected with V_copy，Q₀And A₀Form duplicate logic gates to implement₀Copy to A₀. Steps 3 and 4 are the input to the next cycle to transfer the result of this flip.

In step 5, CP_0-5Connection G_0-1Strobing memristor Q₀、A₀、B_0-1，WL_0-2Is connected with V_read，WL_0-1Is grounded, read A₀Is the output of Unit 0 for this cycle of operation.

In step 6, CP_0-6Connection G_0-2Gating memristor P₀、M_0-1、M_0-2，WL_0-4Is connected with V_set，BL_0-2Is grounded to P₀The LRS is initialized as required by the MAGIC NAND gate.

In step 7, CP_0-7Connection G_0-1、G_0-2、G_0-3Strobing memristor Q₀、A₀、B_0-1、P₀、M_0-1、M_0-2And B_0-2，BL_0-1And BL_0-3Ground, BL_0-2Is connected with V_NAND，Q₀、B_0-2And P₀Form MAGIC NAND door, realize

In step 8, CP_0-8Connection G_0-2Gating memristor P₀、M_0-1、M_0-2，WL_0-5Ground, BL_0-2To | V_reset|，M_0-1Initialization to HRS is as required by the "copy" logic gate.

In step 9, CP_0-8Connection G_0-2Gating memristor P₀、M_0-1、M_0-2，WL_0-4Ground, WL_0-5Is connected with V_copy，P₀And M_0-1Form 'copy' logic gate to realize copy P₀To M_0-1. This step is to update M_0-1The state of (1).

Steps 10 and 11 are updating M_1-1And M_1-2The state of (1).

In step 10, Unit 0, CP_0-10Connection G_0-2Gating memristor P₀、M_0-1、M_0-2，WL_0-4Ground, WL_0-5And (4) grounding. In Unit 1, CP_1-10Connection G_1-2Gating memristor P₁、M_1-1、M_1-2，WL_1-5Is connected with V_OR. In addition, CP_0-10Opening as switch isolation BL_0-2And BL_1-2The MOS transistor of (1). Thus, P₀、M_0-1And M in Unit 1_1-1Forming a MAGIC OR gate to realize M_1-1＝M_0-1OR P₁。

In step 12, CP_0-12Connection G_0-2，WL_0-6Ground, BL_0-2To | V_reset|，M_0-2Initialization to HRS is as required by the "copy" logic gate.

In step 13, CP_0-13Connection G_0-2，WL_0-5Ground, WL_0-6Is connected with V_copy，M_0-1And M_0-2Forming 'copy' logic gate to realize copy M_0-1To M_0-2. Step 12, step 13 is to update M_0-2Status. The analysis of other units in the count up and down operations is similar. Unit 1 memristor Q₁、A₁、B_1-1、B_1-2、P₁、M_1-1、M_1-2And (4) forming. Unit 2 memristor Q₂、A₂、B_2-1、B_2-2、P₂、M_2-1、M_2-2And (4) forming. Unit 3 memristor Q₃、A₃、B₃And (4) forming.

TABLE 3

Similarly, the specific method for applying the driving voltage to Unit 0, Unit 1, Unit 2, and Unit 3 in each step when the 4-bit counter counts down is not described herein again.

The counter described above is exemplified by a counter composed of 4-bit counting units, the counter provided in the embodiment of the present application can be extended to an N-bit counter, and in the N-bit counter, the first N-1 counting units have the same structure and are composed of 7 1T1R units, 7 MOS transistors serving as switches, 2 fixed-value resistors, and 2 inverters. The nth counting unit consists of 3 1T 1R. 1 MOS tube as a switch is arranged between the Nth counting unit and the (N-1) th counting unit, and two MOS tubes as switches are arranged between every two other adjacent counting units. The time delay of the N bit counter is N +9 (N +9 steps are needed for completing one counting operation), the area of the N bit counter is 7N-4 memristors, and the number of MOS tubes is 18N-16.

The embodiment of the application provides a MAGIC-based nonvolatile counter and a counting method, wherein a 4-bit counter is taken as an example, a circuit structure is designed, and a driving voltage application scheme is given; compared with the counter based on IMP, the method has the advantages that the operation steps are greatly simplified, the nonvolatile output result is realized only by fewer operation steps and a relatively simple structure, and the cost of external resources can be effectively reduced.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A MAGIC-based non-volatile counter, the counter comprising: a delay line and a plurality of counting units arranged and connected in sequence; each of the counting units includes: a MAGIC logic gate circuit; each count unit other than the most significant count unit includes: two control signal generating circuits connected to the logic gate circuit of the MAGIC; the delay line is respectively connected with each control signal generating circuit and each MAGIC logic gate circuit;

the delay line is used for outputting an initial signal corresponding to a specific step to each control signal generation circuit, so that each control signal generation circuit converts the initial signal into a control signal corresponding to the specific step and outputs the control signal to the MAGIC logic gate circuit in the next bit counting unit;

the delay line is also used for outputting control signals corresponding to other steps except the specific step to each MAGIC logic gate circuit;

and each counting unit executes each step corresponding to the counting unit according to the control signal and the applied voltage corresponding to each step through the MAGIC logic gate circuit so as to realize binary counting and storage of counting results.

2. The MAGIC-based nonvolatile counter of claim 1, wherein each control signal generation circuit comprises: an intermediate state memristor and a peripheral circuit;

one end of the intermediate state memristor is connected with the output end of the delay line; the other end of the intermediate state memristor is connected with the peripheral circuit;

and each counting unit except the highest counting unit outputs control signals respectively corresponding to the first two steps of the next counting unit through the intermediate state memristor and the peripheral circuit in the two control signal generating circuits.

3. The MAGIC-based non-volatile counter of claim 2, wherein the peripheral circuit comprises: the resistor, the MOS tube and the inverter; the gate of the MOS tube is connected with one end of the intermediate state memristor, which is connected with the delay line; the source electrode of the MOS tube is respectively connected with the other end of the intermediate state memristor and one end of the resistor; the other end of the resistor is grounded; the drain electrode of the MOS tube is connected with the input end of the phase inverter; the output end of the inverter is used as the output end of the peripheral circuit and is used for outputting a control signal of a specific step of a next bit counting unit.

4. The MAGIC-based nonvolatile counter of claim 1, wherein the MAGIC logic gate circuit in the most significant count cell comprises: a 1T1R cell with three bottom electrodes connected together; each 1T1R cell is connected in series by a memristor and a MOS tube.

5. The MAGIC-based nonvolatile counter of claim 1, wherein the MAGIC logic gate circuit of each of the other count units except the most significant count unit comprises: five 1T1R units and five MOS tubes.

6. The MAGIC-based nonvolatile counter of claim 1, wherein the counter further comprises: a voltage supply unit; the voltage providing unit is connected with each counting unit and is used for providing different voltages for the logic gate circuit of the MAGIC in each counting unit.

7. A counting method of a counter, applied to a MAGIC-based non-volatile counter according to any of claims 1-6, the method comprising:

determining a target counting mode; the target counting mode comprises an up-counting mode or a down-counting mode;

determining a voltage application scheme corresponding to each step of each counting unit in the target counting mode;

inputting a pulse signal in the MAGIC-based nonvolatile counter to generate a control signal corresponding to each step of each counting unit;

and accessing voltage according to the voltage application scheme so that each counting unit passes through the MAGIC logic gate circuit, and executing a plurality of steps corresponding to the counting unit according to the control signal corresponding to each step and the applied voltage so as to realize binary counting and storage of counting results.

8. The method according to claim 7, wherein if the number of counting units of the counter is a first number, the number of executing steps corresponding to the counter is a second number; the second number is the first number + 9.

9. The method according to claim 8, characterized in that each counting unit performs said second number of steps within one counting cycle; the first four steps are used for overturning the output end of each counting unit; the fifth step is used for reading the operation result of the counting period of each counting unit; a number of steps are left for performing logic operations to update the resistance state of the intermediate state memristor in preparation for the toggling of the output terminal in the next counting cycle.

10. The method of claim 9, wherein the first five steps comprise:

initializing the output memristor corresponding to each counting unit into a low-resistance state according to the requirement of a MAGIC NAND gate;

overturning the output value corresponding to each counting unit;

the result memristor is initialized to a high resistance state according to the requirement of a replica logic gate;

copying the output value of each counting unit to a result memristor;

the resistance state of the result memristor is read.

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