CN113676176A

CN113676176A - Logic gate circuit

Info

Publication number: CN113676176A
Application number: CN202110876871.XA
Authority: CN
Inventors: 苏康; 郭芬; 满宏涛; 李拓
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2021-07-31
Filing date: 2021-07-31
Publication date: 2021-11-19

Abstract

The invention discloses a logic gate circuit, which comprises an input module, an output memristor and a control module, wherein the input module comprises N input memristors and N switches, the control module controls the action of each switch and the logic state of each memristor based on a user instruction so as to change the resistance value of the input module and the resistance value state of the output memristor, and further logic operation under different numbers of input states can be realized, and the memristor can keep the logic state before power failure after power failure and has non-volatility, so that the reliability of the logic gate circuit in the application is higher; in addition, the memristor has the characteristics of low power consumption and simple structure, so that the power consumption of the logic gate circuit can be reduced, and a calculation framework integrating storage and calculation can be further constructed.

Description

Logic gate circuit

Technical Field

The present invention relates to the field of digital circuits, and more particularly to a logic gate circuit.

Background

The traditional von Neumann computing architecture determines the separation of the processing unit and the memory unit, generates the energy consumption of data transmission between the two, and causes the appearance of a 'memory wall', and limits further enhancement of the computing performance. The nonvolatile logic unit based on the memristor integrates calculation and storage functions, a calculation architecture integrating calculation and storage can be constructed, and the performance bottleneck of the von Neumann architecture is broken through.

Disclosure of Invention

The invention aims to provide a nonvolatile logic gate circuit which can realize logic operation under different numbers of input states, has nonvolatile property and higher reliability, reduces the power consumption of the logic gate circuit and further constructs a calculation framework integrating calculation as the memristor can keep the logic state before power failure after power failure.

In order to solve the technical problem, the invention provides a logic gate circuit which comprises an input module, an output memristor and a control module, wherein the input module comprises N input memristors and N switches, and N is an integer not less than 2;

the input memristors are connected with the switches in a one-to-one correspondence mode, the input end of the input module is connected with a power supply, the output end of the input module is connected with one end of the output memristor, the other end of the output memristor is grounded, and the control module is connected with the control end of the input module;

the control module is used for controlling N switching actions in the input module and controlling the logic states of N input memristors based on the user instruction so as to adjust the resistance value of the input module, and also controlling the logic states of the output memristors so as to enable the logic gate circuit to realize logic operation.

Preferably, the control module is specifically configured to set a logic state of the output memristor based on the user instruction, determine the number and logic state of the input memristors, select a determined number of the input memristors from the N input memristors, set a logic state corresponding to the user instruction for the selected input memristors, and control the N switching actions to adjust a resistance value of the input module, so that the selected input memristors and the output memristors implement a logic operation.

Preferably, the control module is further configured to set the logic states of the N input memristors to preset logic in advance;

controlling N switching actions in the input module and logic states of N input memristors based on the user instruction to adjust resistance values of the input module, and controlling logic states of the output memristors to enable the logic gate circuit to realize logic operation, wherein the logic operation comprises the following steps:

setting a logic state of the output memristors and determining a number and a logic state of the input memristors based on the user instruction;

selecting a determined number of input memristors from the N input memristors, wherein the preset logic corresponds to the user instruction;

and controlling the N switches to act so as to adjust the resistance value of the input module, so that the selected input memristor and the output memristor realize logic operation.

Preferably, the logic gate circuit is an and circuit;

the positive electrode of the first input memristor is connected with the power supply, the positive electrode of the (i + 1) th input memristor is connected with the negative electrode of the ith input memristor, the negative electrode of the Nth input memristor is connected with the positive electrode of the output memristor, the negative electrode of the output memristor is the output end of the logic gate circuit, the switch is connected with the input memristor corresponding to the switch in parallel, and i is an integer not less than 1 and less than N;

setting a logic state of the output memristor based on the user instruction, including:

setting a logic state of the output memristor to a logic 0 based on the user instruction;

controlling N of said switching actions, including:

and controlling the switch corresponding to the selected input memristor to be opened and the rest switches to be closed.

Preferably, the logic gate circuit is a nand circuit;

the positive electrode of the first input memristor is connected with the power supply, the positive electrode of the (i + 1) th input memristor is connected with the negative electrode of the ith input memristor, the negative electrode of the Nth input memristor is connected with the negative electrode of the output memristor, the positive electrode of the output memristor is the output end of the logic gate circuit, the switch is connected in parallel with the input memristor corresponding to the switch, and i is an integer not less than 1 and less than N;

setting a logic state of the output memristor to a logic 1 based on the user instruction;

controlling N of said switching actions, including:

Preferably, the logic gate circuit is an or circuit;

the first ends of the N switches are connected with the power supply, the second ends of the N switches are connected with the anodes of the input memristors corresponding to the N switches, the cathodes of the N input memristors are connected with the anode of the output memristor, and the cathode of the output memristor is the output end of the logic gate circuit;

controlling N of said switching actions, including:

and controlling the switch corresponding to the selected input memristor to be closed and the rest of the switches to be opened.

Preferably, the logic gate circuit is a nor circuit;

the first ends of the N switches are connected with the power supply, the second ends of the N switches are connected with the anodes of the input memristors corresponding to the N switches, the cathodes of the N input memristors are connected with the cathode of the output memristor, and the anode of the output memristor is the output end of the logic gate circuit;

controlling N of said switching actions, including:

Preferably, the switch is a metal oxide semiconductor field effect transistor (MOS) tube or a triode.

Preferably, the switch is an N-channel metal oxide semiconductor field effect transistor NMOS transistor.

Preferably, the input memristor and the output memristor are both threshold-type memristors, the input memristor and the output memristor are logic 1 when the voltage across the input memristor and the output memristor are greater than a first threshold voltage, the input memristors and the output memristors are logic 0 when the voltage across the input memristor and the output memristor are less than a second threshold voltage, and the first threshold voltage is greater than the second threshold voltage;

controlling the logic states of the N input memristors and the output memristors, comprising:

controlling voltage values applied across the N input memristors and the output memristors, respectively, such that the voltage values are greater than the first threshold voltage or less than the second threshold voltage.

The application provides a logic gate circuit, which comprises an input module, an output memristor and a control module, wherein the input module comprises N input memristors and N switches, when a user instruction is received, the control module controls the action of each switch and controls the logic state of each memristor so as to change the resistance value of the input module and the resistance value state of the output memristor, and further logic operation under different numbers of input states can be realized, and the memristor can keep the logic state before power failure after power failure and has non-volatility, so that the reliability of the logic gate circuit is higher; in addition, the memristor has the characteristics of low power consumption and simple structure, so that the power consumption of the logic gate circuit can be reduced, and the calculation framework integrating storage and calculation is further constructed to be reduced

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a block diagram of a logic gate circuit according to the present invention;

FIG. 2 is a schematic diagram of a logic gate circuit for performing an AND operation according to the present invention;

FIG. 3 is a schematic diagram of a logic gate circuit for implementing NAND operation according to the present invention;

FIG. 4 is a schematic diagram of a logic gate circuit for implementing an OR operation according to the present invention;

fig. 5 is a schematic diagram of a logic gate circuit for implementing nor operation according to the present invention.

Detailed Description

The core of the invention is to provide a logic gate circuit which can realize logic operation under different numbers of input states, and has the advantages of non-volatility, higher reliability, reduced power consumption of the logic gate circuit and further construction of a calculation architecture integrating storage and calculation because the memristor can keep the logic state before power failure after power failure.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The application introduces the working principle of the threshold memristor, and the memristor has the characteristics of nonvolatility, low power consumption, simple structure and the like, and has obvious advantages in the aspects of scalability, compatibility with a CMOS (complementary metal oxide semiconductor) process, response speed and the like. Reversible overturning of two states of high and low resistance values can occur when certain conditions are met, wherein the high and low resistance values can represent two states of '0' and '1' in logic, the reversible overturning under the conditions is met, controllable jumping between the logic states is guaranteed, and after power is removed, the resistance state of the memristor is still stable and has a nonvolatile characteristic, so that the memristor can meet the realization of a nonvolatile logic function. Nonvolatile logic operation based on memristors has great potential value in the field of computing.

Specifically, when the memristor is a threshold-type memristor, the memristor requires two threshold voltages to change the response boundary resistance of the memristor, specifically, assuming that the first threshold voltage is V_{T_ON}The second threshold voltage is V_{T_OFF}Wherein V is_{T_ON}＞V_{T_OFF}The memristor transitions to a low-resistance state (R) when a voltage across the memristor is greater than a first threshold voltage_ON) I.e., a transition from logic 0 to logic 1; the memristor transitions to a high resistive state (R) when a voltage across the memristor is less than a second threshold voltage_OFF) I.e. from logic 1 to logic 0, and R_OFF＞＞R_ON。

Referring to fig. 1, fig. 1 is a block diagram of a logic gate circuit provided by the present invention, the circuit includes an input module 11, an output memristor 12 and a control module 13, the input module 11 includes N input memristors 112 and N switches 111, where N is an integer not less than 2;

the input memristors 112 are connected with the switches 111 in a one-to-one correspondence manner, the input end of the input module 11 is connected with a power supply, the output end of the input module 11 is connected with one end of the output memristor 12, the other end of the output memristor 12 is grounded, and the control module 13 is connected with the control end of the input module 11;

the control module 13 is configured to control the actions of the N switches 111 in the input module 11 and the logic states of the N input memristors 112 based on a user instruction, so as to adjust the resistance value of the input module 11, and also control the logic states of the output memristors 12, so that the logic gate circuit realizes logic operation.

Considering that the output signal of the logic gate circuit in the prior art is an unstable level signal, the result of the logic operation may be erroneous.

In order to solve the technical problems, the design idea of the application is as follows: considering that the memristor has the characteristics of nonvolatility, low power consumption and simple structure, the memristor can be applied to a logic gate circuit. Specifically, the working principle of the memristor is as follows: the high-low resistance state of the memristor respectively represents a logic 0 and a logic 1 in the logic state, reversible reversal of the two states of the high-low resistance state can occur to the memristor when a certain condition is met, namely, the jump between the logic 0 and the logic 1 can be completed when the certain condition is met, and the resistance state of the memristor can be kept stable after the power failure of the memristor, and data loss cannot be caused. Therefore, different logical operations are realized by connecting the memristors differently.

Based on this, the logic gate circuit in the present application includes the output memristor 12, the control module 13, and the input module 11 including the N input memristors 112 and the N switches 111, and when receiving a user instruction, the logic state of each input memristor 112 in the input module 11 is controlled based on the user instruction, and the action of each switch 111 is controlled, so as to adjust the resistance value of the input module 11. In addition, the logic state of the output memristor 12 is controlled, the input module 11 is connected with the output memristor 12 in series, and the voltage division value of the output memristor 12 can be changed by adjusting the resistance value of the input module 11, so that the logic state of the output memristor 12 is changed.

As a preferred embodiment, when the memristor in the present application is a threshold-type memristor, the way to detect the logic state of the output memristor 12 is: by detecting the voltage across the output memristor 12, when the voltage value across the output memristor 12 is greater than the first threshold voltage, the corresponding resistance state is converted from the high resistance state to the low resistance state, and the logic state is converted from logic 1 to logic 0. When the voltage values at the two ends of the resistor are smaller than the second threshold voltage, the corresponding resistance state is converted from the low resistance state to the high resistance state, and the logic state is converted from logic 0 to logic 1.

The logic operation implemented by the logic gate circuit in the present application may be a combination of one or more of and operation, or operation, nand operation, and nor operation.

In addition, the switch 111 in the present application may be, but is not limited to, a MOS transistor or a triode, and may also be another controllable switch 111, and the present application is not limited specifically herein.

In conclusion, the logic gate circuit in the application can realize logic operation under different numbers of input states, and the memristor has the characteristics of nonvolatility and low power consumption, so that the logic gate circuit in the application has high reliability and low power consumption, and further can construct a calculation-integrated computing architecture.

On the basis of the above-described embodiment:

as a preferred embodiment, the control module 13 is specifically configured to set the logic state of the output memristor 12 and determine the number and logic state of the input memristors 112 based on a user instruction, select the determined number of input memristors 112 from the N input memristors 112, set the logic state corresponding to the user instruction for the selected input memristors 112, and control the N switches 111 to operate to adjust the resistance value of the input module 11, so that the selected input memristors 112 and the output memristors 12 implement a logic operation.

The embodiment is directed to provide a specific implementation manner for controlling the actions of the N switches 111 in the input module 11 and controlling the logic states of the N input memristors 112 and the output memristors 12 based on a user instruction, and specifically, the logic state of the output memristor 12 may be set according to the user instruction (for example, set to logic 0 during operation or set to logic 1 during operation), the input number required to perform the logic operation and the logic state required to perform the logic operation may be determined based on the user instruction, then, the determined number of input memristors 112 are selected from the N input memristors 112, then, the selected logic state of the input memristors 112 is set to correspond to the user instruction, and then, the N switches 111 are controlled to act, so that the selected input memristors 112 and the output memristors 12 are combined to implement the corresponding logic operation.

For example, when the and operation needs to be performed on "1001", 4 input memristors 112 are selected from the N input memristors 112, the logic states of 2 of the input memristors 112 are set to 1, the logic states of the other 2 input memristors 112 are set to 0, the logic state of the output memristor 12 is set to logic 0, and then the N switches 111 are controlled to operate, so that the four input memristors 112 and the output memristor 12 are combined to realize the and operation, and the output logic state is logic 0.

When the input memristor 112 is selected, alternate current selection can be performed from the N input memristors 112, for example, when the first logic operation is performed, the first four input memristors 112 are selected, and when the second logic operation is performed, the other four input memristors 112 are selected, the selectivity of the logic gate circuit in the application to the input memristors 112 is beneficial to balancing the abrasion of the input memristors 112, the damage of the common input memristors 112 is avoided, the common input memristors 112 are not used, and the service life of the whole logic gate circuit is further prolonged.

Of course, the specific implementation is not limited to the above examples, and the present application is not limited thereto.

In summary, the logic operation corresponding to the user instruction can be realized based on the user instruction in the application, and the reliability of the realization mode is high.

As a preferred embodiment, the control module 13 is further configured to set the logic states of the N input memristors 112 to preset logic in advance;

based on the user instruction, the N switches 111 in the input module 11 are controlled to act and the logic states of the N input memristors 112 are controlled to adjust the resistance of the input module 11, and the logic states of the output memristors 12 are also controlled to make the logic gate circuit realize logic operation, including:

setting the logic state of the output memristor 12 and determining the number and logic states of the input memristors 112 based on the user instructions;

selecting a determined number of input memristors 112 from the N input memristors 112, wherein the preset logic corresponds to the user instruction;

the N switches 111 are controlled to operate to adjust the resistance of the input module 11, so that the selected input memristor 112 and the output memristor realize logic operation.

The present embodiment is directed to another specific implementation manner of controlling the actions of the N switches 111 in the input module 11 and controlling the logic states of the N input memristors 112 and the output memristors 12 based on the user instruction, and specifically, the N input memristors 112 may be firstly set to be a preset logic (where part of the input memristors 112 is set to be logic 1 and part of the input memristors 112 is set to be logic 0), then the logic state of the output memristors 12 is set according to the user instruction (for example, set to be logic 0 during the and operation, or set to be logic 1 during the operation), and the number of inputs that need to be logically operated and the logic state that needs to be logically operated are determined based on the user instruction, then the determined number of input memristors 112 and the preset logic of the input memristors 112 corresponding to the user instruction are selected from the N input memristors 112, and then the N switches 111 are controlled to act, so that the selected input memristor 112 and the output memristor 12 combine to implement the corresponding logical operation.

For example, when the and operation needs to be performed on "1001", 4 input memristors 112 are selected from the N input memristors 112, the logic states of the 4 input memristors 112 are 2

logic

1 and 2 logic 0, respectively, the logic state of the output memristor 12 is set to be logic 0, and then the N switches 111 are controlled to operate, so that the four input memristors 112 and the output memristor 12 are combined to realize the and operation, and the output logic state is logic 0.

In this embodiment, when the input memristor 112 is selected, alternate selection from the N input memristors 112 may also be performed, for example, by taking "1001" as an example, when the logic operation is performed for the first time, the first 2 input memristors 112 with logic 1 and the first 2 input memristors 112 with logic 0 are selected, and when the logic operation is performed for the second time, the next 2 input memristors 112 with logic 1 and the next 2 input memristors 112 with logic 0 are selected.

In addition, in the present application, the N input memristors 112 are set as the preset logic, and the logic states of the N input memristors 112 may be set according to a certain logic state ratio, for example, the number ratio of logic 1 to logic 0 in the N input memristors 112 is 1: 1. Specifically, the specific way to set the logic states of the N input memristors 112 to the preset logic may be to number the N input memristors 112, then set the input memristors 112 of the technical labels to logic 1, and set the input memristors 112 of the even numbers to logic 0, at this time, if the logic operation is to be performed on "1010", the input memristors 112 of the

numbers

1, 2, 3, and 4 may be directly selected.

Of course, the specific implementation is not limited to the above example, and other implementations are possible, and the present application is not limited thereto.

In summary, the present embodiment can also implement the logic operation corresponding to the user instruction based on the user instruction, and the implementation method has higher reliability.

As a preferred embodiment, the input memristor 112 and the output memristor 12 are both threshold-type memristors, which are logic 1 when the voltage across the memristor is greater than a first threshold voltage, and logic 0 when the voltage across the memristor is less than a second threshold voltage, where the first threshold voltage is greater than the second threshold voltage;

controlling the logic states of the N input memristors 112 and controlling the logic states of the output memristors 12 includes:

the voltage values applied across the N input memristors 112 and the output memristor 12, respectively, are controlled to be greater than a first threshold voltage or less than a second threshold voltage.

The embodiment aims to provide a specific control mode of the input memristor 112 and the output memristor 12, and when the memristor is a threshold-type memristor, the jump of the logic state of the memristor is controlled by controlling the voltage value change at two ends of the memristor. Specifically, when the voltage value across the memristor is greater than a first threshold voltage, the logic state of the memristor is logic 1, and when the voltage across the memristor is less than a second threshold voltage, the logic state of the memristor is logic 0. Therefore, in the present application, the logic state of each memristor is controlled by controlling the voltage value applied to both ends of the memristor to be greater than the first threshold voltage or less than the second threshold voltage, so as to control the logic state of the memristor to be logic 1 or logic 0.

In a preferred embodiment, the logic gate circuit is an and circuit;

the positive electrode of the first input memristor 112 is connected with a power supply, the positive electrode of the (i + 1) th input memristor 112 is connected with the negative electrode of the ith input memristor 112, the negative electrode of the Nth input memristor 112 is connected with the positive electrode of the output memristor 12, the negative electrode of the output memristor 12 is the output end of a logic gate circuit, the switch 111 is connected in parallel with the input memristor 112 corresponding to the switch, and i is an integer not less than 1 and less than N;

setting the logic state of the output memristor 12 based on the user instructions includes:

setting the logic state of the output memristor 12 to logic 0 based on the user instruction;

controlling the action of the N switches 111 includes:

the switch 111 corresponding to the selected input memristor 112 is controlled to be opened and the remaining switches 111 are controlled to be closed.

Referring to fig. 2, fig. 2 is a schematic diagram of a logic gate circuit for implementing and operation according to the present invention, based on a manner of controlling logic states of the input memristor 112 and the output memristor 12, i.e., controlling voltage values applied to two ends of the input memristor 112 and the output memristor 12.

In this embodiment, it is intended to provide a logic gate circuit for implementing and operation, that is, the connection relationship between each device when the logic gate circuit is an and circuit, and under the connection diagram of fig. 2, the steps of performing and operation may specifically be: 1) setting output memristors 12M based on user instructions_OUTResistance value of R_OFFThat is, the output memristor 12 is set to logic 0; 2) determining the number of input memristors 112 based on the user instructions, controlling switches 111 corresponding to the determined input memristors 112 to be turned off, and controlling the rest switches 111 to be turned on, and setting logic states corresponding to the user instructions for the determined input memristors 112; 3) the output voltage of the power supply is set toV₀At this time V_{T_ON}<V₀<2V_{T_ON}. Wherein, V_{T_ON}Is a first threshold voltage.

At this time, correspondingly, taking the specific implementation of the switch 111 as NMOS and selecting 3 input memristors 112 as an example, the logic state of the output memristor 12 is first set to logic 0, and then 3 input memristors 112 are selected, for example, M in the diagram X_{IN_1}、M_{IN_2}、M_{IN_3}Set to the corresponding 3 logic states, and then set the gate voltages of the corresponding NMOS of the three memristors to low, i.e., V_{SEL_1}、V_{SEL_2}、V_{SEL_3}Set to low, the corresponding NMOS transistor is turned off, and the corresponding input memristor 112M_{IN_1}、M_{IN_2}、M_{IN_3}And participating in the logic operation, the gate voltages of the NMOS transistors corresponding to the remaining input memristors 112 are set to a high level, so that the NMOS transistors are turned on, and the corresponding input memristors 112 are short-circuited. Assuming that the logic states of the three input memristors 112 are "000", the corresponding input memristors 112 all have resistance values of R_OFFAt this time, the three input memristors 112 and the output memristor 12 are connected in series, and the resistance values are all R_OFFThus, the voltage sustained across the output memristor 12 is V₀/4, not reaching the output memristor 12 from R_OFFConversion to R_ONThe logic state of the output memristor 12 is still "0". Similarly, if the logic states of the three input memristors 112 are "100", "010", or "001", the voltage across the output memristor 12 is approximately V₀A/3; if the logic states of the three input memristors 112 are "110", "011" or "101", the voltage across the output memristor 12 is approximately V₀/2, the voltages at the two ends of the output memristor 12 under the conditions are all smaller than V_{T_ON}Without reaching the output memristor 12 from R_OFFConversion to R_ONThe logic state of the output memristor 12 is still "0". Only when the logic state of the 3 input memristors 112 is "111", the voltage across the output memristor 12 is approximately V0, and the voltage across the output memristor 12 is greater than V_{T_ON}Thereby realizing the output memristorThe logic state of 12 transitions from "0" to "1". The inputs and outputs are in accordance with the truth table of the three-input AND gate, thereby realizing the function of the AND logic gate.

In summary, the logic gate circuit provided in this embodiment can implement the logic of the and circuit, and the stability of the logic gate circuit is better, the power consumption is smaller, and further, a computation architecture integrating computation can be constructed.

In a preferred embodiment, the logic gate circuit is a nand circuit;

the positive electrode of the first input memristor 112 is connected with a power supply, the positive electrode of the (i + 1) th input memristor 112 is connected with the negative electrode of the ith input memristor 112, the negative electrode of the Nth input memristor 112 is connected with the negative electrode of the output memristor 12, the positive electrode of the output memristor 12 is the output end of a logic gate circuit, the switch 111 is connected in parallel with the input memristor 112 corresponding to the switch, and i is an integer not less than 1 and less than N;

setting the logic state of the output memristor 12 to logic 1 based on the user instruction;

controlling the action of the N switches 111 includes:

Referring to fig. 3, fig. 3 is a schematic diagram of a logic gate circuit for implementing nand operation according to the present invention.

In this embodiment, it is intended to provide a logic gate circuit to implement nand operation, that is, the connection relationship between devices when the logic gate circuit is a nand circuit, and under the connection diagram of fig. 3, the step of performing the nand operation may specifically be: 1) setting output memristors 12M based on user instructions_OUTResistance value of R_ONThat is, the output memristor 12 is set to logic 1; 2) determining the number of input memristors 112 based on the user instructions, controlling switches 111 corresponding to the determined input memristors 112 to be turned off, and controlling the rest switches 111 to be turned on, and setting logic states corresponding to the user instructions for the determined input memristors 112; 3) the output voltage of the power supply is set to V₀Herein, thisTime V₀≤(n+1)V_{T_OFF}. Wherein, V_{T_OFF}Is the second threshold voltage.

At this time, taking the specific implementation of the switch 111 as NMOS and selecting 3 input memristors 112 as an example, the logic state of the output memristor 12 is first set to logic 1. Then select 3 input memristors 112, e.g., M in FIG. 3_{IN_1}、M_{IN_2}、M_{IN_3}Set to the corresponding 3 logic states, and then set the gate voltages of the corresponding NMOS of the three memristors to low, i.e., V_{SEL_1}、V_{SEL_2}、V_{SEL_3}Set to low, the corresponding NMOS transistor is turned off, and the corresponding input memristor 112M_{IN_1}、M_{IN_2}、M_{IN_3}And participating in the logic operation, the gate voltages of the NMOS transistors corresponding to the remaining input memristors 112 are set to a high level, so that the NMOS transistors are turned on, and the corresponding input memristors 112 are short-circuited. Assuming that three logic values of the input signal are "000", the corresponding input memristors 112 are all R in resistance_OFFAt this time, the three input memristors 112 and the output memristor 12 are connected in series, and R_OFF>>R_ONTherefore, the voltage across the output memristor 12 is approximately 0, not enough to cause the output memristor 12 to change from R_ONConversion to R_OFFThe logic state of the output memristor 12 is still "1". Similarly, if the logic value of the input signal is "100", "010", "001", "110", "011", or "101", at least one input memristor 112 has a resistance value R_OFFTherefore, the voltage across the output memristor 12 is still approximately 0, and the voltage across the output memristor 12 is smaller than V in several cases_{T_OFF}Without reaching the output memristor 12 from R_ONConversion to R_OFFThe logic state of the output memristor 12 is still "1". Only when the input logic is '111', the resistance values of the input memristor 112 and the output memristor 12 are both R_OFFThe voltage across the output memristor 12 is V₀/4, a threshold voltage V is reached at which the logic state changes from "1" to "0_{T_OFF}The output memristor 12 logic state changes to "0". Input and output of the above signalsAnd a truth table which accords with the three-input NAND gate is obtained, so that the function of the NAND logic gate is realized.

In summary, the logic gate circuit provided in this embodiment can implement the logic of the nand circuit, and the logic gate circuit has better stability and lower power consumption, and further can construct a computation-integrated computing architecture.

In a preferred embodiment, the logic gate circuit is an or circuit;

the first ends of the N switches 111 are connected with a power supply, the second ends of the N switches 111 are connected with the anodes of the input memristors 112 corresponding to the second ends of the N switches 111, the cathodes of the N input memristors 112 are connected with the anode of the output memristor 12, and the cathode of the output memristor 12 is the output end of the logic gate circuit;

controlling the action of the N switches 111 includes:

the switch 111 corresponding to the selected input memristor 112 is controlled to be closed and the remaining switches 111 are controlled to be opened.

Referring to fig. 4, fig. 4 is a schematic diagram of a logic gate circuit for implementing an or operation according to the present invention.

In this embodiment, it is intended to provide an or operation implemented by a logic gate circuit, that is, the connection relationship between devices when the logic gate circuit is an or circuit, and in the connection diagram of fig. 4, the step of performing the or operation may specifically be: 1) setting output memristors 12M based on user instructions_OUTResistance value of R_OFFThat is, the output memristor 12 is set to logic 0; 2) determining the number of input memristors 112 based on the user instructions, controlling switches 111 corresponding to the determined input memristors 112 to be turned off, and controlling the rest switches 111 to be turned on, and setting logic states corresponding to the user instructions for the determined input memristors 112; 3) the output voltage of the power supply is set to V₀At this time V_{T_ON}<V₀<(n+1)/n·V_{T_ON}. Wherein, V_{T_ON}Is a first threshold voltage, V_{T_OFF}Is the second threshold voltage.

At this time, correspondingly, taking the specific implementation of the switch 111 as NMOS and selecting 3 input memristors 112 as an example, the logic state of the output memristor 12 is first set to logic 0, and then 3 input memristors 112, for example, M, are selected_{IN_1}、M_{IN_2}、M_{IN_3}And set to 3 input states corresponding to the user command, and then set the gate voltages of the NMOS corresponding to the three input memristors 112 to a high level, that is, V is set_{SEL_1}、V_{SEL_2}、V_{SEL_3}Set to high level, NMOS transistor is turned on, and corresponding input memristor 112M_{IN_1}、M_{IN_2}、M_{IN_3}And participating in logic operation, setting the grid voltage of the rest NMOS tubes to be low level, and turning off the NMOS tubes to open the branch where the corresponding memristor is located. Assuming that the three logic states of the input memristor 112 are "000", the corresponding input memristors 112 all have resistance values of R_OFFAt this time, the resistance value of the three input memristors 112 after being connected in parallel is R_OFF/3, the voltage across the output memristor 12 is therefore 3V₀/4, not reaching the output memristor 12 from R_OFFConversion to R_ONThe logic state of the output memristor 12 is still "0". If the logic value of the input signal is "100", "010", "001", "110", "011", "101", or "111", the resistance value of the input memristor 112 after being connected in parallel will be smaller than R_ONThus, the voltage across the output memristor 12 is approximately V₀To achieve the purpose that the output memristor 12 is formed by R_OFFConversion to R_ONThe logic state of the output memristor 12 becomes "1". The input and output of the above signals are in accordance with the truth table of the three-input OR gate, thereby realizing the function of the OR logic gate.

In summary, the logic gate circuit provided in this embodiment can implement the logic of an or circuit, and the stability of the logic gate circuit is better, the power consumption is smaller, and further, a computational architecture integrating computation can be constructed.

In a preferred embodiment, the logic gate circuit is a nor circuit;

first ends of the N switches 111 are connected with a power supply, second ends of the N switches 111 are connected with anodes of input memristors 112 corresponding to the N switches, cathodes of the N input memristors 112 are connected with cathodes of output memristors 12, and the anodes of the output memristors 12 are output ends of logic gate circuits;

controlling the action of the N switches 111 includes:

Referring to fig. 5, fig. 5 is a schematic diagram of a logic gate circuit for implementing nor operation according to the present invention.

In this embodiment, it is intended to provide a logic gate circuit for implementing nor operation, that is, the connection relationship between devices when the logic gate circuit is a nor circuit, and in the connection diagram of fig. 5, the step of performing the nor operation may specifically be: 1) setting output memristors 12M based on user instructions_OUTResistance value of R_ONThat is, the output memristor 12 is set to logic 1; 2) determining the number of input memristors 112 based on the user instructions, controlling switches 111 corresponding to the determined input memristors 112 to be turned off, and controlling the rest switches 111 to be turned on, and setting logic states corresponding to the user instructions for the determined input memristors 112; 3) the output voltage of the power supply is set to V₀At this time V_{T_OFF}<V₀<2V_{T_OFF}. Wherein, V_{T_OFF}Is the second threshold voltage.

At this time, correspondingly, taking the specific implementation of the switch 111 as NMOS and selecting 3 input memristors 112 as an example, the logic state of the output memristor 12 is first set to logic 1, and then 3 input memristors 112, for example, M, are selected_{IN_1}、M_{IN_2}、M_{IN_3}And set to 3 input states corresponding to the user command, and then set the gate voltages of the NMOS corresponding to the three input memristors 112 to high level, the NMOS transistor is turned on, and the corresponding input memristor 112M_{IN_1}、M_{IN_2}、M_{IN_3}And participating in logic operation, setting the gate voltages of the rest NMOS tubes to be low levels, and turning off the NMOS tubes to open the branches where the corresponding input memristors 112 are located. Assuming that the three logic states of the input memristor 112 are "000", the corresponding input memristors 112 all have resistance values of R_OFFAt this time, the resistance value of the three input memristors 112 after being connected in parallel is R_OFF/3, but R_OFF>>R_ONTherefore, the voltage across the output memristor 12 is approximately 0, not enough to cause the output memristor 12 to change from R_ONConversion to R_OFFThe logic state of the output memristor 12 is still "1". If the logic value of the input memristor 112 is "100", "010", "001", "110", "011" or "101", the resistance value of the input memristor 112 after being connected in parallel will be smaller than R_ONThus, the voltage across the output memristor 12 is approximately V₀/2, the output memristor 12 is enabled to be formed by R_ONConversion to R_OFFSo the logic state of the output memristor 12 becomes "0". If the logic value of the input signal is '111', the voltage across the output memristor 12 is approximately 3V₀/4, the output memristor 12 is enabled to be formed by R_ONConversion to R_OFFSo the logic state of the output memristor 12 becomes "0". The input and output of the above signals are in accordance with the truth table of the three-input NOR gate, thereby realizing the function of the NOR logic gate.

In summary, the logic gate circuit provided in this embodiment can implement the logic of the nor circuit, and the stability of the logic gate circuit is better, the power consumption is smaller, and further, a computational architecture integrating computation can be constructed.

In addition, an output module can also be connected to the output end of the input module 11, and the output module includes 2

output memristors

12 and 2 output switches, where one end of each output switch is connected to the output end of the input module 11, the other end of the first output switch is connected to the positive electrode of the corresponding output memristor 12, the negative electrode of the output memristor 12 is grounded, the other end of the second output switch is connected to the negative electrode of the corresponding output memristor 12, and the positive electrode of the output memristor 12 is grounded.

And when the connection relation of the input module 11 is the connection relation of the input module 11 corresponding to the circuit or the connection relation of the input module 11 is the connection relation of the input module 11 corresponding to the OR circuit, controlling the first output switch to be closed and the second output switch to be opened. When the and operation or the or operation is required, the switching operation of the input block 11 in the corresponding circuit and the logic state of each input memristor 112 are controlled.

Similarly, when the connection relationship of the input module 11 is the connection relationship of the input module 11 corresponding to the nand circuit, or the connection relationship of the input module 11 is the connection relationship of the input module 11 corresponding to the nand circuit, the first output switch is controlled to be opened, and the second output switch is controlled to be closed. When the nand operation or the nor operation is required, the switching operation of the input block 11 in the corresponding circuit and the logic state of each input memristor 112 are controlled.

It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The logic gate circuit is characterized by comprising an input module, an output memristor and a control module, wherein the input module comprises N input memristors and N switches, and N is an integer not less than 2;

2. The logic gate circuit of claim 1, wherein the control module is specifically configured to set a logic state of the output memristor and determine a number and a logic state of the input memristors based on the user command, select a determined number of the input memristors from the N input memristors, set a logic state corresponding to the user command for the selected input memristors, and control the N switching actions to adjust a resistance of the input module, so that the selected input memristors and the output memristors implement a logic operation.

3. The logic gate circuit of claim 1, in which the control module is further to pre-set the logic states of the N input memristors to a pre-set logic;

4. The logic gate circuit of claim 2, wherein the logic gate circuit is an and circuit;

controlling N of said switching actions, including:

5. The logic gate circuit of claim 2, wherein the logic gate circuit is a nand circuit;

controlling N of said switching actions, including:

6. The logic gate circuit of claim 2, wherein the logic gate circuit is an or circuit;

controlling N of said switching actions, including:

7. The logic gate circuit of claim 2, wherein the logic gate circuit is a nor circuit;

controlling N of said switching actions, including:

8. The logic gate circuit of claim 1, wherein the switch is a metal oxide semiconductor field effect transistor (MOS) transistor or a triode.

9. The logic gate circuit of claim 8, wherein the switch is an N-channel metal oxide semiconductor field effect transistor (NMOS).

10. The logic gate circuit of any of claims 1-9, wherein the input memristor and the output memristor are both threshold-type memristors, logic 1 when a voltage across themselves is greater than a first threshold voltage, logic 0 when a voltage across themselves is less than a second threshold voltage, the first threshold voltage being greater than the second threshold voltage;