CN114285317A - High-stability pulse current generation circuit - Google Patents
High-stability pulse current generation circuit Download PDFInfo
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- CN114285317A CN114285317A CN202111648282.2A CN202111648282A CN114285317A CN 114285317 A CN114285317 A CN 114285317A CN 202111648282 A CN202111648282 A CN 202111648282A CN 114285317 A CN114285317 A CN 114285317A
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Abstract
The invention discloses a high-stability pulse current generating circuit, which belongs to the technical field of electronic equipment and is structurally provided with a frequency setting module (1), a current output module (2), a current sampling module (3), an amplitude measuring module (4), an amplitude control module (5), a duty ratio measuring module (6) and a pulse width control module (7). The invention has the advantages of stable and adjustable output pulse width and current peak value, and the like.
Description
Technical Field
The invention belongs to the technical field of electronic equipment, and particularly relates to a high-stability pulse current generating circuit.
Background
Current sources have important applications in many fields such as LED driving, laser driving, sensor driving, and driving of various glow discharge light sources. The high-power narrow-pulse current source is more convenient to apply particularly to the aspects of semiconductor laser driving and the like. A pulsed current source refers to a current pulse capable of generating a current pulse on a load of controllable amplitude and pulse width.
In a pulsed current source, pulse height (i.e., peak current), pulse width, repetition rate, rise time, fall time are several important parameters that measure the performance of a pulsed current source. The pulse current source generally comprises a pulse trigger circuit, a pulse shaping circuit, a power driving circuit and the like, wherein the pulse trigger circuit is used for generating a signal source with adjustable frequency, the prior art is mature, and the pulse current source can be realized by a 555 timer, a multivibrator, a voltage-controlled oscillator and the like; the pulse shaping circuit is used for shaping a signal generated by the pulse trigger circuit into a narrow pulse, the pulse shaping circuit formed by the monostable trigger can change the pulse width by changing an external resistor and a capacitor to realize the ms or ns-level narrow pulse, but the pulse power is small, the current driving of a load with high power requirement is difficult to realize, and the power driving circuit amplifies the narrow pulse shaped by a previous stage into a current pulse with high power.
The prior art closest to the present invention is the early research result of the applicant's topic group "pulse constant current source theory and technology research for semiconductor laser (the thesis of doctor king sunny, jilin university)", and chapter 3 of the document discloses a pulse constant current source circuit for driving a semiconductor laser (see the original text fig. 3.6), which is composed of a pulse trigger circuit, a pulse shaping module, and a power output module, wherein the power drive module is composed of two-stage power MOSFETs. The above reference has excellent performance when used to drive a semiconductor laser of fixed parameters, and it can be seen from simulation and experimental results that a peak current of up to about 21A can be generated on a load of 1 ohm, and by adjusting the charge and discharge capacitance C5 of the final stage, the output pulse width can be compressed to ns level at a repetition frequency of 10kHz, and the rise and fall time is extremely short.
However, the applications of the above references have great limitations, and the height of the output current may vary when the load varies, and the pulse width of the output current may be affected when the load varies or the repetition frequency is adjusted. This is very disadvantageous if the load has high requirements on the stability of the pulse width or the pulse height, and therefore further improvements are needed in the prior art.
Disclosure of Invention
The technical problem to be solved by the invention is to overcome the defects in the background technology and provide a pulse current generating circuit which has stable frequency, amplitude and pulse width and can be independently adjusted.
The technical problem of the invention is solved by the following technical scheme:
a high-stability pulse current generating circuit is structurally provided with a frequency setting module 1 and a current output module 2, and is characterized in that the structure is also provided with a current sampling module 3, an amplitude measuring module 4, an amplitude control module 5, a duty ratio measuring module 6 and a pulse width control module 7, wherein the frequency setting module is connected with the current output module 2 and the pulse width control module 7, the current output module 2 is connected with the current sampling module 3, the current sampling module 3 is connected with the amplitude measuring module 4 and the duty ratio measuring module 6, the amplitude measuring module 4 is connected with the amplitude control module 5 and the duty ratio measuring module 6, the amplitude control module 5 is connected with the current output module 2, and the pulse width control module 7 is connected with the current output module 2;
the structure of the current output module 2 is that one end of a resistor R1 is connected with one end of a capacitor C2 and is connected with the grid of a field effect transistor Q1, the other end of the resistor R1 is connected with the other end of the capacitor C2 and serves as an input end of the current output module 2 and is marked as a port P2-in1, the port P2-in1 is connected with a pulse voltage signal output end of a frequency setting module 1, and pulse voltage output by the frequency setting module 1 is amplified into high-power current pulse through the current output module 2; the source of the fet Q1 is grounded, the drain is connected to one end of the resistor R2 and the gate of the fet Q2, the other end of the resistor R2 is connected to one end of the capacitor C1 and the source of the fet Q2, and is used as the second input end of the current output module 2, which is denoted as port P2-in2 and is connected to the output end of the amplitude control module 5, the other end of the capacitor C1 is grounded, the drain of the fet Q2 is connected to one end of the resistor R3 and one end of the capacitor C3, the other end of the resistor R3 is grounded, the other end of the capacitor C3 is connected to one end of the resistor R4, one end of the load and the cathode of the diode D1, the other end of the resistor R4 is used as the third input end of the current output module 2, which is denoted as port P2-in3 and is connected to the output end of the pulse width control module 7, the anode of the diode D1 is grounded, the other end of the load is connected to one end of the sampling resistor Rs and is used as the output end of the current output module 2, the port P2-out is connected with the input end of the current sampling module 3, and the other end of the sampling resistor Rs is grounded; wherein the field effect transistor Q1 is N-type field effect transistor, and the field effect transistor Q2 is P-type field effect transistor;
the current sampling module 3 has a structure that a non-inverting input end of the operational amplifier U1A is used as an input end of the current sampling module 3, is recorded as a port P3-in and is connected with a port P2-out of the current output module 2, an inverting input end of the operational amplifier U1A is connected with one end of a resistor R5, one end of a resistor R6 and one end of a resistor R7, the other end of the resistor R6 is connected with an output end of the operational amplifier U1A, is used as an output end of the current sampling module 3, is recorded as a port P3-out and is connected with the amplitude measuring module 4 and the duty ratio measuring module 6; the other end of the resistor R5 is connected with one end of a resistor R8, one end of a resistor R10 and the inverting input end of the operational amplifier U1B, the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1B and is grounded, the other end of the resistor R8 is connected with one end of an adjustable resistor R9, and the other end of the adjustable resistor R9 is connected with the other end of a resistor R7 and the output end of the operational amplifier U1B;
the structure of the amplitude measuring module 4 is that the anode of the diode D2 is used as the input end of the amplitude measuring module 4, which is marked as a port P4-in, and is connected with the port P3-out of the current sampling module 3, the cathode of the diode D2 is connected with one end of the capacitor C4, one end of the resistor R11 and the non-inverting input end of the operational amplifier U2A, the other end of the resistor R11 is grounded with the other end of the capacitor C4, the inverting input end of the operational amplifier U2A is connected with the output end, which is used as the output end of the amplitude measuring module 4, which is marked as a port P4-out, and is connected with the amplitude control module 5 and the duty ratio measuring module 6;
the structure of the amplitude control module 5 is that one end of a resistor R19 is used as an input end of the amplitude control module 5, which is recorded as a port P5-in, and is connected with a port P4-out of the amplitude measurement module 4, the other end of the resistor R19 is connected with one end of a resistor R21 and a non-inverting input end of an operational amplifier U3B, the other end of the resistor R21 is grounded, an inverting input end of the operational amplifier U3B is connected with one end of a resistor R17 and one end of a resistor R18, the other end of the resistor R17 is connected with a sliding terminal of a sliding rheostat W1, one end of the sliding resistor is grounded, the other end of the sliding resistor is connected with a cathode of a 5.1V zener diode D3 and one end of a resistor R20, an anode of the zener diode D3 is grounded, the other end of the resistor R20 is connected with a +12V power supply, the other end of the resistor R18 is connected with an output end of the operational amplifier U3B and an inverting input end of the operational amplifier U3A, one end of a capacitor C5 and one end of the resistor R12 are grounded, the non-inverting input end of the operational amplifier U828653 and the non-inverting input end of the operational amplifier U3, the other end of the resistor R12 is connected with one end of a resistor R13, one end of a resistor R14 and the inverting input end of the operational amplifier U2B, the other end of the resistor R14 is connected with one end of a resistor R15, one end of a resistor R16 and the output end of the operational amplifier U2B, the other end of the resistor R15 and the other end of the resistor R13 are both connected with a +12V power supply, the other end of the resistor R16 is connected with the non-inverting input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with the gate of an N-type field effect transistor Q3, the drain of the field effect transistor Q3 is connected with the power supply VPP, the source is connected with one end of an inductor L1 and the cathode of a diode D4, the anode of the diode D4 is grounded, the other end of the inductor L1 is connected with one end of a capacitor C6 and used as the output end of the amplitude control module 5 and is marked as a port P5-out, and is connected with a port P2-in2 of the current output module, and the other end of the capacitor C6 is grounded;
the structure of the duty ratio measuring module 6 is that the non-inverting input terminal of the operational amplifier U4A is used as an input terminal of the duty ratio measuring module 6, which is marked as a port P6-in1 and is connected with a port P3-out of the current sampling module 3, the inverting input terminal of the operational amplifier U4A is connected with one end of a resistor R27 and one end of a resistor R28, the other end of the resistor R28 is grounded, the other end of the resistor R27 is used as the other input terminal of the duty ratio measuring module 6, which is marked as a port P6-in2 and is connected with a port P4-out of the amplitude measuring module 4, the output terminal of the operational amplifier U4A is connected with the cathode of a diode D6 and the cathode of a diode D5, the anode of a diode D6 is grounded, the anode of the diode D5 is connected with one end of a resistor R26 and one end of an inductor L2, the other end of the resistor R26 is connected with one end of a thermistor R24 and the output terminal of the inverting input terminal 36 24 2 of the operational amplifier U4B, and the inverting input terminal 23 of the resistor R36 24, the other end of the resistor R23 is grounded, the non-inverting input end of the operational amplifier U4B is connected with one end of a resistor R22, one end of a capacitor C7 and one end of a capacitor C8, the other end of the resistor R22 and the other end of a capacitor C7 are both grounded, the other end of the capacitor C8 is connected with one end of a resistor R25, the other end of the resistor R25 is connected with the output end of the operational amplifier U4B, the other end of an inductor L2 is connected with one end of a capacitor C9, the other end of the capacitor C9 is connected with one end of a resistor R30 and the anode of a diode D7, the other end of the resistor R30 is grounded, the cathode of a diode D7 is connected with the non-inverting input end of the operational amplifier U5A, one end of the resistor R29 and one end of the capacitor C10, the other end of the resistor R29 and the other end of the capacitor C10 are both grounded, the inverting input end of the operational amplifier U5A is connected with the output end as the output end of the duty ratio measuring module 6, and the port P6-out is connected with the pulse width control module;
the pulse width control module 7 is configured such that one end of a resistor R33 is connected to an inverting input terminal of an operational amplifier U6A and one end of an adjustable resistor R32, the other end of the resistor R33 serves as an input terminal of the pulse width control module 7, which is denoted as a port P7-in1, which is connected to a port P6-out of the duty ratio measurement module 6, an non-inverting input terminal of the operational amplifier U6A is connected to one end of a resistor R34, the other end of the resistor R34 is grounded, the other end of the adjustable resistor R32 is connected to one end of a resistor R31, the other end of the resistor R31 is connected to an output terminal of an analog multiplier U7, one input terminal of the analog multiplier U7 serves as a second input terminal of the pulse width control module 7, which is denoted as a port P7-in2, which is connected to a voltage port for controlling frequency in the frequency setting module 1, the other input terminal of the analog multiplier U7 is connected to one end of a capacitor C11, an output terminal of the operational amplifier U6A, and the other end of the inverting input terminal of the capacitor C B, the output end of the pulse width control module 7 is marked as a port P7-out and is connected with a port P2-in3 of the current output module 2, the non-inverting input end of the operational amplifier U6B is connected with the slide wire end of the slide rheostat W2, one end of the slide rheostat W2 is grounded, the other end of the slide rheostat W2 is connected with one end of a resistor R35 and the anode of a 5.1V voltage stabilizing diode D8, the other end of the resistor R35 is connected with a-12V power supply, and the cathode of a voltage stabilizing diode D8 is grounded; the operational amplifier U6A and the operational amplifier U6B are two units integrating double operational amplifiers and adopt +12V and-12V double power supplies for power supply.
The size range of the power supply VPP in the amplitude control module 5 of the present invention is preferably +12V to + 200V.
The frequency setting module 1 of the present invention belongs to the prior art, and can be designed according to the conventional scheme, and the basic requirement is to be able to generate a frequency-controlled voltage pulse signal (such as a voltage-controlled oscillator), and the frequency-controlled voltage signal is also connected to the port P7-in2 of the pulse width control module 7, so as to provide the frequency parameter for the pulse width control module 7, so as to convert the duty ratio into the pulse width.
Has the advantages that:
1. the invention dynamically controls the power supply voltage of the final stage field effect transistor through the output current sampling result, so that the output current peak value is not influenced by load change, and the real pulse constant current output is realized.
2. The invention adds a current compensation branch circuit in the current output module to offset the change of the final stage current charge-discharge time constant caused by load change or frequency change, so that the pulse width of the output current is constant.
3. The invention designs a current sampling module with ultrahigh input impedance and an amplitude measuring module with ultralow output impedance so as to realize sampling of ultra-narrow current pulses and convert the current amplitude into a direct-current voltage signal without loss.
4. The invention designs a unique pulse width control module, and realizes the purpose of controlling the pulse width by using the measurement result of the duty ratio.
5. The invention skillfully utilizes the result of the amplitude measuring module and the result of the current sampling module to realize the accurate measurement of the duty ratio of the output current. When different definitions are carried out on the duty ratio, the circuit can be quickly matched again by conveniently adjusting the variable resistor.
Description of the drawings:
fig. 1 is a block diagram of the overall structure of the present invention.
Fig. 2 is a schematic circuit diagram of a current output module.
Fig. 3 is a schematic circuit diagram of a current sampling module.
Fig. 4 is a schematic circuit diagram of an amplitude measurement module.
Fig. 5 is a schematic circuit diagram of an amplitude control module.
Fig. 6 is a schematic circuit diagram of a duty cycle measurement module.
Fig. 7 is a schematic circuit diagram of a pulse width control module.
Detailed Description
The detailed structure and operation principle of each circuit of the present invention will be described with reference to the accompanying drawings. The parameters indicated in the figures are preferred circuit parameters for the various embodiments, but the scope of the present invention is not limited to these parameters.
Example 1 Overall System Structure and Overall working Process
As shown in fig. 1, the system structure includes a frequency setting module 1 and a current output module 2, and is characterized in that the structure further includes a current sampling module 3, an amplitude measuring module 4, an amplitude control module 5, a duty ratio measuring module 6 and a pulse width control module 7, the frequency setting module is connected to the current output module 2 and the pulse width control module 7, the current output module 2 is connected to the current sampling module 3, the current sampling module 3 is connected to the amplitude measuring module 4 and the duty ratio measuring module 6, the amplitude measuring module 4 is connected to the amplitude control module 5 and the duty ratio measuring module 6, the amplitude control module 5 is connected to the current output module 2, and the pulse width control module 7 is connected to the current output module 2.
The frequency setting module 1 can be designed by conventional means, for example, a voltage-controlled oscillator is used as a pulse trigger circuit to generate an ac signal with frequency controlled by voltage, a pulse shaping circuit (such as a monostable trigger) is used to shape the ac signal into a narrow pulse voltage signal with a duty ratio less than 50%, the current output module 2 amplifies the narrow pulse voltage signal into a high-power narrow pulse current signal and outputs the high-power narrow pulse current signal to a load, the current sampling module 3 is responsible for sampling the current flowing through the load and measuring the peak current through the amplitude measuring module 4 to present the peak current in a dc voltage manner, the amplitude control module 5 automatically adjusts the power supply voltage of a final stage field effect tube in the current output module 2 according to the result output by the amplitude measuring module 4 to realize that the current peak value finally flowing through the load is constant and controllable, the duty ratio measuring module 6 measures the duty ratio of the output current according to the result output by the amplitude measuring module 4 and the current sampling module 3, the pulse width control module 7 automatically adjusts the current of the current compensation branch in the current output module 2 according to the measurement result provided by the duty ratio measurement module 6 and the control voltage parameter provided by the frequency setting module 1 and reflecting the frequency, so as to stabilize the charging and discharging time of the capacitor and further achieve the purpose of stabilizing the pulse width of the output current.
The structure of the current output module 2 is shown in fig. 2, one end of a resistor R1 is connected with one end of a capacitor C2 and is connected with a gate of a field effect transistor Q1, the other end of the resistor R1 is connected with the other end of the capacitor C2 and serves as an input end of the current output module 2, which is marked as a port P2-in1, the port P2-in1 is connected with a pulse voltage signal output end of a frequency setting module 1, and pulse voltage output by the frequency setting module 1 is amplified into high-power current pulses through the current output module 2; the source of the fet Q1 is grounded, the drain is connected to one end of the resistor R2 and the gate of the fet Q2, the other end of the resistor R2 is connected to one end of the capacitor C1 and the source of the fet Q2, and is used as the second input end of the current output module 2, which is denoted as port P2-in2 and is connected to the output end of the amplitude control module 5, the other end of the capacitor C1 is grounded, the drain of the fet Q2 is connected to one end of the resistor R3 and one end of the capacitor C3, the other end of the resistor R3 is grounded, the other end of the capacitor C3 is connected to one end of the resistor R4, one end of the load and the cathode of the diode D1, the other end of the resistor R4 is used as the third input end of the current output module 2, which is denoted as port P2-in3 and is connected to the output end of the pulse width control module 7, the anode of the diode D1 is grounded, the other end of the load is connected to one end of the sampling resistor Rs and is used as the output end of the current output module 2, the port P2-out is connected with the input end of the current sampling module 3, and the other end of the sampling resistor Rs is grounded; the field effect transistor Q2 is a P-type field effect transistor, wherein the N-type field effect transistor of the field effect transistor Q1 is a P-type field effect transistor.
The current output module 2 is responsible for amplifying the narrow pulse voltage signal generated by the frequency setting module 1 into a high-power current narrow pulse signal, outputting the high-power current narrow pulse signal to a load, combining with the attached figure 2, a resistor R1 and a capacitor C2 form a pulse accelerator, so that the rising edge of an output pulse is further steepened, the field effect transistors Q1 and Q2 form a two-stage amplifying circuit driven by steps, so that the output power is greatly improved, when a trigger pulse arrives, the field effect transistor Q2 is conducted, the left side potential of the capacitor C3 is equal to the voltage potential provided by the ports P2-in2, because the voltages at the two ends of the capacitor cannot be suddenly changed, the right side potential of the C3 is instantly increased to be equal to the voltage potential provided by the ports P2-in2, potential difference is generated at the two sides of the load, and further current from left to right is generated, along with the reverse charging of the capacitor C3, the potential difference at the left and right sides of the C3 is gradually increased, and because the left side potential is kept unchanged under the control of the ports P2-in2, therefore, the right side potential is gradually reduced to 0, no potential difference and no current exist on two sides of the load, the process realizes the purpose of generating pulse current on the load, the peak value of the generated pulse current is controlled by the voltage at the ports P2-in2 and the load + sampling resistor Rs, the pulse width is controlled by the reverse charging time constant of the capacitor C3, in a single loop, the charging time constant is determined by the product of the capacitor and the resistor in the loop, therefore, when the load changes, the time constant is changed inevitably, and the pulse width of the output current is changed, the invention reserves a compensating current branch consisting of R4, the time constant is determined by the capacitor C3 and the current flowing through C3, and the current flowing through C3 is determined by the current flowing through the load branch and the compensating branch together (the diode D1 is in a cut-off state during the period when the right side potential of the capacitor C3 is pulled up, and no current can be seen as no current), therefore, the current of the compensation branch formed by the resistor R4 can balance the change of the charging time constant caused by the change of the load branch current, so that the pulse width of the output current is constant.
The structure of the current sampling module 3 is shown in fig. 3, a non-inverting input terminal of an operational amplifier U1A is used as an input terminal of the current sampling module 3 and is marked as a port P3-in, and is connected with a port P2-out of the current output module 2, an inverting input terminal of the operational amplifier U1A is connected with one end of a resistor R5, one end of a resistor R6 and one end of a resistor R7, the other end of the resistor R6 is connected with an output terminal of the operational amplifier U1A and is used as an output terminal of the current sampling module 3 and is marked as a port P3-out, and is connected with the amplitude measuring module 4 and the duty ratio measuring module 6; the other end of the resistor R5 is connected with one end of a resistor R8, one end of a resistor R10 and the inverting input end of the operational amplifier U1B, the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1B and is grounded, the other end of the resistor R8 is connected with one end of an adjustable resistor R9, and the other end of the adjustable resistor R9 is connected with the other end of a resistor R7 and the output end of the operational amplifier U1B.
The structure of the amplitude measuring module 4 is that the anode of the diode D2 is used as the input end of the amplitude measuring module 4, which is recorded as a port P4-in, and is connected with the port P3-out of the current sampling module 3, the cathode of the diode D2 is connected with one end of the capacitor C4, one end of the resistor R11, and the non-inverting input end of the operational amplifier U2A, the other end of the resistor R11 is grounded with the other end of the capacitor C4, the inverting input end of the operational amplifier U2A is connected with the output end, which is used as the output end of the amplitude measuring module 4, which is recorded as a port P4-out, and is connected with the amplitude control module 5 and the duty ratio measuring module 6.
The current sampling module 3 is a complementary amplification structure formed by two operational amplifiers, has very high input impedance, and is used for performing non-interference sampling on current flowing through a sampling resistor Rs (in a current output module), so that a pulse current signal is converted into a pulse voltage signal with the same characteristics, an adjustable resistor R9 can finely adjust the transmission coefficient of the current sampling module, and the amplitude measuring module 4 extracts the peak value of a pulse and converts the peak value into a direct current voltage signal so as to be convenient for the use of the amplitude control module and the duty ratio measuring module.
The structure of the amplitude control module 5 is that one end of a resistor R19 is used as an input end of the amplitude control module 5, which is recorded as a port P5-in, and is connected with a port P4-out of the amplitude measurement module 4, the other end of the resistor R19 is connected with one end of a resistor R21 and a non-inverting input end of an operational amplifier U3B, the other end of the resistor R21 is grounded, an inverting input end of the operational amplifier U3B is connected with one end of a resistor R17 and one end of a resistor R18, the other end of the resistor R17 is connected with a sliding terminal of a sliding rheostat W1, one end of the sliding resistor is grounded, the other end of the sliding resistor is connected with a cathode of a 5.1V zener diode D3 and one end of a resistor R20, an anode of the zener diode D3 is grounded, the other end of the resistor R20 is connected with a +12V power supply, the other end of the resistor R18 is connected with an output end of the operational amplifier U3B and an inverting input end of the operational amplifier U3A, one end of a capacitor C5 and one end of the resistor R12 are grounded, the non-inverting input end of the operational amplifier U828653 and the non-inverting input end of the operational amplifier U3, the other end of the resistor R12 is connected with one end of a resistor R13, one end of a resistor R14 and the inverting input end of the operational amplifier U2B, the other end of the resistor R14 is connected with one end of a resistor R15, one end of a resistor R16 and the output end of the operational amplifier U2B, the other end of the resistor R15 and the other end of the resistor R13 are both connected with a +12V power supply, the other end of the resistor R16 is connected with the non-inverting input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with the gate of an N-type field effect transistor Q3, the drain of the field effect transistor Q3 is connected with the power supply VPP, the source is connected with one end of an inductor L1 and the cathode of a diode D4, the anode of the diode D4 is grounded, the other end of the inductor L1 is connected with one end of a capacitor C6 and used as the output end of the amplitude control module 5 and is marked as a port P5-out, and is connected with the port P2-in2 of the current output module, and the other end of the capacitor C6 is grounded.
The operational amplifier U2B and the peripheral resistance capacitor form a triangular wave generator, the operational amplifier U3B forms a subtracter, the voltage signal of the port P5-in (provided by the amplitude measuring module 4 and reflecting the peak value of the output current) and the voltage value set by the slide rheostat W1 are subjected to subtraction operation, the operation result is compared with the triangular wave in the operational amplifier U3A to generate a PWM wave for driving the field effect transistor Q3, when the peak value of the output current of the system is increased under certain influence, the voltage output by the subtracter is increased, the duty ratio of the PWM wave output by the U3A is decreased, the power supply provided by the VPP is converted into a lower voltage, the lower voltage is provided to the ports P2-in2 of the current output module 2 through the ports P5-out, and further, the increase of the output current peak value is restrained, and vice versa, the output current peak value is constant, and the size of the power supply VPP can be selected in the range of +12V to +200V according to needs. If the peak value of the output current is artificially changed, the peak value of the output current can be kept constant at another set value by only adjusting the sliding rheostat W1 to change the set voltage value.
The structure of the duty cycle measuring module 6 is shown in fig. 6, a non-inverting input terminal of an operational amplifier U4A serving as an input terminal of the duty cycle measuring module 6 is denoted as a port P6-in1 and connected to a port P3-out of the current sampling module 3, an inverting input terminal of the operational amplifier U4A is connected to one end of a resistor R27 and one end of a resistor R28, the other end of the resistor R28 is grounded, the other end of the resistor R27 serving as another input terminal of the duty cycle measuring module 6 is denoted as a port P6-in2 and connected to a port P4-out of the amplitude measuring module 4, an output terminal of the operational amplifier U4A is connected to a cathode of a diode D6 and a cathode of a diode D5, an anode of a diode D6 is grounded, an anode of a diode D6959 is connected to one end of a resistor R26 and one end of an inductor L2, the other end of the resistor R26 is connected to one end of a thermistor R24 and an inverting input terminal 23 of the thermistor U B, the other end of the resistor R23 is grounded, the non-inverting input end of the operational amplifier U4B is connected to one end of a resistor R22, one end of a capacitor C7 and one end of a capacitor C8, the other end of the resistor R22 and the other end of the capacitor C7 are both grounded, the other end of the capacitor C8 is connected to one end of a resistor R25, the other end of the resistor R25 is connected to the output end of the operational amplifier U4B, the other end of the inductor L2 is connected to one end of a capacitor C9, the other end of the capacitor C9 is connected to one end of a resistor R30 and the anode of a diode D7, the other end of the resistor R30 is grounded, the cathode of a diode D7 is connected to the non-inverting input end of the operational amplifier U5A, one end of the resistor R29 and one end of the capacitor C10, the other end of the resistor R29 and the other end of the capacitor C10 are both grounded, the inverting input end of the operational amplifier U5A is connected to the output end of the duty ratio measuring module 6, and the port P6-out is connected to the pulse width control module.
The current amplitude value (provided by the amplitude measuring module 4) input by the port P6-in2 is divided by the resistors R27 and R28 to obtain a half-peak value of current as a measurement reference of a duty ratio, a current sampling signal (provided by the current sampling module) input by the port P6-in1 is compared with the measurement reference, a switching signal with the amplitude of 12V reflecting the duty ratio is obtained at the output end of the operational amplifier U4A, a 1kHz standard sinusoidal signal generated by the operational amplifier U4B is chopped, a frequency selection network consisting of L2, C9 and R30 selects a low-frequency part, the envelope of the signal subjected to frequency selection after being chopped forms a positive proportional relation with the duty ratio of the switching signal is known by Fourier theorem, and the envelope of the signal subjected to frequency selection after being chopped forms a positive proportional relation with the duty ratio, and a direct current voltage signal reflecting the duty ratio is obtained at the port P6-out by an envelope detector consisting of the diode D7, the capacitor C10, the resistor R29 and the operational amplifier U5A. The measurement of the duty ratio is usually based on the half-peak width of the signal, but in a few scenarios, the measurement reference of the duty ratio can be conveniently changed by adjusting the variable resistor R28 to change the voltage division relation between the variable resistor R28 and the R27, wherein the measurement reference of the duty ratio is also based on 0.7-time peak value or 0.1-time peak value width.
The structure of the pulse width control module 7 is shown in fig. 7, one end of a resistor R33 is connected to an inverting input terminal of an operational amplifier U6A and one end of an adjustable resistor R32, the other end of the resistor R33 is used as one input terminal of the pulse width control module 7 and is marked as a port P7-in1, and is connected to a port P6-out of the duty ratio measurement module 6, a non-inverting input terminal of the operational amplifier U6A is connected to one end of a resistor R34, the other end of the resistor R34 is grounded, the other end of the adjustable resistor R32 is connected to one end of a resistor R31, the other end of the resistor R31 is connected to an output terminal of an analog multiplier U7, one input terminal of an analog multiplier U7 is used as a second input terminal of the pulse width control module 7 and is marked as a port P7-in2, and is connected to a voltage port for controlling frequency in the frequency setting module 1, the other input terminal of the analog multiplier U7 is connected to one end of a capacitor C11, an output terminal of the operational amplifier U6A and the other end of the inverting input terminal of the capacitor C B, the output end of the pulse width control module 7 is marked as a port P7-out and is connected with a port P2-in3 of the current output module 2, the non-inverting input end of the operational amplifier U6B is connected with the slide wire end of the slide rheostat W2, one end of the slide rheostat W2 is grounded, the other end of the slide rheostat W2 is connected with one end of a resistor R35 and the anode of a 5.1V voltage stabilizing diode D8, the other end of the resistor R35 is connected with a-12V power supply, and the cathode of a voltage stabilizing diode D8 is grounded; the operational amplifier U6A and the operational amplifier U6B are two units integrating double operational amplifiers and adopt +12V and-12V double power supplies for power supply.
If the duty ratio of the output current pulse is N, the pulse width is W, the frequency is f, and the period is T, then
W＝N*T＝N/f。
Referring to fig. 7, the voltage at a is 0 due to the virtual short at the two input terminals of the operational amplifier U6A, where Vf reflects the frequency of the output current, the voltage at the ports P7-in1 (provided by the duty cycle measuring module 6) reflects the duty cycle of the output current, the voltage at the ports P7-in2 (provided by the frequency setting module 1) reflects the frequency of the output current, and the output voltage of the analog multiplier U7 is VM＝Vf*VBFrom the node current equation at point A
VN/R33＝-VM/(R31+R32)＝-Vf*VB/(R31+R32)
The set voltage of the sliding rheostat W2 is set to V2(V is shown in the figure)2<0) The input end of the operational amplifier U6B has a virtual short to obtain VB＝V2Thus there are
VN/R33＝-Vf*V2/(R31+R32)
VN/Vf＝-V2*R33/(R31+R32)
And from W ═ N/f, VN/VfThe value of (3) determines the pulse width W of the output current, so that when the values of the resistors R31, R32 and R33 are determined, the pulse width W of the output current is proportional to the set voltage of the sliding rheostat W2 only, and has a proportionality coefficient of-R33/(R31 + R32) regardless of the load size, the frequency size and the like, because V is the value of2<0, ensuring that W is positive. Therefore, the pulse width of the output current can be controlled by adjusting the slide rheostat W2.
The principle of the system for stabilizing the pulse width is as follows: assuming that the output current pulse width is increased due to the frequency change or the load change, the voltage outputted from the port P7-out is decreased, i.e. becomes "more negative", due to the feedback action of the pulse width control module 7, the voltage is decreased, i.e. becomes "more negative", and the voltage is supplied to the port P2-in3 of the current output module 2, so that the current flowing through the resistor R4 from bottom to top is increased, and further the reverse charging current (from left to right) of the resistor C3 is increased, and the charging time is shortened due to the increase of the charging current, i.e. the pulse width is narrowed, that is, when the external condition tries to increase the pulse width, the feedback action of the pulse width control module 7 will make the pulse width narrow in reverse, and vice versa, the end effect is to make the pulse width remain stable, if the pulse width is to be changed artificially, the set voltage is changed by adjusting the sliding W2, the pulse width may be re-stabilized at the newly set value.
Claims (2)
1. A high-stability pulse current generating circuit comprises a frequency setting module (1) and a current output module (2), the device is characterized by also comprising a current sampling module (3), an amplitude measuring module (4), an amplitude control module (5), a duty ratio measuring module (6) and a pulse width control module (7), wherein a frequency setting module is connected with the current output module (2) and the pulse width control module (7), the current output module (2) is connected with the current sampling module (3), the current sampling module (3) is connected with the amplitude measuring module (4) and the duty ratio measuring module (6), the amplitude measuring module (4) is connected with the amplitude control module (5) and the duty ratio measuring module (6), the amplitude control module (5) is connected with the current output module (2), and the pulse width control module (7) is connected with the current output module (2);
the structure of the current output module (2) is that one end of a resistor R1 is connected with one end of a capacitor C2 and is connected with the grid of a field effect transistor Q1, the other end of the resistor R1 is connected with the other end of a capacitor C2 and serves as one input end of the current output module (2) and is marked as a port P2-in1, the port P2-in1 is connected with a pulse voltage signal output end of a frequency setting module (1), and pulse voltage output by the frequency setting module (1) is amplified into high-power current pulses through the current output module (2); the source of the field effect transistor Q1 is grounded, the drain is connected with one end of a resistor R2 and the gate of the field effect transistor Q2, the other end of the resistor R2 is connected with one end of a capacitor C1 and the source of the field effect transistor Q2, the resistor R2 is used as a second input end of the current output module (2) and is marked as a port P2-in2 and is connected with the output end of the amplitude control module (5), the other end of the capacitor C1 is grounded, the drain of the field effect transistor Q2 is connected with one end of the resistor R3 and one end of a capacitor C3, the other end of the resistor R3 is grounded, the other end of the capacitor C3 is connected with one end of a resistor R4, one end of a load and the cathode of a diode D1, the other end of the resistor R4 is used as a third input end of the current output module (2) and is marked as a port P2-in3 and is connected with the output end of a pulse width control module (7), the anode of a diode D1 is grounded, and the other end of the load is connected with one end of a sampling resistor Rs, the output end of the current output module (2) is marked as a port P2-out and is connected with the input end of the current sampling module (3), and the other end of the sampling resistor Rs is grounded; wherein the field effect transistor Q1 is N-type field effect transistor, and the field effect transistor Q2 is P-type field effect transistor;
the current sampling module (3) is structurally characterized in that the in-phase input end of the operational amplifier U1A is used as the input end of the current sampling module (3) and is marked as a port P3-in and is connected with the port P2-out of the current output module (2), the reverse phase input end of the operational amplifier U1A is connected with one end of a resistor R5, one end of a resistor R6 and one end of a resistor R7, the other end of the resistor R6 is connected with the output end of the operational amplifier U1A and is used as the output end of the current sampling module (3) and is marked as a port P3-out and is connected with the amplitude measuring module (4) and the duty ratio measuring module (6); the other end of the resistor R5 is connected with one end of a resistor R8, one end of a resistor R10 and the inverting input end of the operational amplifier U1B, the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1B and is grounded, the other end of the resistor R8 is connected with one end of an adjustable resistor R9, and the other end of the adjustable resistor R9 is connected with the other end of a resistor R7 and the output end of the operational amplifier U1B;
the structure of the amplitude measuring module (4) is that the anode of a diode D2 is used as the input end of the amplitude measuring module (4) and is marked as a port P4-in, and is connected with a port P3-out of the current sampling module (3), the cathode of the diode D2 is connected with one end of a capacitor C4, one end of a resistor R11 and the non-inverting input end of an operational amplifier U2A, the other end of the resistor R11 and the other end of the capacitor C4 are grounded, the inverting input end of the operational amplifier U2A is connected with the output end and is used as the output end of the amplitude measuring module (4) and is marked as a port P4-out, and is connected with the amplitude control module (5) and the duty ratio measuring module (6);
the structure of the amplitude control module (5) is that one end of a resistor R19 is used as the input end of the amplitude control module (5) and is marked as a port P5-in, and is connected with a port P4-out of the amplitude measurement module (4), the other end of a resistor R19 is connected with one end of a resistor R21 and the non-inverting input end of an operational amplifier U3B, the other end of the resistor R21 is grounded, the inverting input end of the operational amplifier U3B is connected with one end of a resistor R17 and one end of a resistor R18, the other end of the resistor R17 is connected with the sliding terminal of a sliding rheostat W1, one end of the sliding resistor is grounded, the other end of the sliding resistor is connected with the cathode of a 5.1V voltage stabilizing diode D3 and one end of a resistor R20, the anode of the voltage stabilizing diode D3 is grounded, the other end of the resistor R20 is connected with a +12V power supply, the other end of the resistor R18 is connected with the output end of the operational amplifier U3B and the inverting input end of the operational amplifier U3A, one end of a capacitor C5 and one end of the resistor R12 are both grounded, the other end of the capacitor C5 is connected with the non-inverting input end of the operational amplifier U2B and the non-inverting input end of the operational amplifier U3A, the other end of the resistor R12 is connected with one end of the resistor R13, one end of the resistor R14 and the inverting input end of the operational amplifier U2B, the other end of the resistor R14 is connected with one end of the resistor R15, one end of the resistor R16 and the output end of the operational amplifier U2B, the other end of the resistor R15 and the other end of the resistor R13 are both connected with a +12V power supply, the other end of the resistor R16 is connected with the non-inverting input end of the operational amplifier U3A, the output end of the operational amplifier U3A is connected with the gate of an N-type field effect transistor Q3, the drain of the field effect transistor Q3 is connected with the power supply VPP, the source is connected with one end of the inductor L1 and the cathode of a diode D4, the anode of a diode D4 is grounded, the other end of the inductor L1 is connected with one end of the capacitor C6 as the output end of an amplitude control module (5) which is marked as the output end of the P5-out of the output module 2 connected with the output terminal of the current output module 2-P2, the other end of the capacitor C6 is grounded;
the structure of the duty ratio measuring module (6) is that the non-inverting input end of the operational amplifier U4A is used as an input end of the duty ratio measuring module (6) and is marked as a port P6-in1 to be connected with a port P3-out of the current sampling module (3), the inverting input end of the operational amplifier U4A is connected with one end of a resistor R27 and one end of a resistor R28, the other end of the resistor R28 is grounded, the other end of the resistor R27 is used as the other input end of the duty ratio measuring module (6) and is marked as a port P6-in2 to be connected with a port P4-out of the amplitude measuring module (4), the output end of the operational amplifier U4A is connected with the cathode of a diode D6 and the cathode of a diode D5, the anode of the diode D6 is grounded, the anode of a diode D5 is connected with one end of the resistor R26 and one end of an inductor L2, the other end of a resistor R26 is connected with one end of a thermistor R24 and the output end of the operational amplifier U4B, the other end of the thermistor R24 is connected with the inverting input end of the operational amplifier U4B and one end of the resistor R23, the other end of the resistor R23 is grounded, the non-inverting input end of the operational amplifier U4B is connected with one end of the resistor R22, one end of the capacitor C7 and one end of the capacitor C8, the other end of the resistor R22 and the other end of the capacitor C7 are grounded, the other end of the capacitor C8 is connected with one end of the resistor R25, the other end of the resistor R25 is connected with the output end of the operational amplifier U4B, the other end of the inductor L2 is connected with one end of the capacitor C9, the other end of the capacitor C9 is connected with one end of the resistor R30 and the anode of the diode D7, the other end of the resistor R30 is grounded, the cathode of the diode D7 is connected with the non-inverting input end of the operational amplifier U5A, one end of the resistor R29 and one end of the capacitor C10, the other end of the resistor R29 and the other end of the capacitor C10 are grounded, the inverting input end of the operational amplifier U5 is connected with the inverting input end of the output end 5A, and used as a duty ratio measuring module, is marked as a port P6-out and is connected with the pulse width control module (7);
the pulse width control module (7) is structurally characterized in that one end of a resistor R33 is connected with an inverting input end of an operational amplifier U6A and one end of an adjustable resistor R32, the other end of the resistor R33 serves as one input end of the pulse width control module (7) and is marked as a port P7-in1, the other end of the resistor R33 serves as a port P6-out of the duty ratio measuring module (6), a non-inverting input end of the operational amplifier U6A is connected with one end of a resistor R34, the other end of the resistor R34 is grounded, the other end of the adjustable resistor R32 is connected with one end of a resistor R31, the other end of the resistor R31 is connected with an output end of an analog multiplier U7, one input end of an analog multiplier U7 serves as a second input end of the pulse width control module (7) and is marked as a port P7-in2 and is connected with a voltage port for controlling frequency in the frequency setting module (1), the other end of the analog U7 is connected with one end of a capacitor C11, an output end of the operational amplifier U596 and the other end of the operational amplifier U596 is connected with an inverting input end of a capacitor U B, the output end of the pulse width control module (7) is marked as a port P7-out and is connected with a port P2-in3 of the current output module (2), the non-inverting input end of the operational amplifier U6B is connected with the slide wire end of the slide rheostat W2, one end of the slide rheostat W2 is grounded, the other end of the slide rheostat W2 is connected with one end of a resistor R35 and the anode of a 5.1V voltage-stabilizing diode D8, the other end of the resistor R35 is connected with a-12V power supply, and the cathode of a voltage-stabilizing diode D8 is grounded; the operational amplifier U6A and the operational amplifier U6B are two units integrating double operational amplifiers and adopt +12V and-12V double power supplies for power supply.
2. A high-stability pulse current generating circuit as claimed in claim 1, wherein the magnitude of the power VPP in the amplitude control block (5) is in the range of +12V to + 200V.
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