CN111542148A

CN111542148A - LED driving module

Info

Publication number: CN111542148A
Application number: CN202010344741.7A
Authority: CN
Inventors: 蔡业信; 杨正友; 黄沛胜
Original assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Current assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Priority date: 2020-04-27
Filing date: 2020-04-27
Publication date: 2020-08-14
Anticipated expiration: 2040-04-27
Also published as: CN111542148B

Abstract

The application relates to an LED driving module, which comprises a PWM detection circuit, a PWM dimming circuit and a PWM dimming control circuit, wherein the PWM detection circuit is used for detecting and outputting a PWM dimming signal; the linear dimming circuit controls the sampling voltage to be reduced along with the reduction of the duty ratio of the PWM dimming signal according to the PWM dimming signal; the PWM processing circuit is used for outputting a first level when the duty ratio of the PWM dimming signal exceeds a set value and outputting a second level when the duty ratio of the PWM dimming signal does not exceed the set value; and the selection circuit is used for inputting the PWM dimming signal to the control end of the switching tube for PWM dimming when the PWM processing circuit outputs a first level, and starting the linear dimming circuit for linear dimming when the PWM processing circuit outputs a second level. By combining PWM dimming and linear dimming, the problems of stroboflash and dimming depth in PWM dimming can be solved to the maximum extent, and the LED dimming effect is optimized.

Description

LED driving module

Technical Field

The invention relates to the field of LEDs, in particular to an LED driving module.

Background

LED lighting is widely used because of its many advantages such as environmental protection, economy, and high luminous efficiency. In practical operation, there are two ways to adjust the brightness of the LED, the first is PWM (Pulse width modulation) dimming, and the second is linear dimming. The PWM dimming belongs to digital dimming, and has high dimming precision and a large dimming range. When PWM is adopted for dimming, if the frequency is too low (less than 100Hz), flicker can be seen by naked eyes, and if the frequency is too high (200 Hz-20 KHz), howling in the range of human ears can occur. If linear dimming is adopted, although phenomena such as flicker and howling do not occur, the linear dimming range is narrow, and dimming is not flexible enough.

Disclosure of Invention

Based on this, the present application provides an LED driving module, aiming at the above technical problem that howling is easily generated when the PWM dimming pulse frequency is too high.

In order to solve the technical problem, the technical scheme provided by the application is as follows:

the utility model provides a LED drive module, LED drive module has first to third port, wherein, first port is used for inserting PWM dimming signal, the second port with be used for the access to establish ties the luminous branch road that forms by power supply unit, LED lamp pearl, inductance and sampling resistor between the third port, just the third port with sampling resistor's current input end is connected, LED drive module includes:

the PWM detection circuit is connected with the first port and used for detecting and outputting a PWM dimming signal;

the linear dimming circuit is connected between the PWM detection circuit and the third port and is used for controlling the sampling voltage of the third port to be reduced along with the reduction of the duty ratio of the PWM dimming signal according to the PWM dimming signal;

the PWM processing circuit is connected with the PWM detection circuit and used for outputting a first level when the duty ratio of the PWM dimming signal exceeds a set value and outputting a second level when the duty ratio of the PWM dimming signal does not exceed the set value, wherein one of the first level and the second level is a high level, and the other one of the first level and the second level is a low level;

the input end and the output end of the switching tube are respectively connected with the second port and the third port;

and the selection circuit is respectively connected with the PWM detection circuit, the PWM processing circuit and the linear dimming circuit and is used for inputting the PWM dimming signal output by the PWM detection circuit into the control end of the switching tube to perform PWM dimming when the PWM processing circuit outputs a first level, and starting the linear dimming circuit to adjust the sampling voltage of the third port to perform linear dimming when the PWM processing circuit outputs a second level.

In one embodiment, the first level is a high level and the second level is a low level.

In one embodiment, the PWM processing circuit includes a calculation unit and a voltage comparator, wherein the calculation unit includes:

the input end of the first inverter is used as the input end of the calculation unit and is connected with the output end of the PWM detection circuit, and the first inverter is used for outputting a first voltage after inverting the high and low levels of the PWM dimming signal;

the integrator is used for accessing the first voltage, integrating the first voltage and outputting a second voltage of a triangular wave;

the first error amplifier is respectively connected to the second voltage and the first reference voltage, performs error amplification and outputs a third voltage;

the voltage comparator is respectively connected to the third voltage and the second reference voltage, an output end of the voltage comparator is used as an output end of the PWM processing circuit to output a fourth voltage, when the third voltage exceeds the second reference voltage, a high level is output, and when the third voltage does not exceed the second reference voltage, a low level is output.

In one of the embodiments, the first and second electrodes are,

the selection circuit includes:

the AND gate is respectively connected with the PWM dimming signal and the fourth voltage and outputs a fifth voltage;

the linear dimming circuit is connected with the output end of the second inverter and is used for starting linear dimming when the fifth voltage is at a high level;

one input end of the first or gate is connected to the fifth voltage, and the output end of the first or gate is connected to the control end of the switch tube;

the linear dimming circuit includes:

the error reference value adjusting unit is connected with the PWM detection circuit and used for acquiring a PWM dimming signal and outputting a reference adjusting value, and the reference adjusting value is reduced along with the reduction of the duty ratio of the PWM dimming signal;

the multiplier is respectively connected with the fifth voltage and the reference adjusting value, performs multiplication operation and outputs a sixth voltage;

the subtracter is respectively connected with the sixth voltage and the third reference voltage, subtracts the sixth voltage from the third reference voltage and outputs an error reference value;

one input end of the second error amplifier is connected to the error reference value, the other input end of the second error amplifier is connected to a third port to obtain a sampling voltage, and the second error amplifier is used for calculating an error between the sampling voltage and the error reference value, amplifying the error and outputting the error;

and the input end and the output end of the PFC control unit are respectively connected with the output end of the second error amplifier and the input end of the first OR gate.

In one embodiment, the error reference value adjusting unit is the calculating unit, and the output terminal of the first error amplifier is connected to the multiplier as the output terminal of the error reference value adjusting unit.

In one embodiment, a third inverter is connected between the and gate and the PWM detection circuit, the LED driving module further includes an RS flip-flop, the RS flip-flop is an RS flip-flop formed by a nor gate, an output end of the first or gate is connected to an R end of the RS flip-flop, and a Q end of the RS flip-flop is connected to a control end of the switching tube.

In one embodiment, the first inverter comprises a first operational amplifier, a resistor R11, a resistor R12, and a resistor R1f, wherein,

the inverting input end of the first operational amplifier is connected with one end of a resistor R11, and the other end of the resistor R11 is used as the input end of the first inverter and is connected with the output end of the PWM detection circuit; the non-inverting input terminal of the first operational amplifier is grounded through a resistor R12, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through a resistor R1 f.

In one embodiment, the integrator comprises a second op-amp, a feedback capacitor, a resistor R21, a resistor R22, and a resistor R2f, wherein,

the inverting input end of the second operational amplifier is connected with one end of a resistor R21, and the other end of the resistor R21 is used as the input end of the integrator and is connected with the output end of the first inverter; the non-inverting input end of the second operational amplifier is grounded through a resistor R22; the output end of the second operational amplifier is connected with the inverting input end of the second operational amplifier through a resistor R2f, and the feedback capacitor is connected with a resistor R2f in parallel.

In one embodiment, the first error amplifier comprises a third operational amplifier, a first capacitor, a second capacitor, a resistor R31, and a resistor R32, wherein,

the non-inverting input end of the third operational amplifier is connected with one end of a resistor R31, and the other end of the resistor R31 is used as the input end of the first error amplifier and is connected with the output end of the integrator; the inverting input end of the third operational amplifier is connected to a first reference voltage; the output end of the third operational amplifier is connected with the non-inverting input end of the third operational amplifier through the second capacitor, and the resistor R32 is connected with the first capacitor in series and then connected with the second capacitor in parallel.

In one embodiment, the subtractor comprises a fourth op-amp, a resistor R71, a resistor R72, a resistor R73, and a resistor R74, wherein,

the inverting input end of the fourth operational amplifier is connected with one end of a resistor R71, and the other end of the resistor R71 is used as the input end of the subtracter and is connected with the output end of the multiplier; the non-inverting input end of the fourth operational amplifier is connected to a third reference voltage through a resistor R73, and the non-inverting input end of the fourth operational amplifier is grounded through a resistor R74; the output end of the fourth operational amplifier is connected with the inverting input end of the fourth operational amplifier through a resistor R72.

The LED driving module is integrated with a PWM detection circuit and a linear dimming circuit, so that the LED driving module has two functions of PWM dimming and linear dimming, and the LED driving module is also integrated with a PWM processing circuit and a selection circuit, wherein the PWM processing circuit can detect the pulse duty ratio of a PWM dimming signal, and outputs a first level when the pulse duty ratio of the PWM dimming signal exceeds a set value, and outputs a second level when the pulse duty ratio of the PWM dimming signal does not exceed the set value. When the selection circuit detects the first level, the PWM dimming is started, and when the selection circuit detects the second level, the linear dimming is started. The selection circuit selects different dimming circuits according to different levels, when the pulse duty ratio of the PWM pulse signal is large, PWM dimming is allowed, and when the pulse duty ratio of the PWM pulse signal is small, the PWM dimming is stopped, and the linear dimming is converted. In this application, through combining PWM to adjust luminance and linear dimming, can solve the stroboscopic and adjust luminance the degree of depth problem in PWM adjusts luminance by at utmost, optimize LED dimming effect.

Drawings

Fig. 1 is a schematic diagram illustrating a connection relationship between ports of an LED driving module according to an embodiment;

FIG. 2 is a block diagram of the internal connections of an LED driver module according to an embodiment;

FIG. 3 is a connection diagram of an internal circuit of an LED driving module according to an embodiment;

FIG. 4a is a circuit diagram of a first inverter according to an embodiment;

fig. 4b is a schematic diagram illustrating a variation of the PWM dimming signal and the first voltage according to an embodiment;

FIG. 5 is a circuit diagram of an integrator of an embodiment;

FIG. 6 is a circuit diagram of a first error amplifier of an embodiment;

FIG. 7 is a circuit diagram of a multiplier of an embodiment;

fig. 8 is a circuit diagram of a subtractor according to an embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In this application, LED drive module is used for adjusting and control the luminance of LED lamp pearl. As shown in fig. 1, the LED driving module U1 has a first port DIM, a second port DRN and a third port ISEN. The first port DIM is connected to the PWM dimming signal, for example, the first port DIM is used for being connected to a PWM modulation module that generates the PWM dimming signal. The series branch formed by serially connecting the power supply unit, the LED lamp bead, the inductor L1 and the sampling resistor R2 is connected between the second port DRN and the third port ISEN, and the third port ISEN is connected with the current input end of the sampling resistor R2. Specifically, the negative output terminal of the power supply unit is grounded, and the sampling resistor R2 is connected between the third port ISEN and ground.

As shown in fig. 2, the LED driving module U1 includes a PWM detection circuit 110, a linear dimming circuit 130, a PWM processing circuit 120, a switching tube T1, and a selection circuit 140.

An input terminal of the PWM detection circuit 110 is connected to the first port DIM, and is used for detecting and outputting the PWM dimming signal from an output terminal thereof. As is well known, the PWM dimming signal is a pulse signal in a square wave, and the brightness of the LED can be adjusted by adjusting the pulse duty ratio of the PWM dimming signal.

The input end of the linear dimming circuit 130 is connected to the output end of the PWM detection circuit 110, the output end of the linear dimming circuit 130 is connected to the third port ISEN, and the linear dimming circuit 130 is configured to obtain the PWM dimming signal and control the sampling voltage of the third port ISEN to increase with the increase of the duty ratio of the PWM dimming signal according to the PWM dimming signal. The sampling voltage of the third port ISEN is actually the voltage of the sampling resistor R2, the sampling voltage is increased, the current flowing through the sampling resistor R2 is increased, namely, the current flowing through the LED lamp bead is increased, the sampling voltage is reduced, the current flowing through the sampling resistor R2 is reduced, namely, the current flowing through the LED lamp bead is reduced, and therefore the linear dimming of the LED is realized by controlling the size of the sampling voltage of the third port ISEN.

The input end of the PWM processing circuit 120 is connected to the output end of the PWM detecting circuit 110, and is configured to obtain the PWM dimming signal and perform calculation, specifically, the PWM processing circuit 120 is configured to output a first level when the duty ratio of the PWM dimming signal exceeds a set value, and output a second level when the duty ratio of the PWM dimming signal does not exceed the set value. One of the first level and the second level is a high level, and the other is a low level. Specifically, the first level may be a high level, and the second level may be a low level. Wherein, the set value can be set according to specific needs.

The input end of the switch tube T1 is connected to the second port DRN, the output end of the switch tube T1 is connected to the third port ISEN, namely, the power supply unit, the LED lamp bead, the inductor L1, the switch tube T1 and the sampling resistor R2 form a series loop. Specifically, the power supply unit, the LED lamp bead, the inductor L1, the switch tube T1 and the sampling resistor R2 are sequentially connected in series to form a series loop. The on-off of the series circuit can be controlled by controlling the on-off of the switching tube T1.

The selection circuit 140 is respectively connected to the PWM detection circuit 110, the PWM processing circuit 120, and the linear dimming circuit 130, and is configured to obtain the level signal output by the PWM processing circuit 120 and select PWM dimming or linear dimming according to the level signal output by the PWM processing circuit 120. Specifically, when the PWM processing circuit 120 outputs the first level, the linear dimming is disabled, and the PWM dimming signal output by the PWM detecting circuit 110 is input to the control terminal of the switching tube T1, where the PWM dimming signal is a pulse signal that controls the on/off of the switching tube T1 to perform the PWM dimming. When the PWM processing circuit 120 outputs the second level, the PWM dimming is disabled, and the linear dimming circuit 130 is enabled to adjust the sampling voltage of the third port ISEN for linear dimming.

In one embodiment, as shown in fig. 3, the PWM processing circuit 120 includes a calculation unit 121 and a voltage comparator a 4. The calculation unit 121 includes a first inverter a1, an integrator a2, and a first error amplifier a 4.

An input terminal of the first inverter a1 is connected to an output terminal of the PWM detection circuit 110 as an input terminal of the calculation unit 121, and an input terminal of the calculation unit 121 is also an input terminal of the PWM processing circuit 120. The first inverter a1 is configured to obtain and invert the PWM dimming signal, invert a high level of the PWM dimming signal to a low level, and invert a low level of the PWM dimming signal to a high level, thereby outputting a first voltage Vo 1. It will be appreciated that the first voltage Vo1 is actually a pulse level signal that inverts the PWM dimming signal.

The input end of the integrator a2 is connected to the output end of the first inverter a1, and is used for receiving the first voltage Vo1 and performing an integration operation to obtain and output a second voltage Vo2, wherein the second voltage Vo2 is obtained by integrating an square wave, and therefore, the second voltage Vo2 is a triangular wave.

One input end of the first error amplifier A3 is connected with the output end of the integrator A2 to obtain the second voltage Vo2, the other input end is connected with the first reference voltage Vr1, and the first error amplifier A3 calculates the error between the connected second voltage Vo2 and the first reference voltage Vr1, amplifies the error and outputs the third voltage Vo 3. The output of the first error amplifier a3 also serves as the output of the calculation unit 121.

One input terminal of the voltage comparator a4 is connected to the output terminal of the calculating unit 121 to obtain a third voltage Vo3, the other input terminal is connected to the second reference voltage Vr2, and the output terminal of the voltage comparator a4, as the output terminal of the PWM processing unit 120, outputs a fourth voltage, when the third voltage Vo3 exceeds the second reference voltage Vr2, outputs a first level, and when the third voltage Vo3 does not exceed the second reference voltage Vr2, outputs a second level, wherein the first level is a high level and the second level is a low level. Specifically, the voltage comparator a4 is a hysteresis comparator. It should be noted that, when the pulse duty ratio exceeds the preset value, the third output voltage Vo3 exceeds Vr2 and the third output voltage Vo3 increases with the increase of the pulse duty ratio, so that the fourth output voltage Vo4 continuously outputs a high level by the first error amplifier a 3; when the pulse duty does not exceed the preset value, the third output voltage Vo3 increases with the decrease of the pulse duty, but does not exceed Vr2, so that the fourth output voltage Vo4 continuously outputs a low level.

In a specific embodiment, as shown in fig. 4a, the first inverter a1 includes a first operational amplifier a11, a resistor R11, a resistor R12, and a resistor R1 f. The inverting input end of the first operational amplifier a11 is connected to one end of the resistor R11, and the other end of the resistor R11 is connected to the output end of the PWM detection circuit 110 as the input end of the first inverter a11 to obtain a PWM dimming signal; the non-inverting input terminal of the first operational amplifier a11 is connected to ground through a resistor R12, and the output terminal of the first operational amplifier a11 is connected to the inverting input terminal of the first operational amplifier a11 through a resistor R1 f. In this embodiment, let Vi be the PWM dimming signal, and the output voltage characteristic relation of the inverter:

by setting Rf to R1, a Vo1 to Vi inverse follower can be realized, and a specific waveform transformation diagram is shown in fig. 4 b.

In one embodiment, as shown in fig. 5, the integrator a2 includes a second operational amplifier a21, a feedback capacitor C2f, a resistor R21, a resistor R22, and a resistor R2 f. The inverting input end of the second operational amplifier A21 is connected with one end of a resistor R21, and the other end of the resistor R21 is connected with the output end of the first inverter A1 as the input end of an integrator A2; the non-inverting input end of the second operational amplifier A21 is grounded through a resistor R22; the output end of the second operational amplifier A21 is connected with the inverting input end of the second operational amplifier A21 through a resistor R2f, and a feedback capacitor C2f is connected with the resistor R2f in parallel.

In this embodiment, for the PWM dimming signal, the recommended frequency f of the PWM signal is within the range of 200Hz to 10KHz for optimal dimming effect, and then the time constant τ R21C 2f is determined, and a square wave signal with the PWM input standard D of 0.5 is assumed, so as to obtain the PWM dimming signal

0.05mS<t<2.5 mS. Assuming that the integrator supply voltage VDD is 10V, Uom is VDD, and the maximum output voltage E of the PWM dimming signal is 1V, since τ must be satisfied

The value range of tau can be obtained as follows: 0.005mS<τ<0.25mS, i.e. 0.005mS<R21*C2f<0.25 mS. Therefore, the value range of C2f can be determined, because the input resistance of the inverse integration circuit must satisfy R21 ≥ 10K Ω, and R21 ≥ 10K Ω, the value of the feedback capacitor Cf is: 0.5nF<Cf<25nF, and nF-level capacitors can be implemented in the integrated driver IC, and the value of R2 is obtained according to the relationship R22 ═ R21// R2 f.

In a specific embodiment, as shown in fig. 6, the first error amplifier includes a third operational amplifier a31, a first capacitor C31, a second capacitor C32, a resistor R31, and a resistor R32. The non-inverting input end of the third operational amplifier A31 is connected with one end of a resistor R31, and the other end of the resistor R31 is connected with the output end of the integrator A2 as the input end of the first error amplifier A3; the inverting input end of the third operational amplifier A31 is connected with a first reference voltage Vr 1; the output end of the third operational amplifier A31 is connected with the non-inverting input end of the third operational amplifier A31 through a second capacitor C32, and the resistor R32 is connected with the first capacitor C31 in series and then connected with the second capacitor C32 in parallel.

In this embodiment, to stabilize the first error amplifier a3 circuitry, the cutoff frequency Fco is first determined, since the system open loop gain is 0dB at this cutoff frequency, then the gain of the first error amplifier is selected, and then the first error amplifier gain slope is designed such that the slope of the system total open loop gain curve around the cutoff frequency is-1; finally, the gain curve of the first error amplifier is adjusted (i.e. the zero and polar positions are set) to obtain the phase margin required by the stable system. Wherein, to ensure the system stability, the cut-off frequency must be less than 1/2 of the working frequency according to the sampling theorem. However, considering the combined effect of various factors, the actual design cutoff frequency Fco is much smaller than 1/2 of the operating frequency, otherwise the first error amplifier output Vo3 will have a large ripple voltage affecting the final output result. Fco is therefore usually designed to be 1/4-1/5 of the operating frequency Fk. And the transition frequencies Fz and Fp satisfy Fz 1/2 × pi R32 × C31 and Fp 1/2 × pi R32 × C32, and satisfy Fco/Fz × Fp/Fco, where the gain curve decreases with a slope-1.

In one embodiment, with continued reference to fig. 3, the selection circuit 140 includes an AND gate AND, a first OR gate OR1, AND a second inverter a 5; the linear dimming circuit 130 includes an error reference value adjusting unit 131, a multiplier a6, a second error amplifier a7, and a PFC control unit.

One input end of the AND gate AND is connected to the output end of the PWM detection circuit 110 to obtain the PWM dimming signal Vi, the other input end of the AND gate AND is connected to the output end of the PWM processing circuit 120 to obtain an output result thereof, specifically, the output end of the voltage comparator a4 to obtain the fourth voltage Vo4, AND the AND gate AND performs an AND operation on the fourth voltage Vo4 AND the PWM dimming signal Vi to output an operation result. At this time, if the PWM processing circuit 120 outputs a high level, the AND gate AND outputs a PWM dimming signal; if the PWM processing circuit 120 outputs a low level, the AND gate AND outputs a low level 0.

The input terminal of the second inverter a5 is connected to the output terminal of the PWM processing circuit 120, specifically, to the output terminal of the voltage comparator a4 to obtain the fourth voltage Vo4, and the second inverter a5 inverts the high and low levels of the fourth voltage Vo4, that is, inverts the high level of the fourth voltage Vo4 to a low level, inverts the low level of the fourth voltage Vo4 to a high level, and outputs the fifth voltage Vo 5. It can be seen that the fifth voltage Vo5 is also a level signal including high and low levels.

One input end of the first OR gate OR1 is connected with the output end of the AND gate AND, the other input end is connected with the output end of the PFC control unit, AND the output end of the first OR gate OR1 is connected with the control end of the switching tube T1.

An input terminal of the error reference value adjusting unit 131 is connected to the PWM detecting circuit 110 to obtain the PWM dimming signal, and outputs a reference adjustment value according to the PWM dimming signal, the reference adjustment value increasing with a decrease in the duty ratio of the PWM dimming signal.

One input terminal of the multiplier a6 is connected to the output terminal of the inverter a5 to obtain the fifth voltage Vo5, the other input terminal is connected to the output terminal of the error reference value adjusting unit 131 to obtain the reference adjustment value, and the multiplier multiplies the fifth voltage Vo5 and the reference adjustment value to output the sixth voltage Vo 6. At this time, if the PWM processing circuit 120 outputs a high level, the AND gate AND outputs a PWM dimming signal AND transmits the PWM dimming signal to the control terminal of the switching tube T1, so as to implement PWM dimming; if the PWM processing circuit 120 outputs a low level, the AND gate AND outputs a low level 0, the fifth voltage Vo5 inputted to the multiplier is a high level, AND the sixth voltage Vo6 outputted from the multiplier a6 is equal to the reference adjustment value.

One input end of the subtracter A7 is connected with the output end of the multiplier A6 to obtain the sixth voltage Vo6, the other input end is connected with the third reference voltage Vr3, and the subtracter subtracts the sixth voltage Vo6 from the third reference voltage Vr3 to output an error reference value Vo7, namely the error reference value Vo7 decreases along with the increase of the sixth voltage.

And a second error amplifier A8, one input end of which is connected with the output end of the subtracter A7 to obtain an error reference value Vo7, the other input end of which is connected with the third port ISEN to obtain a sampling voltage, wherein the sampling voltage is recorded as Ve, and the second error amplifier A8 is used for calculating the error between the sampling voltage Ve and the error reference value Vo7 and outputting the error.

An input terminal of the PFC control unit is connected to an output terminal of the second error amplifier A8, and an output terminal of the PFC control unit is connected to an input terminal of the first OR gate OR 1.

In the above embodiment, when the duty ratio of the PWM dimming signal exceeds the set value, the PWM processing circuit 120 outputs a high level, AND the PWM dimming signal still outputs the PWM dimming signal after passing through the AND gate AND is transmitted to the control terminal of the switching tube T1 through the first OR gate OR1, so as to perform PWM dimming. At this time, the fifth voltage Vo5 input to the multiplier by the second inverter a5 is low, the sixth voltage Vo6 output from the multiplier a6 is zero, the error reference value Vo7 output from the subtractor a7 remains unchanged, and the linear dimming circuit does not perform linear dimming. When the duty ratio of the PWM dimming signal does not exceed the set value, the PWM processing circuit 120 outputs a low level, the PWM dimming signal outputs a low level after passing through the AND gate AND, AND the PWM dimming is turned off. At this time, the fifth voltage Vo5 input to the multiplier by the second inverter a5 is at a high level, the sixth voltage Vo6 output by the multiplier a6 is equal to the reference adjustment value, the error reference value Vo7 output by the subtractor a7 is equal to the third reference value minus the reference adjustment value, and the reference adjustment value increases as the duty ratio of the PWM dimming signal decreases, resulting in a decrease of the error reference value Vo7 as the duty ratio of the PWM dimming signal decreases, that is, the error reference value Vo7 and the duty ratio of the PWM dimming signal change linearly. The error reference value Vo7 is linearly reduced, so that the sampling voltage Ve of the third port ISEN is also approximately linearly reduced, and the current flowing through the LED lamp bead is linearly reduced, so that the linear dimming circuit 130 is triggered to perform linear dimming.

In an embodiment, the error reference value adjusting unit 131 and the calculating unit 121 are the same unit, that is, the error reference value adjusting unit 131 includes the first inverter a1, the integrator a2 and the first error amplifier A3, and an output terminal of the first error amplifier A3 is connected to an input terminal of the multiplier a6 as an output terminal of the error reference value adjusting unit 131.

In a specific embodiment, as shown in fig. 7, the multiplier a6 includes a transistor T61, a transistor T62, a transistor T63, a resistor R61, a resistor R62, and a resistor Re, wherein the transistor T61, the transistor T62, and the transistor T63 are NPN transistors. Specifically, an emitter of the transistor T61 is connected to an emitter of the transistor T62 and a collector of the transistor T63, a collector of the transistor T61 and a collector of the transistor T62 are respectively connected to the reference voltage VCC through a resistor R61 and a resistor R62, a base of the transistor T61 and a base of the transistor T62 are respectively connected to a positive output terminal and a negative output terminal of the fifth voltage Vo5, an emitter of the transistor T63 is grounded through a resistor Re, a base of the transistor Te is connected to the third voltage Vo3, and a collector of the transistor T61 and a collector of the transistor T62 are respectively used as a positive output terminal and a negative output terminal of the multiplier A6 to output the sixth voltage Vo 6.

In an embodiment, as shown in fig. 8, the subtractor a7 includes a fourth op-amp a71, a resistor R71, a resistor R72, a resistor R73, and a resistor R74. The non-inverting input terminal of the fourth operational amplifier a71 is connected to the third reference voltage Vr3 through the resistor R73, and the non-inverting input terminal of the fourth operational amplifier a71 is also grounded through the resistor R74; the inverting input end of the fourth operational amplifier a71 is connected to one end of the resistor R71, and the other end of the resistor R71 is connected to the output end of the multiplier a6 as the input end of the subtractor a7 to obtain a sixth voltage Vo 6; the output end of the fourth operational amplifier a71 is connected to the inverting input end of the fourth operational amplifier a71 through a resistor R72, and the output end of the fourth operational amplifier a71 serves as the output end of the subtractor a7 to output the error reference value Vo 7. In the present embodiment, it is preferred that,

is provided with

At this time, the process of the present invention,

is provided with

Vo7 ═ k (Vr3-Vo 6).

In one embodiment, as shown in fig. 3, the LED driving module U1 further includes a third inverter a9 and an RS flip-flop, where the RS flip-flop is a nor gate, that is, when R is 0, Q is 1, when R is 1, Q is 0, the and gate is connected to the output terminal of the PWM detecting circuit 110 through the third inverter a9, the output terminal of the first OR gate OR1 is connected to the R terminal of the RS flip-flop, and the Q terminal of the RS flip-flop is connected to the control terminal of the switching tube T1. Further, as shown in fig. 3, the LED driving module U1 further includes a second and gate OR2, a demagnetization detecting unit, a maximum off-time detecting unit, and other protecting units, where the demagnetization detecting unit is configured to detect demagnetization time of the serial loop and output a high level when the demagnetization time is smaller than the minimum demagnetization time, the maximum off-time detecting unit is configured to detect off-time of the switching tube T1 and output a high level when the off-time exceeds the maximum off-time, output ends of the demagnetization time detecting unit and the maximum off-time detecting unit are respectively connected to an input end of the second OR gate OR2, and an output end of the second OR gate OR2 is connected to an S end of the RS flip-flop.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. The utility model provides a LED drive module, its characterized in that LED drive module has first to third port, wherein, first port is used for inserting PWM signal of adjusting luminance, the second port with be used for the access to establish ties the luminous branch road that forms by power supply unit, LED lamp pearl, inductance and sampling resistor between the third port, just the third port with sampling resistor's current input end connects, LED drive module includes:

2. The LED driving module according to claim 1, wherein the first level is a high level and the second level is a low level.

3. The LED driving module of claim 2, wherein the PWM processing circuit comprises a calculation unit and a voltage comparator, wherein the calculation unit comprises:

the first error amplifier is respectively connected to the second voltage and the first reference voltage, performs error amplification and outputs a third voltage, and the output end of the first error amplifier is used as the output end of the calculation unit;

4. The LED driver module according to claim 3,

the selection circuit includes:

the linear dimming circuit includes:

the error reference value adjusting unit is connected with the PWM detection circuit and used for acquiring a PWM dimming signal and outputting a reference adjusting value, and the reference adjusting value is increased along with the reduction of the duty ratio of the PWM dimming signal;

5. The LED driver module according to claim 4, wherein the error reference value adjusting unit is the calculating unit, and an output terminal of the first error amplifier is connected to the multiplier as an output terminal of the error reference value adjusting unit.

6. The LED driving module according to claim 4, wherein a third inverter is connected between the AND gate and the PWM detection circuit, the LED driving module further comprises an RS trigger, the RS trigger is an RS trigger composed of a NOR gate, an output end of the first OR gate is connected with an R end of the RS trigger, and a Q end of the RS trigger is connected with a control end of the switching tube.

7. The LED driving module of claim 3, wherein the first inverter comprises a first operational amplifier, a resistor R11, a resistor R12, and a resistor R1f, wherein,

8. The LED driving module of claim 3, wherein the integrator comprises a second op-amp, a feedback capacitor, a resistor R21, a resistor R22, and a resistor R2f, wherein,

9. The LED driver module of claim 3, wherein the first error amplifier comprises a third op-amp, a first capacitor, a second capacitor, a resistor R31, and a resistor R32, wherein,

10. The LED driving module of claim 4, wherein the subtractor comprises a fourth op-amp, a resistor R71, a resistor R72, a resistor R73, and a resistor R74, wherein,