CN114283749A - Source driver, display panel, display device and data driving method - Google Patents

Source driver, display panel, display device and data driving method Download PDF

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Publication number
CN114283749A
CN114283749A CN202111648355.8A CN202111648355A CN114283749A CN 114283749 A CN114283749 A CN 114283749A CN 202111648355 A CN202111648355 A CN 202111648355A CN 114283749 A CN114283749 A CN 114283749A
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display
data
display information
order
voltage output
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CN114283749B (en
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吴国强
兰传艳
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Abstract

The present disclosure provides a source driver, a display panel, a display device and a data driving method, the source driver including: the device comprises a receiving module, an adjusting module, a sending module and X voltage output channels, wherein X is more than or equal to 2 and is a positive integer; the receiving module is used for receiving original line display information, and the original line display information comprises X pieces of display data which are sequentially arranged; the adjusting module is used for adjusting the sequence of the display data in the original row display information according to a preset adjusting algorithm to obtain new row display information; the sending module is used for sending each display data to each voltage output channel according to the new row display information, wherein the display data in the new row display information at the jth order is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X; the voltage output channel is used for outputting corresponding data voltage through a voltage output end according to the received display data.

Description

Source driver, display panel, display device and data driving method
Technical Field
The present disclosure relates to the field of display, and in particular, to a source driver, a display panel, a display device, and a data driving method.
Background
The source driver, which is an important component of the display device, has a plurality of voltage output terminals arranged in sequence, each of which is electrically connected to one of the data lines in the display region. Each voltage output terminal can respectively provide data voltage for the corresponding data line, and the data voltage is written into the pixel unit in a driving state through the data line (generally, the display panel performs display driving in a line-by-line scanning manner, and the working state of the pixel unit is controlled by the gate line) so as to control the pixel unit to generate light with required brightness.
Disclosure of Invention
In a first aspect, an embodiment of the present disclosure provides a source driver, including: the device comprises a receiving module, an adjusting module, a sending module and X voltage output channels, wherein X is more than or equal to 2 and is a positive integer
The receiving module is used for receiving original line display information, and the original line display information comprises X pieces of display data which are sequentially arranged;
the adjusting module is used for adjusting the sequence of the display data in the original row display information according to a preset adjusting algorithm to obtain new row display information;
the sending module is used for sending each display data to each voltage output channel according to the new row display information, wherein the display data in the new row display information at the jth order is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X;
the voltage output channel is used for outputting corresponding data voltage through a voltage output end according to the received display data.
In some embodiments, X is an even number, and the original line display information is located from 1 st to c1Each of the display data of the order in which the order in the new line of display information is located is
Figure BDA0003445800620000021
Order to the first
Figure BDA0003445800620000022
Between the orders of bits, c1And a are all preset positive integers,
Figure BDA0003445800620000023
and is
Figure BDA0003445800620000024
The original line display information is positioned at the X-c2(ii) each of + 1-bit to Xth-bit display data, the bit in the new line of display information being at the Xth bit
Figure BDA0003445800620000025
Order to the first
Figure BDA0003445800620000026
Between the orders of bits, c2Is > 1 and is c2Is a positive integer, c2And b are all preset positive integers,
Figure BDA0003445800620000027
and is
Figure BDA0003445800620000028
In some embodiments, the display information is for the 1 st order to the c th order within the original line display information1Display data of a rank, the higher the rank of the display data in the original row display information is, the lower the rank in the new row display information is;
for the display information located at X-c within the original line2And display data from +1 th order to X-th order, wherein the higher the order of the display data in the original line display information is, the lower the order of the display data in the new line display information is.
In some embodiments, the original row display information is located within the second row display information
Figure BDA0003445800620000029
Order to the first
Figure BDA00034458006200000210
Each of the display data of the order in which the order in the new line of display information is located is
Figure BDA00034458006200000211
Order to the first
Figure BDA00034458006200000212
Between the bits;
the original line display information is positioned at the second position
Figure BDA00034458006200000213
Order to the first
Figure BDA00034458006200000214
Each of the display data of the order in which the order in the new line of display information is located is
Figure BDA00034458006200000215
Order to the first
Figure BDA00034458006200000216
Between the bits;
wherein the content of the first and second substances,
Figure BDA00034458006200000217
I1、I2、N1、N2are all positive integers which are set in advance,
Figure BDA00034458006200000218
Figure BDA00034458006200000219
the operation results of (1) are all positive integers.
In some embodiments, the display data at the ith position in the original row of display information has the position at the Pth (i) position in the new row of display information, i is greater than or equal to 1 and less than or equal to X, and i is a positive integer;
in i ∈ [1, c ]1]And P (i) is:
Figure BDA0003445800620000031
e1is composed of
Figure BDA0003445800620000032
Is rounded down, f1Is c1-I and I1Making remainder after division operation;
at i e c1+1,
Figure BDA0003445800620000033
and P (i) is:
P(i)＝i-c1
in that
Figure BDA0003445800620000034
And P (i) is:
Figure BDA0003445800620000035
e2is composed of
Figure BDA0003445800620000036
Is rounded down, f2Is composed of
Figure BDA0003445800620000037
And N1Making remainder after division operation;
in that
Figure BDA0003445800620000038
And P (i) is:
Figure BDA0003445800620000039
e3is composed of
Figure BDA00034458006200000310
Is rounded down, f3Is composed of
Figure BDA00034458006200000311
And N2Making remainder after division operation;
in that
Figure BDA00034458006200000312
And P (i) is:
P(i)＝i+c2
in i ∈ [ X-c ]2+1，X]And P (i) is:
Figure BDA00034458006200000313
e4is composed of
Figure BDA00034458006200000314
Is rounded down, f4Is X-I and I2And making a remainder after division operation.
In some embodiments, c1＝c2，I1＝I2，N1＝N2。
In some embodiments, I1Has a value range of [2,5 ]]；
I2Has a value range of [2,5 ]]；
N1Has a value range of [2,5 ]]；
N2Has a value range of [2,5 ]]。
In some embodiments, the source driver further includes:
an algorithm setting module configured to set c according to external input information1、c2、I1、I2、N1And N2A value of at least one of them.
In a second aspect, embodiments of the present disclosure also provide a display panel, including: a display area and a peripheral area located around the display area, wherein the source driver provided in the first aspect is disposed in the peripheral area.
In some embodiments, a pixel unit array and X data lines arranged along a first direction are disposed in the display region, and the pixel units are electrically connected with the corresponding data lines;
the display data at the ith position in the original row display information has the position at the P (i) th position in the new row display information, i is more than or equal to 1 and less than or equal to X, and i is a positive integer;
the data line positioned at the ith in the display area is electrically connected with the voltage output channel positioned at the p (i) th in the source driver.
In a third aspect, an embodiment of the present disclosure further provides a display device, including: a display panel as provided in the second aspect above.
In a fourth aspect, an embodiment of the present disclosure further provides a data driving method, based on the source driver provided in the first aspect, the data driving method includes:
the receiving and adjusting module receives original line display information, wherein the original line display information comprises X pieces of display data which are sequentially arranged;
the adjusting module adjusts the sequence of the display data in the original row display information according to a preset adjusting algorithm to obtain new row display information;
the receiving module sends the display data to the voltage output channels respectively according to the new row display information, wherein the display data in the new row display information at the jth order is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X;
and the voltage output channel outputs corresponding data voltage according to the received display data.
Drawings
Fig. 1 is a schematic circuit diagram of a display panel according to the related art;
fig. 2 is a schematic circuit diagram of a source driver according to the related art;
fig. 3 is a schematic circuit diagram of another display panel according to the related art;
fig. 4 is a schematic circuit diagram of another display panel according to the related art;
fig. 5 is a schematic circuit diagram of a source driver according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram illustrating an embodiment of the present disclosure in which the order of display data in original row display information is adjusted to obtain new row display information;
FIG. 7 is a schematic diagram of a voltage output channel according to an embodiment of the present disclosure;
fig. 8 is a schematic circuit diagram of another source driver according to an embodiment of the disclosure;
fig. 9 is a flowchart of a data driving method according to an embodiment of the disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present disclosure, a source driver, a display panel, a display device and a data driving method provided by the present disclosure are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram of a display panel according to the related art, and fig. 2 is a schematic circuit diagram of a source driver according to the related art, as shown in fig. 1 and fig. 2, the display panel includes a display area and a peripheral area, a pixel unit (not shown) array and a DATA line DATA are disposed in the display area, a source driver 1 and a pad area Q201 are disposed in the peripheral area Q2, the source driver 1 includes a receiving module 101, a transmitting module 102, and a plurality of voltage output channels 103, each voltage output channel 103 is configured with a voltage output end, a plurality of pads 2 corresponding to the voltage output ends are disposed in the pad area Q201, and the voltage output ends are electrically connected to the corresponding pads 2 (for example, the voltage output ends are electrically connected to the corresponding pads 2 through a circuit on the FPC).
The receiving module 101 is configured to receive line display information (generally, display DATA input from the outside is received through a dedicated interface circuit), where the line display information includes a plurality of display DATA that are in one-to-one correspondence with the DATA lines DATA and are sequentially arranged, the display DATA located at the ith in the line display information is the display DATA corresponding to the ith DATA line DATA, i is greater than or equal to 1 and less than or equal to X, and X is the number of the voltage output channels 103 (also is the number of the DATA lines DATA). The sending module 102 is configured to send each display data to each voltage output channel 103 according to new row display information, where the display data located at the ith bit in the row display information is sent to the ith voltage output channel 103. The voltage output channel 103 is configured to output a corresponding data voltage through a voltage output terminal according to the received display data. That is, the ith voltage output channel 103 receives the display DATA located at the ith in the row display information, and the ith voltage output channel 103 outputs the DATA voltage required by the ith DATA line DATA. At this time, the signal output terminal of the ith voltage output channel 103 needs to be electrically connected to the ith DATA line DATA. That is, the pads corresponding to the signal output terminals of the source driver 1 need to be sequentially connected to the DATA lines DATA (hereinafter, referred to as "sequentially connected").
Referring to fig. 1, the peripheral region Q2 further includes a fan-out region Q202, the fan-out region Q202 being located between the pad region Q201 and the display region Q1; in order to sequentially connect the pads 2 corresponding to the signal output terminals of the source driver 1 and the DATA lines DATA, X first connection lines L1 sequentially arranged along a first direction need to be arranged in the fan-out region Q202, and any two first connection lines L1 are not intersected.
In practical application, it is found that, since the distance between two adjacent pads 2 in the pad area Q201 is smaller than the distance between two adjacent DATA lines DATA in the display area Q1, so that the width of the pad area Q201 in the first direction is smaller than the width of the display area Q1 in the first direction, when the pad and the DATA lines DATA are sequentially connected by using the design of X first connection lines L1 that are sequentially arranged along the first direction and do not intersect with each other, most of the first connection lines L1 in the fan-out area Q202 extend from the middle of the fan-out area Q202 to the side of the fan-out area Q202, the long total length of the first connection lines L1 that need to be arranged in the fan-out area Q202 is longer, and the size occupied by the fan-out area Q202 is larger, so that the size occupied by the peripheral area Q2 is larger, which is not favorable for a narrow frame of a product.
Fig. 3 is a schematic circuit diagram of another display panel according to the related art, and fig. 4 is a schematic circuit diagram of another display panel according to the related art, as shown in fig. 3 and fig. 4, in order to reduce the size of the fan-out region Q202, the related art further proposes a design in which the pads 2 are connected to the data lines in a non-sequential manner, that is, there is a case in which the pad 2 located at the t-th position is electrically connected to the data line located at the w-th (w ≠ t). For example, the pad 2 located at the 1 st is electrically connected to the data line located at the 301 st, and the pad 2 located at the 600 th is electrically connected to the data line located at the 1 st; the specific correspondence between the pads 2 and the data lines can be designed in advance according to actual needs.
To realize the non-sequential connection between the pad 2 and the DATA line DATA, as shown in fig. 3, the first connection trace L1 in the fan-out region Q202 for connecting the pad 2 and the corresponding DATA line DATA may be designed to be crossed; alternatively, referring to fig. 4, corresponding second connection traces L2 are disposed in the display area Q1 for some DATA lines DATA near the edge of the display area Q1, one end of the second connection trace L2 is connected to the corresponding DATA line DATA, and the other end of the second connection trace L2 is located at the middle position of the side of the display area Q1 near the fan-out area Q202, at this time, part of the first connection trace L1 may be electrically connected to the corresponding DATA line DATA (the DATA line DATA near the edge of the display area Q1) through the second connection trace L2. Through the design, the total length of the first connecting wiring L1 arranged in the fan-out area Q202 can be shortened to a certain extent, and the occupied size of the fan-out area Q202 is reduced, so that the occupied size of the peripheral area Q2 is reduced, and the narrow frame of a product is facilitated.
However, since the conventional source driver 1 can only output DATA voltages sequentially, that is, the DATA voltage output by the signal output terminal of the ith voltage output channel 103 is the DATA voltage required by the ith DATA line DATA, that is, the DATA voltage loaded on the ith pad 2 is the DATA voltage required by the ith DATA line DATA for any i, the conventional source driver 1 cannot be adapted to the design in which the pads 2 are not sequentially connected to the DATA lines DATA.
The present disclosure provides a corresponding solution to the technical problem that the conventional source driver 1 cannot be adapted to the design in which the pad and the DATA line DATA are not connected in sequence.
Fig. 5 is a schematic circuit structure diagram of a source driver 1 according to an embodiment of the disclosure, and fig. 6 is a schematic diagram of a new row of display information obtained by adjusting a sequence of display data in an original row of display information according to an embodiment of the disclosure, as shown in fig. 5 and fig. 6, the source driver 1 includes: the device comprises a receiving module 101, an adjusting module 104, a sending module 102 and X voltage output channels 103, wherein the voltage output channels 103 are configured with voltage output ends, X is larger than or equal to 2, and X is a positive integer.
The receiving module 101 is configured to receive original line display information, where the original line display information includes X pieces of display data arranged in sequence. It should be noted that the display data located at the ith in the original row display information is the display data corresponding to the ith data line, and i is greater than or equal to 1 and less than or equal to X.
The adjusting module 104 is configured to adjust the sequence of the display data in the original line display information according to a preset adjusting algorithm to obtain new line display information. The preset adjusting algorithm can be designed according to the corresponding relation between the bonding pad and the data line in the display panel; for example, the data line in the display panel at the ith row is electrically connected to the pad at the p (i) th row, so that the display data in the ith row in the original row display information is located at the p (i) th row in the new row display information when the preset adjustment algorithm is designed, wherein 1 ≦ p (i) ≦ X. It should be noted that, the technical solution of the present disclosure does not limit the specific algorithm of the preset adjustment algorithm.
The sending module 102 is configured to send each display data to each voltage output channel 103 according to new row display information, where the display data in the new row display information at the jth order is sent to the jth voltage output channel 103, and j is greater than or equal to 1 and less than or equal to X.
The voltage output channel 103 is configured to output a corresponding data voltage through a voltage output terminal according to the received display data. That is, the display data in the ith line of the original line display information is sent to the pth (i) voltage output channel 103, and the data voltage output by the pth (i) voltage output channel 103 is the data voltage corresponding to the ith line.
In the embodiment of the present disclosure, the adjusting module 104 is arranged to adjust the sequence of the display data in the original row display information to obtain new row display information, and the sending module 102 is configured to send each display data to each voltage output channel 103 according to the new row display information, so that the data voltage output by the (p) (i) th voltage output channel 103 is the data voltage corresponding to the ith line, and the data voltage output by the (p) (i) th voltage output channel 103 can be loaded onto the (p) (i) th pad, thereby being capable of adapting to a design in which the pad is connected to the data line in a non-sequential manner.
Fig. 7 is a schematic structural diagram of the voltage output channel 103 in the embodiment of the present disclosure, as shown in fig. 7, the voltage output channel 103 generally includes a digital-to-analog conversion circuit 1031 and an output buffer circuit 1032, wherein an input terminal of the analog-to-digital conversion circuit 1031 is electrically connected to the sending module 102, an output terminal of the analog-to-digital conversion circuit 1031 is electrically connected to an input terminal of the output buffer circuit 1032, and an output terminal of the output buffer circuit 1032 is electrically connected to a data voltage output terminal of the voltage output channel 103. An analog-to-digital conversion circuit 1031 for performing an analog-to-digital conversion process on the display data (a digital signal) to generate a data voltage (an analog signal); the output buffer generally adopts a unity gain operational amplifier (with better unity gain) structure for improving the driving capability of the data voltage.
It should be noted that the specific structure of the voltage output channel 103 shown in fig. 7 is only for exemplary purposes, and does not limit the technical solution of the present disclosure.
In some embodiments, X is an even number, and the original row display information is located from the 1 st bit to the c th bit1Each of the display data of the order, the order being the first order in the display information of the new line
Figure BDA0003445800620000091
Order to the first
Figure BDA0003445800620000092
Between the orders (includingFirst, the
Figure BDA0003445800620000093
The order and the first
Figure BDA0003445800620000094
Order of bits), c1And a are all preset positive integers,
Figure BDA0003445800620000095
and a is not less than c1. At the X-c within the original line display information2The display data of +1 bit to Xth bit, the bit in the new row display information being at the second position
Figure BDA0003445800620000096
Order to the first
Figure BDA0003445800620000097
Between the orders (including the first
Figure BDA0003445800620000098
The order and the first
Figure BDA0003445800620000099
)，c2Is > 1 and is c2Is a positive integer, c2And b are all preset positive integers,
Figure BDA00034458006200000910
and b is not less than c2。
With the above design, some of the voltage output channels 103 located at the middle position in the source driver 1 can be enabled to output some of the data lines (c in total) near the edge of the display region Q1 in the display region Q11+c2Bar) to adapt to a scenario in which a pad located at a middle position is electrically connected to a data line located at an edge position. Wherein, c1、c2The specific values of a and b can be set according to actual needs.
In some embodiments, for a bit within the original line display information1 st order to c th order1The display data of the order, the higher the order of the display data in the display information of the original line is, the lower the order in the display information of the new line is; for the display information at the X-c th position in the original line2The display data of +1 bit to the X-th bit, the higher the bit number of the display data in the original row display information is, the lower the bit number in the new row display information is.
In some embodiments, the original row display information is located within the second row display information
Figure BDA00034458006200000911
Order to the first
Figure BDA00034458006200000912
Each of the display data of the order, the order being the first order in the display information of the new line
Figure BDA00034458006200000913
Order to the first
Figure BDA00034458006200000914
Between the orders (including the first
Figure BDA00034458006200000915
The order and the first
Figure BDA00034458006200000916
Bit order); the original line display information is positioned at the second
Figure BDA00034458006200000917
Order to the first
Figure BDA00034458006200000918
Each of the display data of the order, the order being the first order in the display information of the new line
Figure BDA00034458006200000919
Order to the first
Figure BDA00034458006200000920
Between the orders (including the first
Figure BDA00034458006200000921
The order and the first
Figure BDA00034458006200000922
Bit order); wherein the content of the first and second substances,
Figure BDA0003445800620000101
I1、I2、N1、N2are all positive integers which are set in advance,
Figure BDA0003445800620000102
the operation results of (1) are all positive integers.
In some embodiments, the display data at the ith position in the original row display information has the position at the p (i) th position in the new row display information, i is greater than or equal to 1 and less than or equal to X, i is a positive integer, and the p (i) and i satisfy the following relationship:
1) in i ∈ [1, c ]1]And P (i) is:
Figure BDA0003445800620000103
wherein the content of the first and second substances,
Figure BDA0003445800620000104
f1＝(c1-i)％I1(ii) a I.e. e1Is composed of
Figure BDA0003445800620000105
Is rounded down, f1Is c1-I and I1And making a remainder after division operation.
2) In that
Figure BDA0003445800620000106
And P (i) is:
P(i)＝i-c1
3) in that
Figure BDA0003445800620000107
And P (i) is:
Figure BDA0003445800620000108
wherein the content of the first and second substances,
Figure BDA0003445800620000109
i.e. e2Is composed of
Figure BDA00034458006200001010
Is rounded down, f2Is composed of
Figure BDA00034458006200001011
And N1And making a remainder after division operation.
4) In that
Figure BDA00034458006200001012
And P (i) is:
Figure BDA00034458006200001013
wherein the content of the first and second substances,
Figure BDA0003445800620000111
i.e. e3Is composed of
Figure BDA0003445800620000112
Is rounded down, f3Is composed of
Figure BDA0003445800620000113
And N2And making a remainder after division operation.
5) In that
Figure BDA0003445800620000114
And P (i) is:
P(i)＝i+c2
6) in i ∈ [ X-c ]2+1，X]And P (i) is:
Figure BDA0003445800620000115
wherein the content of the first and second substances,
Figure BDA0003445800620000116
f4＝(X-i)％I2(ii) a I.e. e4Is composed of
Figure BDA0003445800620000117
Is rounded down, f4Is X-I and I2And making a remainder after division operation.
Taking the above-mentioned situation as an example, the process of adjusting the sequence of the display data in the original line display information by the adjusting module 104 to obtain the new line display information may be regarded as performing reverse-order insertion processing on the display data corresponding to some data lines in the display area Q1 close to the edge of the display area Q1.
Specifically, the display region Q1 of the display panel may be divided into a left half display region Q1 and a right half display region Q1, the 1 st to the 1 st bars
Figure BDA0003445800620000118
The data lines are located in the left half of the display area Q1
Figure BDA0003445800620000119
The through xth data lines are located in the right half display area Q1. Accordingly, the display data within the original line display information may be divided into left half-side display data and right half-side display data, wherein the original line display information is located from 1 st to 1 st
Figure BDA00034458006200001110
The display data of the display is left half display data, and the first row display information is positioned at the second row
Figure BDA00034458006200001111
The display data of the second to the xth are right half display data.
At this time, the display data located from the 1 st to the c1 th in the original line display information are display data (c 1 in total) which are required to be partially inserted in reverse order in the left half display data, and the display data located from the X-c th in the original line display information2The display data of +1 to xth are display data (c 2 in total) that require local reverse-order insertion processing within the left half display data.
C requiring local reverse-order insertion processing in left half side display data1Display data per I1The display data as a group is divided into
Figure BDA0003445800620000121
A left half side data group to be processed; c for performing insertion processing requiring local reverse order in right half display data2Display data per I2The display data as a group is divided into
Figure BDA0003445800620000122
The right half of the data set to be processed. New line display information inner
Figure BDA0003445800620000123
Order to the first
Figure BDA0003445800620000124
The region of the order is the left half reverse order insertion region, the second in the new row display information
Figure BDA0003445800620000125
Order to the first
Figure BDA0003445800620000126
The bit order region is a right-half reverse-order insertion interval.
In will
Figure BDA0003445800620000127
When a left half side data group to be processed is inserted into the left half side reverse order insertion interval in a reverse order mannerN is arranged in the front of any left half data group to be processed1Display data without reverse-order insertion processing, so that the left half reverse-order insertion interval is totally provided
Figure BDA0003445800620000128
Display data, that is to say
Figure BDA0003445800620000129
In will
Figure BDA00034458006200001210
When the right half-side data group to be processed is inserted into the right half-side reverse-sequence insertion interval in a reverse sequence manner, N is arranged in the front of any right half-side data group to be processed and is adjacent to the right half-side data group to be processed2Display data without reverse-order insertion processing, so that the right-side reverse-order insertion interval has total display data
Figure BDA00034458006200001211
Display data, that is to say
Figure BDA00034458006200001212
In some embodiments, c1＝c2，I1＝I2，N1＝N2(ii) a That is, the left half display data and the right half display data are symmetrically processed in the adjustment manner when the order adjustment is performed.
In some embodiments, I1Has a value range of [2,5 ]]；I2Has a value range of [2,5 ]]；N1Has a value range of [2,5 ]]；N2Has a value range of [2,5 ]]. In practical application, I can be adjusted according to actual needs1、I2、N1、N2The value of (a) is set and adjusted.
As a specific example, X takes the value 2160, c1＝c2＝300，I1＝I2＝4，N1＝N2When the value is 2, the value a-b-450 is calculated, and the new line displays the second line in the informationThe area from 631 bits to 1080 bits is the left half reverse insertion section, and the area from 1081 bits to 1531 bits in the new row of display information is the right half reverse insertion section. i and P (i) satisfy:
1) when i ∈ [1, 300], P (i) is:
P(i)＝630+6*e1+f1+3
wherein the content of the first and second substances,
Figure BDA0003445800620000131
f1 ═ 4 (300-i)%; i.e. e1Is composed of
Figure BDA0003445800620000132
Is rounded down, f1The remainder after division is taken as 300-i and 4.
2) When i ∈ [301, 930], P (i) is:
P(i)＝i-300
3) when i ∈ [931, 1080], P (i) is:
P(i)＝630+6*e2+f1+1
wherein the content of the first and second substances,
Figure BDA0003445800620000133
f2＝[i-931]% 2; i.e. e2Is composed of
Figure BDA0003445800620000134
Is rounded down, f2The remainder after division is i-931 and 2.
4) When i ∈ [1081, 1230], P (i) is:
P(i)＝1080+6*e3+f3+1
wherein the content of the first and second substances,
Figure BDA0003445800620000135
f3(i-1081)% 2; i.e. e3Is composed of
Figure BDA0003445800620000136
Is rounded down, f3Is divided by i-1081 and 2The remainder after the arithmetic operation.
5) When i ∈ [1231, 1860], P (i) is:
P(i)＝i+300
6) when i ∈ [1861, 2160], P (i) is:
P(i)＝1080+6*e4+f4+3
wherein the content of the first and second substances,
Figure BDA0003445800620000137
f4(2160-i)% 4; i.e. e4Is composed of
Figure BDA0003445800620000138
Is rounded down, f4The remainder after division is 2160-i and 4.
Fig. 8 is a schematic circuit structure diagram of another source driver 1 provided in the embodiment of the present disclosure, and as shown in fig. 8, the source driver 1 provided in the embodiment of the present disclosure includes not only the receiving module 101, the adjusting module 104, the sending module 102, and the voltage output channel 103 according to the previous embodiments, but also an algorithm setting module 105, wherein the algorithm setting module 105 is connected to the adjusting module 104, and the algorithm setting module 105 is configured to set c according to external input information1、c2、I1、I2、N1And N2A value of at least one of them. That is, the parameters in the setting and adjusting algorithm used by the adjusting module 104 can be set by external input to meet the use requirements of different scenes.
Based on the same inventive concept, the embodiment of the present disclosure also provides a data driving method, which is based on the source driver 1 provided in the previous embodiment. For a detailed description of the source driver 1, reference may be made to the contents in the foregoing embodiments, and details are not described here. Fig. 9 is a flowchart of a data driving method according to an embodiment of the disclosure, and as shown in fig. 9, the data driving method includes:
step S1, the receiving adjustment module receives the original line display information, where the original line display information includes X pieces of display data arranged in sequence.
And step S2, the adjusting module adjusts the sequence of the display data in the original line display information according to a preset adjusting algorithm to obtain new line display information.
And step S3, the sending module sends each display data to each voltage output channel according to the new row display information, wherein the display data positioned at the jth order in the new row display information is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X.
And step S4, the voltage output channel outputs corresponding data voltage through the voltage output end according to the received display data.
For the specific description of each step, reference may be made to the related description of each module in the foregoing embodiment, and details are not described here.
In some embodiments, an algorithm setting module is disposed in the source driver 1, and before step S2, the method further includes: the algorithm setting module sets a preset adjusting algorithm according to external input information. For example, c is set according to a preset adjustment algorithm1、c2、I1、I2、N1And N2A value of at least one of them.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, where the display panel includes a display area Q1 and a peripheral area Q2 located around the display area Q1, a source driver 1 is disposed in the peripheral area Q2, the source driver 1 is the source driver 1 provided in any of the foregoing embodiments, and for the specific description of the source driver 1, reference may be made to the contents in the foregoing embodiments, and details are not repeated here.
In some embodiments, a pixel cell array and X data lines arranged along a first direction are disposed in the display area Q1, and the pixel cells are electrically connected to the corresponding data lines; the display data at the ith position in the original row display information has the position of the P (i) th position in the new row display information, i is more than or equal to 1 and less than or equal to X, and i is a positive integer; the data line in the ith display area Q1 is electrically connected to the voltage output channel in the pth (i) of the source driver 1.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which includes a display panel, and the display panel provided by the foregoing embodiment is adopted as the display panel.
The display device provided by the embodiment can be: any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
Further, the display device may also include various types of display devices, such as a liquid crystal display device, an organic electroluminescent display device (e.g., an OLED display device, a QLED display device), without being limited thereto.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims (12)

1. A source driver, comprising: the device comprises a receiving module, an adjusting module, a sending module and X voltage output channels, wherein X is more than or equal to 2 and is a positive integer;
the receiving module is used for receiving original line display information, and the original line display information comprises X pieces of display data which are sequentially arranged;
the adjusting module is used for adjusting the sequence of the display data in the original row display information according to a preset adjusting algorithm to obtain new row display information;
the sending module is used for sending each display data to each voltage output channel according to the new row display information, wherein the display data in the new row display information at the jth order is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X;
the voltage output channel is used for outputting corresponding data voltage through a voltage output end according to the received display data.
2. The source driver of claim 1, wherein X is an even number, and the original row of display information is located from the 1 st bit to the c th bit1Each of the display data of the order in which the order in the new line of display information is located is
Figure FDA0003445800610000011
Order to the first
Figure FDA0003445800610000012
Between the orders of bits, c1And a are all preset positive integers,
Figure FDA0003445800610000013
and a is not less than c1；
The original line display information is positioned at the X-c2(ii) each of + 1-bit to Xth-bit display data, the bit in the new line of display information being at the Xth bit
Figure FDA0003445800610000014
Order to the first
Figure FDA0003445800610000015
Between the orders of bits, c2Is > 1 and is c2Is a positive integer, c2And b are all preset positive integers,
Figure FDA0003445800610000016
and b is not less than c2。
3. The source driver of claim 2, wherein the display information is displayed for the 1 st to c-th bits within the original row1Display data of a higher order within the original line display informationThe lower the number of bits in the new row of display information;
for the display information located at X-c within the original line2And display data from +1 th order to X-th order, wherein the higher the order of the display data in the original line display information is, the lower the order of the display data in the new line display information is.
4. The source driver of claim 2, wherein the original row of display information is located at the second position within the original row of display information
Figure FDA0003445800610000021
Order to the first
Figure FDA0003445800610000022
Each of the display data of the order in which the order in the new line of display information is located is
Figure FDA0003445800610000023
Order to the first
Figure FDA0003445800610000024
Between the bits;
the original line display information is positioned at the second position
Figure FDA0003445800610000025
Order to the first
Figure FDA0003445800610000026
Each of the display data of the order in which the order in the new line of display information is located is
Figure FDA0003445800610000027
Order to the first
Figure FDA0003445800610000028
Between the bits;
wherein，
Figure FDA0003445800610000029
I1、I2、N1、N2Are all positive integers which are set in advance,
Figure FDA00034458006100000210
Figure FDA00034458006100000211
the operation results of (1) are all positive integers.
5. The source driver of claim 4, wherein the display data at the i-th order in the original row of display information has the P (i) -th order, i ≦ 1 ≦ X, and i is a positive integer;
in i ∈ [1, c ]1]And P (i) is:
Figure FDA00034458006100000212
e1is composed of
Figure FDA00034458006100000213
Is rounded down, f1Is c1-I and I1Making remainder after division operation;
in that
Figure FDA00034458006100000214
And P (i) is:
P(i)＝i-c1
in that
Figure FDA00034458006100000215
And P (i) is:
Figure FDA0003445800610000031
e2is composed of
Figure FDA0003445800610000032
Is rounded down, f2Is composed of
Figure FDA0003445800610000033
And N1Making remainder after division operation;
in that
Figure FDA0003445800610000034
And P (i) is:
Figure FDA0003445800610000035
e3is composed of
Figure FDA0003445800610000036
Is rounded down, f3Is composed of
Figure FDA0003445800610000037
And N2Making remainder after division operation;
in that
Figure FDA0003445800610000038
And P (i) is:
P(i)＝i+c2
in i ∈ [ X-c ]2+1，X]And P (i) is:
Figure FDA0003445800610000039
e4is composed of
Figure FDA00034458006100000310
Is rounded down, f4Is X-I and I2And making a remainder after division operation.
6. The source driver of claim 4 or 5, wherein c is1＝c2，I1＝I2，N1＝N2。
7. The source driver of claim 4 or 5, wherein I is1Has a value range of [2,5 ]]；
I2Has a value range of [2,5 ]]；
N1Has a value range of [2,5 ]]；
N2Has a value range of [2,5 ]]。
8. The source driver of claim 4 or 5, further comprising:
an algorithm setting module configured to set c according to external input information1、c2、I1、I2、N1And N2A value of at least one of them.
9. A display panel, comprising: a display area and a peripheral area around the display area, the peripheral area having the source driver as claimed in any one of claims 1 to 8 disposed therein.
10. The display panel according to claim 9, wherein an array of pixel units and X data lines arranged along a first direction are disposed in the display region, and the pixel units are electrically connected to the corresponding data lines;
the display data at the ith position in the original row display information has the position at the P (i) th position in the new row display information, i is more than or equal to 1 and less than or equal to X, and i is a positive integer;
the data line positioned at the ith in the display area is electrically connected with the voltage output channel positioned at the p (i) th in the source driver.
11. A display device, comprising: a display panel as claimed in claim 9 or 10.
12. A data driving method based on the source driver of any one of claims 1 to 8, the data driving method comprising:
the receiving and adjusting module receives original line display information, wherein the original line display information comprises X pieces of display data which are sequentially arranged;
the adjusting module adjusts the sequence of the display data in the original row display information according to a preset adjusting algorithm to obtain new row display information;
the receiving module sends the display data to the voltage output channels respectively according to the new row display information, wherein the display data in the new row display information at the jth order is sent to the jth voltage output channel, and j is more than or equal to 1 and less than or equal to X;
and the voltage output channel outputs corresponding data voltage according to the received display data.
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