CN114281753A - Missile inertia measurement front-end system - Google Patents
Missile inertia measurement front-end system Download PDFInfo
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- CN114281753A CN114281753A CN202111590427.8A CN202111590427A CN114281753A CN 114281753 A CN114281753 A CN 114281753A CN 202111590427 A CN202111590427 A CN 202111590427A CN 114281753 A CN114281753 A CN 114281753A
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Abstract
The invention discloses a missile inertia measurement front-end system. The system comprises a fiber-optic gyroscope, an accelerometer, a digital signal processor, a field programmable gate array and a communication interface; the fiber-optic gyroscope is respectively connected with the digital signal processor and the field programmable gate array; the accelerometer is respectively connected with the digital signal processor and the field programmable gate array; the digital signal processor is connected with the field programmable gate array; the field programmable gate array is connected with the communication interface. The invention innovatively adopts the digital signal processor and the field programmable gate array cooperative processing technology, realizes the transparent operation of the DSP on the peripheral equipment, and improves the operation efficiency and the operation reliability of the DSP, thereby reducing the complexity of the CPU template, realizing all the peripheral equipment by FPGA software programming, reducing the design difficulty and the development period of the CPU template, further optimizing the system performance index and improving the practical value of engineering.
Description
Technical Field
The invention relates to the technical field of missile inertia measurement, in particular to a missile inertia measurement front-end system.
Background
With the development of aerospace technology, novel aerospace vehicles are emerging continuously, and missiles with various purposes are moving to high-precision and miniaturized roads. The guided missile is required to have high guidance control precision and good stability and can adapt to a complex external environment, so that the guided missile has a complex control algorithm, high calculation speed and high precision. The missile is required to be small in size and good in maneuverability in miniaturization, under the condition of the same effective load, higher requirements are provided for the weight and the volume of a control system, the higher the performance of the control system is, the better the volume is, the smaller the volume is, and the lighter the weight is, the better the control system is. Due to the performance index and the volume limitation, the prior art urgently needs to develop an integrated inertia measurement front-end product with smaller volume, lighter weight and better performance index.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a missile inertia measurement front-end system.
In order to achieve the purpose, the invention provides the following scheme:
a missile inertia measurement front-end system, comprising: the system comprises a fiber-optic gyroscope, an accelerometer, a digital signal processor, a field programmable gate array and a communication interface;
the optical fiber gyroscope is respectively connected with the digital signal processor and the field programmable gate array; the accelerometer is respectively connected with the digital signal processor and the field programmable gate array; the digital signal processor is connected with the field programmable gate array; the field programmable gate array is connected with the communication interface.
Preferably, the communication interface includes: a synchronous half-duplex RS-485 data interface, a synchronous simplex RS-485 data interface and a full-duplex RS-485 data interface;
the synchronous half-duplex RS-485 data interface, the synchronous simplex RS-485 data interface and the full-duplex RS-485 data interface are all connected with the field programmable gate array.
Preferably, the synchronous half-duplex RS-485 data interface includes: the optical coupler comprises a first optical coupler, a second optical coupler, a first differential chip and a second differential chip;
the first optical coupler is respectively connected with the first differential chip and the second differential chip; the second optical coupler is respectively connected with the first differential chip and the second differential chip;
preferably, a first pull-up resistor, a first pull-down resistor and a first matching resistor are arranged between the first differential signal output port and the second differential signal output port of the first differential chip;
and a third pull-up resistor, a fourth pull-down resistor and a second matching resistor are arranged between the first differential signal output port and the second differential signal output port of the second differential chip.
Preferably, the first pull-up resistor, the first pull-down resistor, the third pull-up resistor and the fourth pull-down resistor have a resistance of 510 Ω.
Preferably, the first matching resistor and the second matching resistor have a resistance of 120 Ω.
Preferably, a crystal oscillator is further included;
the crystal oscillator is respectively connected with the digital signal processor and the field programmable gate array.
Preferably, the digital signal processor is of the model TMS320F 28335.
Preferably, the model of the field programmable gate array is A3P 1000.
Preferably, the digital signal processor, the field programmable gate array and the communication interface are integrated on a PCB board.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the missile inertia measurement front-end system provided by the invention innovatively adopts a digital signal processor and field programmable gate array (namely DSP + FPGA) cooperative processing technology, realizes the transparent operation of DSP on peripheral equipment, improves the operation efficiency and the operation reliability of DSP, thereby reducing the complexity of a CPU template, and reduces the design difficulty and the development period of the CPU template by programming all the peripheral equipment through FPGA software, thereby optimizing the performance index of the system and improving the practical value of engineering.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is a schematic block diagram of a missile inertia measurement front-end system provided by the present invention;
FIG. 2 is a schematic diagram of DSP and FPGA interfaces provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of a synchronous half-duplex RS485 data interface according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a synchronous half-duplex RS485 data interface circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a synchronous simplex RS485 data interface according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a synchronous simplex RS485 data interface circuit according to an embodiment of the present invention;
FIG. 7 is a flowchart of the DSP working software according to an embodiment of the present invention;
fig. 8 is a block diagram of an FPGA software structure according to an embodiment of the present invention.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
As shown in fig. 1, the missile inertia measurement front-end system provided by the invention comprises: the system comprises a fiber-optic gyroscope, an accelerometer, a digital signal processor, a field programmable gate array and a communication interface.
The fiber-optic gyroscope is respectively connected with the digital signal processor and the field programmable gate array. The accelerometer is respectively connected with the digital signal processor and the field programmable gate array. The digital signal processor is connected with the field programmable gate array. The field programmable gate array is connected with the communication interface.
The Digital Signal Processor (DSP) adopts TMS320F28335 produced by TI company, is a high-performance low-power-consumption 32-bit floating-point type digital signal processor, and has a main clock working frequency of 150MHz and a single-cycle instruction execution time of 6.67 ns. The circuit integrates various enhanced control peripherals and a floating point arithmetic unit supporting single-precision IEEE-754 standard, and provides a good platform for the analysis and processing of high-precision complex data and the realization of the application of other motor motion control fields. The DSP internal processor integrates 256K 16 Flash memory, 8K 16 boot ROM, a digital operation table and 1K 16 OTP ROM, and is suitable for the occasion of missile flight guidance control high-speed operation. In the application process, the DSP obtains the inertial flight track and the flight distance based on the superposition fitting of the angular velocity information acquired by the fiber-optic gyroscope and the flight acceleration information acquired by the accelerometer. Since the calculation process is the prior art, it is not described herein again.
Meanwhile, although the DSP chip has high-speed and high-precision data processing capacity, the number of peripheral control interfaces is small. The central processing system adopts a DSP + FPGA combined mode, takes a DSP chip as a central processing module, takes an FPGA as a double-port RAM module, an FIFO module and an RS485 communication module, and plays a role in time sequence control task, and receives and sends data and instructions. FPGA adopts ACTEL company A3P1000 of 100 ten thousand gates based on the third generation of Flash architecture. The FPGA working clock and the DSP share the same external crystal oscillator, and the working clock is 40M, so that the working precision is ensured. The interface principle design of the DSP and the FPGA is shown in figure 2. In the invention, the FPGA is mainly used for carrying out time sequence control on the acquired data and further transmitting the data to the DSP according to a time sequence control result.
The RS-485 synchronous half duplex/simplex communication is a bus communication mode based on HDLC protocol control, and the HDLC is a data link layer protocol for transmitting data and facing bits on a synchronous network, and is widely used as a control protocol of a data link layer. However, in china, there is no HDLC autonomous product, and among them, ASIC chips of HDLC include MC92460 by Motorola, MK5025 by ST, MT8952B by Zarlink, and the like. Innocor, Xinlinx corporation introduced IP cores (intellectual property cores) that could implement HDLC functionality in FPGAs, and these IP cores needed to purchase licenses for use. In addition, the purchased ASIC chip and IP core are subject to various limitations in application, such as the CRC generator polynomial of the overall requirement may be different from the CRC generator polynomial of the purchased product, and the start bit/stop bit may be different. Therefore, in order to solve the problem in the prior art and reduce the communication cost, the communication interface adopted by the invention is arranged into an interface module comprising a synchronous half-duplex RS-485 data interface, a synchronous simplex RS-485 data interface and a full-duplex RS-485 data interface.
The synchronous half-duplex RS-485 data interface, the synchronous simplex RS-485 data interface and the full-duplex RS-485 data interface are all connected with the field programmable gate array.
In order to increase the communication rate and enable the system to have higher data throughput, the synchronous half-duplex RS-485 data interface adopted by the invention comprises: the optical coupler comprises a first optical coupler, a second optical coupler, a first differential chip and a second differential chip.
The first optical coupler is respectively connected with the first differential chip and the second differential chip. The second optical coupler is respectively connected with the first differential chip and the second differential chip.
Preferably, a first pull-up resistor, a first pull-down resistor and a first matching resistor are arranged between the first differential signal output port and the second differential signal output port of the first differential chip.
And a third pull-up resistor, a fourth pull-down resistor and a second matching resistor are arranged between the first differential signal output port and the second differential signal output port of the second differential chip.
Preferably, the resistance values of the first pull-up resistor, the first pull-down resistor, the third pull-up resistor and the fourth pull-down resistor are all 510 Ω, so as to prevent the problem that the output state of the receiving end is uncertain when the receiving end is idle or open.
Preferably, the first matching resistor and the second matching resistor each have a resistance of 120 Ω to suppress a reflection phenomenon formed at the ends of the transmission line.
For example, in the actual design process, the design requirements of the synchronous half-duplex RS-485 interface are as follows:
a) the communication rate is 4 Mbps.
b) Matching resistors with the resistance value of 120 omega are added at the high end and the low end of the data and sclk two groups of differential signals so as to inhibit the reflection phenomenon formed at the transmission line terminal.
c) And an upper pull-down resistor and a lower pull-down resistor are respectively used at the high end and the low end of the data and sclk two groups of differential signals, and the resistance value is 510 omega.
d) And when the inertial measurement front end is in a receiving state in idle. When data is transmitted, the output is enabled, and the data is transmitted.
e) The optocoupler uses GH6651J for the midrange 44, and the RS-485 driver uses MAX3088ESA from MAXIM.
The design principle and the circuit design principle of the synchronous half-duplex RS-485 interface are shown in figures 3 and 4.
The synchronous simplex RS-485 is used for communicating with the telemetering device of the missile, so that the inertial measurement front end is a data sending end, the telemetering device is a data receiving end, the schematic diagram of a communication interface circuit is shown in figure 5, and the schematic diagram is designed as shown in figure 6. The inertia measurement front end sends the sensitive attitude information and the working state of the product to the missile-borne remote measuring device through a synchronous simplex RS-485 interface.
Based on the specific structure of the missile inertia measurement front-end system, the motion parameters of the missile can be directly sensed during implementation, and information communication and interaction can be carried out with other equipment on the missile. And only 4 lines are needed to complete the bus communication on the missile, the structure is simple, and the use is convenient.
The design technology of the inertia measurement front-end system of the RS-485 synchronous half-duplex simplex communication based on the HDLC protocol can realize four-wire system communication of all device information on a bomb, namely the communication information of all the devices of the whole bomb is hung on an RS-485 synchronous bus, the wiring is simple and reliable, the communication rate is as high as 4Mbps, and the data throughput rate is high. Meanwhile, the CRC technology is adopted to detect the correctness of data transmission, so that the reliable transmission of signals is ensured. The CRC can be configured at will in engineering application, is flexible and reliable, has independent intellectual property rights, meets the communication requirements of multiple types of RS-485, and has higher engineering practical value.
Furthermore, in order to reduce the volume of a missile inertia measurement front-end system, the digital signal processor, the field programmable gate array and the communication interface are integrated on the PCB. For example, the inertial measurement front-end core signal processing board can be designed integrally by adopting a 6-layer PCB, and has the characteristics of high speed, high density, high reliability and the like. Meanwhile, the weight of the product is less than 3.0kg, and the volume is less than 90mm multiplied by 50 mm.
In the specific implementation process, software programs in the DSP and the FPGA can be set according to actual requirements, and the technical solution provided by the present invention is described below with a specific embodiment in combination with a specific process of functions implemented by a software design program.
The inertial measurement front end consists of two parts, namely DSP software and FPGA software. The DSP software mainly comprises four parts, namely a power-on initialization module, a self-checking module, a synchronous RS-485 receiving interrupt program, an uploading module and an inertia measurement data acquisition and compensation module. In order to meet the requirement of confidentiality, a JTAG interface of a DSP chip is not led out, a serial port guide mode uploading scheme is adopted for uploading the inertial measurement front-end DSP software, the JTAG interface is cancelled, and a third party can be effectively prevented from acquiring a software core program in a debugging mode. The working flow chart of the inertial measurement front-end DSP software is shown in figure 7.
The FPGA software at the front end of the inertial measurement comprises an A \ D synchronous data acquisition module, asynchronous serial port communication, synchronous serial port communication, a parallel bus module, an FIFO (first in first out) and logic control and the like, is in modular design and is realized by using a Verilog HDL (hardware description language), and is written into an information processing circuit FPGA to complete the design after simulation, synthesis, layout and wiring, so that the operation is simple and convenient. The structural block diagram of the design structure of the FPGA software at the front end of the inertial measurement is shown in figure 8.
The RS485 data link layer protocol may be divided into according to the format of data frame control: character-oriented data link layer protocols and bit-oriented data link layer protocols. The HDLC protocol for the inertial measurement front-end system is a bit-oriented data link protocol, in the bit-oriented data link protocol, a frame head and a frame tail are specific 8-bit binary codes 01111110(0x7E), monitoring of a link is achieved through a control field, and efficient and reliable transparent transmission can be achieved through multiple coding modes. As shown in table 1, an RS-485 communication frame format based on the HDLC protocol can be obtained.
Table 1 RS-485 communication frame format design table based on HDLC protocol
Wherein:
FLAG: frame start/end flag, 8-bit binary code 01111110(0x7E), the number of frame start/end flags is 4.
AR: slave address, 8-bit binary integer, 0x 45. And can be configured as desired.
AT: master address, 8-bit binary integer, 0x 52. And can be configured as desired.
CO: command code, 8-bit binary integer.
ST: and the response state code is the response state returned to the master station by the slave station, and the range of 8-bit binary integers is 0-255.
And (3) CP: and the length of the control parameter, the binary code, which is sent to the slave station by the master station is integral multiple of the 8-bit binary code.
SP: the slave station sends back the response parameter of the master station, the binary code, the length of which is integral multiple of the eight-bit binary code.
CRC: the check code adopts 16-bit cyclic redundancy check code, CCITT-CRC, and the generator polynomial is X16+X12+X5+1, the data other than FLAG bit and CRC all participate in the CRC calculation (station address + ST + SP). The initial value of CRC is 0 xFFFF. The final result of CRC is the XOR of the data calculation result and 0 xFFFF. The 16-bit CRC transmission is transmitted with the lower bits first and the upper bits second.
All data including CRC check codes are subjected to zero insertion sending and zero deletion receiving according to an HDLC (high level data link control) rule, and transparent transmission of the received and transmitted data is achieved.
The specific implementation of zero bit insertion is: at the data sending end, the valid data field of the frame to be sent, i.e. other fields except the frame head and the frame tail, is filled with a '0' immediately after every 5 '1's are detected continuously. After such processing, the valid data field does not have 6 consecutive "1" s. At the data receiving end, after detecting the frame header F mark, scanning the following bit stream, and deleting the following 0's of 5 consecutive 1's to restore the original bit stream when finding 5 consecutive 1's. This ensures that frame delimitation errors do not occur.
Based on the specific process of the software setting, the RS-485 synchronous half duplex/simplex communication in the inertial measurement front-end system does not depend on any character coding set, transparent transmission of data can be easily realized by adopting a bit filling method, and binary bit strings with any length can be transmitted. The HDLC adopts a uniform frame format to realize the transmission of data, commands and responses, and completes various specified link operation functions by changing the bit mode of a control field in a frame, and the RS-485 synchronous half-duplex/simplex design is very convenient and fast.
Then, based on the specific structure of the missile inertia measurement front-end system provided by the invention, the invention has the following advantages:
1. the design technology of the inertia measurement front-end system based on the synchronous RS485 half-duplex simplex communication of the HDLC protocol innovatively adopts the DSP + FPGA cooperative processing technology, and realizes the RS-485 synchronous half-duplex/simplex reliable communication. The synchronous RS-485 communication breaks through the HDLC IP core independent design key technology, does not need to purchase a special ASIC chip or a paid IP core, can be configured with CRC check at will in engineering application, is flexible and reliable, has independent intellectual property rights, meets the communication requirements of multiple types of RS-485, and has higher engineering practical value.
2. In order to meet the requirement of xx-17AE inertia measurement front-end communication, the invention adopts an inertia measurement front-end system design technology of RS-485 synchronous half-duplex simplex communication based on an HDLC protocol, the HDLC communication realizes four-wire system communication of all equipment information on a bomb, namely all the equipment communication information of the whole bomb is hung on an RS-485 synchronous bus, the wiring is simple and reliable, the communication rate is as high as 4Mbps, and the data throughput rate is higher. Meanwhile, the CRC technology is adopted to detect the correctness of data transmission, so that the reliable transmission of signals is ensured.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the disclosed embodiments includes the full ambit of the claims, as well as all available equivalents of the claims. As used in this application, although the terms "first," "second," etc. may be used in this application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, unless the meaning of the description changes, so long as all occurrences of the "first element" are renamed consistently and all occurrences of the "second element" are renamed consistently. The first and second elements are both elements, but may not be the same element. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method or device comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit may be merely a division of a logical function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A missile inertia measurement front-end system, comprising: the system comprises a fiber-optic gyroscope, an accelerometer, a digital signal processor, a field programmable gate array and a communication interface;
the optical fiber gyroscope is respectively connected with the digital signal processor and the field programmable gate array; the accelerometer is respectively connected with the digital signal processor and the field programmable gate array; the digital signal processor is connected with the field programmable gate array; the field programmable gate array is connected with the communication interface.
2. The missile inertia measurement front-end system of claim 1, wherein the communication interface comprises: a synchronous half-duplex RS-485 data interface, a synchronous simplex RS-485 data interface and a full-duplex RS-485 data interface;
the synchronous half-duplex RS-485 data interface, the synchronous simplex RS-485 data interface and the full-duplex RS-485 data interface are all connected with the field programmable gate array.
3. The missile inertia measurement front-end system of claim 2, wherein the synchronous half-duplex RS-485 data interface comprises: the optical coupler comprises a first optical coupler, a second optical coupler, a first differential chip and a second differential chip;
the first optical coupler is respectively connected with the first differential chip and the second differential chip; the second optical coupler is respectively connected with the first differential chip and the second differential chip.
4. The missile inertia measurement front-end system of claim 3, wherein a first pull-up resistor, a first pull-down resistor and a first matching resistor are arranged between the first differential signal output port and the second differential signal output port of the first differential chip;
and a third pull-up resistor, a fourth pull-down resistor and a second matching resistor are arranged between the first differential signal output port and the second differential signal output port of the second differential chip.
5. The missile inertia measurement front-end system of claim 4, wherein the first pull-up resistor, the first pull-down resistor, the third pull-up resistor, and the fourth pull-down resistor are all 510 Ω.
6. The missile inertia measurement front-end system of claim 4, wherein the first and second matching resistors each have a resistance of 120 Ω.
7. The missile inertia measurement front-end system of claim 1, further comprising a crystal oscillator;
the crystal oscillator is respectively connected with the digital signal processor and the field programmable gate array.
8. The missile inertia measurement front-end system of claim 7, wherein the digital signal processor is model TMS320F 28335.
9. The missile inertia measurement front-end system of claim 7, wherein the field programmable gate array is model A3P 1000.
10. The missile inertia measurement front-end system of claim 1, wherein the digital signal processor, the field programmable gate array, and the communication interface are integrated on a PCB.
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