CN114281560A

CN114281560A - Processing unit, synchronization method for a processing unit and corresponding product

Info

Publication number: CN114281560A
Application number: CN202011036272.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Anhui Cambricon Information Technology Co Ltd
Current assignee: Anhui Cambricon Information Technology Co Ltd
Priority date: 2020-09-27
Filing date: 2020-09-27
Publication date: 2022-04-05

Abstract

The present disclosure discloses a processing unit, a multi-core processor, a synchronization method for a processing unit/multi-core processing unit and related products. The processing unit may be implemented as a computing device included in a combined processing device, which may also include interface devices and other processing devices. The computing device interacts with other processing devices to jointly complete computing operations specified by a user. The combined processing device may further comprise a storage device connected to the computing device and the other processing device, respectively, for storing data of the computing device and the other processing device. The processing unit provided by the scheme of the disclosure can effectively realize data synchronization among multiple cores through various synchronization instructions.

Description

Processing unit, synchronization method for a processing unit and corresponding product

Technical Field

The disclosure relates to the field of processors, and in particular, to a processing unit, a multi-core processor, a synchronization method for a processing unit/multi-core processor, a chip, and a board card.

Background

With the development of computer technology, various applications (such as video structure, advertisement recommendation, intelligent translation, etc.) have increasingly high requirements on the storage capacity and the computing capacity of a machine. Since single-core processors have not been able to meet the requirements of applications, a variety of multi-core processor systems have emerged. One key issue with multi-core processor systems is the cooperation between the cores. Therefore, how to realize the work cooperation among the cores based on the multi-core structure is an urgent problem to be solved.

Disclosure of Invention

To address one or more technical problems as mentioned above, the present disclosure provides, in various aspects, a processing unit, a multi-core processor, and a synchronization method for a processing unit/multi-core processor, wherein data synchronization between a plurality of cores in a multi-core processor architecture can be achieved by the provided synchronization method.

In a first aspect, the present disclosure provides a processing unit comprising at least one first core, wherein: the first core is configured to: querying, in response to a first synchronization instruction associated with a second core, whether there is an unprocessed synchronization event associated with the second core; and based on the result of the query, performing a corresponding synchronization operation.

In a second aspect, the present disclosure provides a processing unit comprising at least one second core, wherein: the second core is configured to: in response to a second synchronization instruction associated with a first core, sending a synchronization request signal to the first core to indicate a pending synchronization event; and acquiring the transmitted data to be synchronized in response to receiving a data transmission end signal from the first core.

In a third aspect, the present disclosure provides a multi-core processor comprising the processing unit of any of the foregoing first aspect embodiments and the processing unit of any of the foregoing second aspect embodiments.

In a fourth aspect, the present disclosure provides a chip, in which the processing unit according to any one of the embodiments of the first aspect, the processing unit according to any one of the embodiments of the second aspect, or the multi-core processor according to any one of the embodiments of the third aspect is packaged.

In a fifth aspect, the present disclosure provides a board card comprising the chip of any of the embodiments of the fourth aspect.

In a sixth aspect, the present disclosure provides a synchronization method for a processing unit, the processing unit including at least one first core, the method comprising: the first core, in response to a first synchronization instruction associated with a second core, querying whether there is an unprocessed synchronization event associated with the second core; and the first core executes corresponding synchronous operation based on the query result.

In a seventh aspect, the present disclosure provides a synchronization method for a processing unit comprising at least one second core, the method comprising: the second core transmitting a synchronization request signal to the first core to indicate a pending synchronization event in response to a second synchronization instruction associated with the first core; and the second core acquires the transmitted data to be synchronized in response to receiving a data transmission end signal from the first core.

In an eighth aspect, the present disclosure provides a synchronization method for a multi-core processor, wherein the multi-core processor includes a first processing unit and a second processing unit, the method comprising: the first processing unit performs the synchronization method according to any of the preceding sixth aspect embodiments; and the second processing unit performs the synchronization method according to any of the embodiments of the preceding seventh aspect.

By the processing unit, the multi-core processor, the synchronization method for the processing unit/the multi-core processor, the chip and the board card, the embodiment of the disclosure provides a scheme for data synchronization between two cores under the multi-core processor architecture, so that cooperative work among the cores in the multi-core processor architecture is ensured, flexible scheduling of tasks of the multi-core processor is facilitated, and processing efficiency is improved.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 shows an exemplary block diagram of a multi-core processor architecture to which embodiments of the disclosure may be applied;

FIG. 2 illustrates an exemplary internal architecture diagram of a processor core;

3A-3D illustrate schematic flow diagrams of synchronization methods according to embodiments of the present disclosure;

4A-4B illustrate schematic diagrams of data storage spaces according to embodiments of the present disclosure;

FIG. 5 shows a block diagram of a combined treatment device according to an embodiment of the disclosure; and

fig. 6 shows a schematic structural diagram of a board card according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. as may be used in the claims, the specification, and the drawings of the present disclosure, are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

FIG. 1 shows an exemplary block diagram of a multi-core processor architecture to which embodiments of the disclosure may be applied. Multicore processor 100 may be used to process input data such as computer vision, speech, natural language, data mining, and the like. Multicore processor 100 in fig. 1 is designed in a multi-Core hierarchical structure, and multicore processor 100 may be implemented as a system on a chip, which may include a plurality of clusters (clusters), each of which includes a plurality of cores (cores). In other words, multicore processor 100 is constructed at a system-on-chip-cluster-core hierarchy.

Looking at the system-on-chip hierarchy, as shown in FIG. 1, multicore processor 100 includes an external storage controller 111, a peripheral communication module 112, an on-chip interconnect module 113, and a plurality of clusters 115.

There may be multiple external memory controllers 111, 2 shown by way of example in the figure, for accessing an external memory device (e.g., DRAM) to read data from or write data to off-chip in response to an access request issued by the processor core. The peripheral communication module 112 is configured to receive a control signal from a processing device (not shown) through an interface device (not shown) and to start the multicore processor 100 to execute a task. The on-chip interconnect module 113 connects the external memory controller 111, the peripheral communication module 112, and the plurality of clusters 115 for transmitting data and control signals between the respective modules. The plurality of clusters 115 are computing cores of the multicore processor 100, 4 are exemplarily shown in the figure, and as hardware evolves, the multicore processor 100 of the present disclosure may further include 8, 16, 64, or even more clusters 115. The cluster 115 is used to efficiently execute deep learning algorithms.

Viewed at the cluster level, as shown in fig. 1, each cluster 115 includes a plurality of processor cores (IPU cores) 121 and a memory core (MEM core) 122.

The processor cores 121 are exemplarily shown in 4 in the figure, and the present disclosure does not limit the number of the processor cores 121.

The storage core 122 is mainly used for storing and communicating, i.e., storing shared data or intermediate results among the processor cores 121, and performing communication between the cluster 115 and the DRAM 127, communication among the clusters 115, communication among the processor cores 121, and the like. In other embodiments, memory core 122 has the capability of scalar operations to perform scalar operations.

The memory core 122 includes a shared memory unit (SMEM)124, a broadcast bus 123, a Cluster Direct Memory Access (CDMA) module 126, and a Global Direct Memory Access (GDMA) module 125. The SMEM 124 plays a role of a high-performance data transfer station, data multiplexed between different processor cores 121 in the same cluster 115 does not need to be respectively obtained to the DRAM 127 through the processor cores 121, but is transferred among the processor cores 121 through the SMEM 124, and the storage core 122 only needs to rapidly distribute the multiplexed data from the SMEM 124 to the plurality of processor cores 121, so that the inter-core communication efficiency is improved, and on-chip and off-chip input/output access is greatly reduced. The broadcast bus 123, CDMA 126, and GDMA 125 are used to perform communication among the processor cores 121, communication among the clusters 115, and data transmission between the clusters 115 and the DRAM 127, respectively. As will be described separately below.

The broadcast bus 123 is used to accomplish high-speed communication among the processor cores 121 in the cluster 115, and the broadcast bus 123 of this embodiment supports inter-core communication modes including unicast, multicast and broadcast. Unicast refers to point-to-point (i.e., from a single processor core to a single processor core) data transfer, multicast is a communication that transfers a copy of data from the SMEM 124 to a particular number of processor cores 121, and broadcast is a communication that transfers a copy of data from the SMEM 124 to all processor cores 121, and is a special case of multicast.

CDMA 126 is used to control access to SMEM 124 between different clusters 115 within the same multicore processor 100.

The GDMA 125 cooperates with the external memory controller 111 to control access of the SMEM 124 of the cluster 115 to the DRAM 127 or to read data from the DRAM 127 into the SMEM 124.

Although FIG. 1 illustrates a multi-core processor architecture with a single system-on-a-chip multi-core processor 100, those skilled in the art will appreciate that a multi-core processor may also be constructed with multiple single-core or multi-core processing units, and the disclosure is not limited in this respect.

Fig. 2 shows an exemplary internal architecture diagram of processor core 121. As shown in fig. 2, processor core 121 may include three major modules: a control module 21, an operation module 22 and a storage module 23.

The control module 21 is used for coordinating and controlling the operations of the operation module 22 and the storage module 23 to complete the task of deep learning, and includes an Instruction Fetch Unit (IFU) 211 and an Instruction Decode Unit (IDU) 212. The instruction fetch unit 211 is used for fetching an instruction from a processing device (not shown), and the instruction decode unit 212 decodes the fetched instruction and sends the decoded result to the operation module 22 and the storage module 23 as control information.

The operation module 22 includes a vector operation unit 221 and a matrix operation unit 222. The vector operation unit 221 is used for performing vector operations, and can support complex operations such as vector multiplication, addition, nonlinear transformation, and the like; the matrix operation unit 222 is responsible for core calculations of the deep learning algorithm, such as matrix multiplication and convolution.

The storage module 23 is used to store or transport related data, and includes a neuron storage unit (neuron RAM, NRAM)231, a weight storage unit (weight RAM, WRAM)232, an input/output direct memory access (IODMA) 233, and a transport direct memory access (MVDMA) 234. NRAM 231 is used to store input and output data and intermediate results for calculation by processor core 121; the WRAM 232 is used for storing the weight of the deep learning network; IODMA 233 controls access of NRAM 231/WRAM 232 and DRAM 127 through broadcast bus 123 (see FIG. 1); MVDMA 234 is used to control access to NRAM 231/WRAM 232 and SMEM 124.

In some embodiments, the functionality of the GDMA 125 (see fig. 1) and the functionality of the IODMA 233 (see fig. 2) may be integrated in the same component. For convenience of description, the GDMA 125 and the IODMA 233 are regarded as different components, and it is within the scope of the disclosure for those skilled in the art to achieve the same functions and achieve the same technical effects as the present disclosure. Further, the functions of the GDMA 125, the IODMA 233, the CDMA 126 and the MVDMA 234 can be realized by the same component, and the realized functions and achieved technical effects are similar to those of the present disclosure.

In a multi-core processor architecture, multiple processes may run simultaneously on multiple cores, and there may be some association between some processes. Multiple processes may need to synchronize data in order to accomplish the same task. Based on the foregoing multi-core processor architecture, data synchronization may include synchronization between storage cores among different clusters, as well as synchronization between a storage core and a processor core within the same cluster. The disclosed embodiments provide a synchronization mechanism for a multi-core processor architecture that can be applied to any of the synchronization scenarios described above.

FIG. 3A illustrates an example flow diagram of a method for synchronous interaction between two cores in a multi-core processor architecture in accordance with one embodiment of this disclosure. The multi-core processor architecture may be, for example, the example multi-core processor architecture described above with reference to fig. 1-2. As shown in fig. 3A, the synchronous interaction method involves at least two cores: a first core 310 and a second core 320, performing data synchronization between the first core 310 and the second core 320. The first core and the second core may be provided by different processing units, or may be provided by the same processing unit, and the disclosure is not limited herein. For convenience of description, it is not assumed that the first core 310 is a data generation side that generates data that needs to be synchronized; the second core 320 is a data acquisition end, which acquires data generated by the second core to achieve data synchronization.

Those skilled in the art will appreciate that the first core and the second core may represent different cores for different synchronization scenarios. For example, for inter-cluster synchronization of a multi-core processor, the first core and the second core may be storage cores of different clusters in the multi-core processor, respectively (see storage core 122 of fig. 1). For another example, for intra-cluster synchronization of a multi-core processor, the first core and the second core may be a processor core or a storage core, respectively, within the same cluster in the multi-core processor. In particular, the first core may be a processor core and the second core is a storage core; or conversely, the first core is a memory core and the second core is a processor core.

In the multi-core processing mode, each core maintains data under its own resources, and is not seen by other cores, nor is data of other cores seen. Therefore, before data to be synchronized is transmitted, synchronization is required, both ends of synchronization are guaranteed to be ready, and then data transmission can be performed. The generation end of the data needs to prepare the relevant data; the data acquisition end needs to prepare the corresponding storage space so as to store the related data. Thus, in embodiments of the present disclosure, two synchronization instructions are provided: a first synchronization instruction and a second synchronization instruction.

The first synchronization instruction is used for a core that is a data generation side in the multicore processor, for example, the first core 310 in this embodiment. The first synchronization instruction may be a Send (Send) instruction indicating that the sender of the data to be synchronized of the relevant synchronization event is ready, in other words, that the data to be synchronized has been generated at this time.

The first synchronization instruction may contain information related to the data to be synchronized to which the synchronization event relates, information related to the synchronization object, etc. The synchronization object may be, for example, a core in a multicore processor as a data acquisition end, such as the second core 320 in this embodiment. The information related to the synchronization object may include, for example, an identification of the core. In some embodiments, the information related to the synchronization object may further include a data receiving address of the synchronization object, that is, a predetermined address in the synchronization object for initially storing the data transmitted by the data generating end. The address may be a fixed address or a variable address, and the present disclosure is not limited in this respect. The address may also be preset so as not to be included in the first synchronization instruction.

The second synchronization instruction is used for a core in the multicore processor, which is a data acquisition end, such as the second core 320 in this embodiment. The second synchronization instruction may be a Receive (Receive) instruction indicating that the receiver of the data to be synchronized of the related synchronization event is ready, in other words, that the storage space for storing the data to be synchronized is ready at this time. The storage space corresponds to a data reception address or a predetermined address of the aforementioned synchronization object.

The second synchronization instruction may contain information related to the data to be synchronized to which the synchronization event relates, information related to the synchronization object, etc. The synchronization object may be, for example, a core that is a data generation end in a multi-core processor, such as the first core 310 in this embodiment. The information related to the synchronization object may include, for example, an identification of the core. Information related to the data to be synchronized may be used to determine a destination address at the data acquisition end for ultimately storing the data to be synchronized. In some embodiments, the data to be synchronized is tensor data and the second synchronization instruction comprises a descriptor of the tensor data. The specific contents of the descriptors regarding tensor data will be described later.

Referring to fig. 3A, an interaction flow for data synchronization between a first core 310 and a second core 320 is shown. The first core 310 and the second core 320 may each execute corresponding instructions, which may include a synchronization instruction, such as a first synchronization instruction or a second synchronization instruction, for indicating a data synchronization event between the cores.

In step S321, the second core may encounter a second synchronization instruction during instruction execution. As described earlier, the second synchronization instruction means that there is one data synchronization event, and the second core acts as a data acquisition or receiving end, which is ready for the synchronization event. That is, the second core is ready to store space to receive data. The second synchronization instruction may contain information related to the data to be synchronized to which the synchronization event relates, information related to the synchronization object, etc. In this example, the synchronization object is the first core 310.

Next, in step S322, the second core transmits a synchronization request signal to the first core as a synchronization target to indicate the pending synchronization event in response to the second synchronization instruction. The synchronization request signal does not need to carry data information to be synchronized, and only needs to indicate the state of ready reception to the first core.

The second core may then enter a wait state, waiting for a data transfer end signal from the first core.

The first core may execute respective instructions in parallel with the second core, and the instruction execution schedules may be different from each other. In fig. 3A, the first core 310 is shown to receive the synchronization request signal from the second core 320 before executing the first synchronization instruction associated with the second core.

As shown in fig. 3A, in step S311, in response to receiving a synchronization request signal from the second core, a relevant synchronization event is recorded. The record indicates that there is a pending data synchronization event associated with the second core.

In step S312, the first core may encounter a first synchronization instruction during instruction execution. As described previously, the first synchronization instruction means that there is one data synchronization event, and the first core is the producer or sender of the data for which it is ready. That is, the first core, having generated or prepared the data to be synchronized, may send to the second core. The first synchronization instruction may contain information related to the data to be synchronized to which the synchronization event relates, information related to the synchronization object, etc. In this example, the synchronization object is the second core 320.

Next, in step S313, the first core queries whether there is an unprocessed synchronization event associated with the second core in response to the first synchronization instruction. Corresponding synchronization operations may then be performed based on the results of the query.

In the embodiment shown in FIG. 3A, the situation is shown where the synchronization request signal of the second core has been received before the first synchronization instruction is executed. Thus, in this embodiment, the query at step S313 results in the presence of an unprocessed synchronization event. Then, the flow may advance to step S314.

At step S314, the data that needs to be synchronized is transferred to the second core 320. The transfer address of the data may be fixed or variable. This address may be, for example, indicated in the first synchronization instruction as described above, or may be preset and known to the second core, so that no additional indication is required in the first synchronization instruction.

At the end of the data transfer, at step S315, a data transfer end signal may be sent to the second core to indicate the end of the data transfer to the second core.

Then, at step S322, the second core acquires the transmitted data in response to receiving the data transmission end signal from the first core.

In some embodiments, the second core obtaining the transmitted data may include: determining a destination address of the data to be synchronized based on the second synchronization instruction; and reading the data transferred by the first core from the aforementioned transfer address (e.g., a fixed address known in advance) of the data and writing the determined destination address. The second core may cache the second synchronization instruction as it is executed for use in determining the destination address at this time.

Further, the synchronization method may further include the step S323 of the second core transmitting a response signal to the first core to indicate completion of the synchronization in response to receiving the data transfer end signal from the first core. The second core may then end the synchronization operation upon receiving the reply signal. The receipt of the acknowledgement signal can be regarded as the completion of data synchronization between the two, without waiting for the second core to write the data to the destination address in its entirety, whereby the execution of the instruction can be accelerated.

Alternatively or additionally, in some embodiments, when dependencies between processed data are maintained by some dependency data structure, the dependency data structure may be updated accordingly after synchronization is complete. In some implementations, the data structure may be represented as a data table, a data read/write counter, or the like, as the present disclosure is not limited in this respect.

Alternatively or additionally, in some embodiments, the second core, after acquiring the data, may compare the total amount of data received with the total amount of data expected to be received. If not, reporting an exception, and discarding the redundant data under the condition of redundant data.

The physical path that carries the data transfer between the first core and the second core is order-preserved, thereby ensuring that the data is correct. Various techniques in the art of communications transmission may be employed to ensure order-preserving transmission of physical paths, and the present disclosure is not limited in this respect.

The various signaling between the first core and the second core described above may be implemented in various ways. These signal transmissions include, for example, synchronization request signals, data transfer end signals, acknowledgement signals, etc. In some embodiments, the transmission of these signals may be accomplished in a semaphore manner.

FIG. 3B illustrates an example flow diagram of a synchronization method for a multicore processor according to another embodiment of the present disclosure. As mentioned previously, the first core may execute respective instructions in parallel with the second core, and the instruction execution schedules may be different from each other. Fig. 3B is substantially the same as fig. 3A, except that: fig. 3B shows that the first core 310 executes the first synchronization instruction associated with the second core before receiving the synchronization request signal sent by the second core 320, that is, the first core 310 executes the synchronization instruction before the second core 320.

As shown in FIG. 3B, in step S312, the first core executes to a first synchronization instruction during instruction execution. The first synchronization instruction indicates that the first core has generated or is ready to synchronize data, which may be sent to the second core. In this example, the synchronization object is the second core 320.

In the embodiment shown in FIG. 3B, the situation is shown where the synchronization request signal of the second core has not been received before the first synchronization instruction is executed. Thus, in this embodiment, the result of the query at step S313 is that there are no unprocessed synchronization events. The flow may then wait for a synchronization request signal from the second core.

During the wait of the first core, the second core may execute to a second synchronization instruction. As shown in fig. 3B, in step S321, the second core may encounter a second synchronization instruction during instruction execution. The second synchronization instruction indicates that the second core is ready to receive data.

At this time, the first core records the relevant synchronization event in response to receiving the synchronization request signal from the second core during the waiting process, as shown in step S311. The record indicates that there is a pending data synchronization event associated with the second core.

Then, the first core may determine that there is an unprocessed synchronous event based on the record in step S311 in the query of step S313. Therefore, the flow advances to step S314 to perform transmission of the synchronization data. The following data transmission process is the same as that in fig. 3A, and is not described herein again.

3A-3B illustrate the synchronization mechanism provided by embodiments of the present disclosure in an interactive manner. However, it will be appreciated by those skilled in the art that the disclosed embodiments provide a synchronization method for each core in the synchronization process accordingly.

FIG. 3C illustrates a synchronization method for a processing unit including at least a first core according to an embodiment of the disclosure.

As shown in fig. 3C, the method 300C includes a step S331 in which the first core queries whether there is an unprocessed synchronization event associated with the second core in response to a first synchronization instruction associated with the second core. In some implementations, the first synchronization instruction may be a Send (Send) instruction that indicates that the sender of the data to be synchronized for the relevant synchronization event is ready.

Next, in step S332, the first core performs a corresponding synchronization operation based on the result of the query.

Specifically, in one embodiment, based on the determination at step S3321, the method 300C may further include, when it is queried that there is an unprocessed synchronization event (yes branch at S3321), transmitting data requiring synchronization to the second core at step S3322. In some implementations, the first core may transfer data that needs to be synchronized to a predetermined address of the second core. The predetermined address is, for example, specified in the first synchronization instruction, or set in advance.

Next, it may be judged whether or not the data has been transferred to the end (step S3323); and transmitting a data transfer end signal to the second core when the data transfer is ended (step 3324).

In some implementations, the data transfer end signal may be signaled in a semaphore manner.

In another embodiment, based on the determination at step S3321, the method 300C may further include, when an unprocessed synchronization event is not queried (branch "no" at S3321), waiting for a synchronization event, i.e., waiting for a synchronization request signal from the second core, at step S3325.

During the waiting period, when a synchronization request signal is received from the second core (branch yes of S3326), the synchronization event is recorded (step S3327). The method flow may then return to step S3321 to determine whether there is an unprocessed synchronization event.

Alternatively or additionally, in some embodiments, the method 300C may further include step S333, the first core ending the synchronization operation in response to receiving a reply signal from the second core indicating completion of the synchronization.

FIG. 3D illustrates a synchronization method for a processing unit including at least one second core in accordance with embodiments of the present disclosure.

As shown in fig. 3D, the method 300D includes a step S341 of sending a synchronization request signal to the first core to indicate a pending synchronization event in response to a second synchronization instruction associated with the first core; and step S342 of acquiring the transferred data to be synchronized in response to receiving the data transfer end signal from the first core. In some implementations, the second synchronization instruction is a Receive (Receive) instruction that indicates that a receiver of data to be synchronized for the relevant synchronization event is ready. In still other implementations, the synchronization request signal is transmitted in a semaphore manner.

In one embodiment, acquiring the transmitted data to be synchronized may be embodied as a number of substeps. For example, in step S3421, the destination address of the data to be synchronized is determined based on the second synchronization instruction. In step S3422, the transferred data to be synchronized is read from a predetermined address for receiving the data to be synchronized transferred from the first core. Finally, in step S3423, the read data to be synchronized is written to the destination address determined in step S3421.

In some implementations, the data to be synchronized is tensor data, and the second synchronization instruction includes descriptors of the tensor data. Therefore, the destination address of the tensor data may be determined based on the descriptor in the second synchronization instruction in step S3421. The descriptors may include at least shape information of tensor data.

Alternatively or additionally, in some embodiments, the method 300D may further include step S343, in which the second core transmits a reply signal to the first core to indicate completion of the synchronization in response to receiving the data transfer end signal from the first core.

For specific implementation of each step in fig. 3C and fig. 3D, reference may be made to the description in conjunction with fig. 3A and fig. 3B, which is not described herein again.

As can be seen from the method flowcharts in fig. 3A to fig. 3D, the embodiment of the present disclosure provides a synchronization mechanism in a Send-Receive (Receive) manner, data is actively sent from one core (source end) to another core (destination end), and data information related to synchronization in each core does not need to be transferred between the two cores. In addition, in the data transfer process, instructions exist in both the first core (source end) and the second core (destination end), and the first core (source end) and the second core (destination end) maintain order consistency in the cores, so that data synchronization can be realized between the two cores without influencing the execution order of the instructions. In some embodiments, when the data receiving channel of the destination receives the data, the source may consider that the transmission between the two is completed, and does not need to wait until the destination actually writes the data to the destination address, thereby accelerating instruction processing and improving the efficiency of the processor.

The synchronization mechanism applied to the multi-core processor of the embodiments of the present disclosure has been described above with reference to flowcharts. It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It is further noted that, although the steps in the flowcharts of fig. 3A and 3B are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 3A and 3B may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least some of the sub-steps or stages of other steps.

With the development of artificial intelligence technology, in tasks such as image processing and pattern recognition, the oriented operands tend to be data types of multidimensional vectors (i.e., tensor data) that are typically processed on the multi-core processor of embodiments of the present disclosure. Therefore, how to implement the tensor data synchronization among the cores of the multi-core processor is also an urgent problem to be solved in the current computing field.

In an embodiment of the present disclosure, when the data to be synchronized is tensor data, a descriptor may be included in an operand in the synchronization instruction, by which information related to the tensor data can be quickly acquired. For example, a descriptor of the tensor data may be included in the second synchronization instruction, and then the second core (destination) may determine the destination address of the tensor data based on the descriptor.

In particular, the descriptor may indicate at least shape information of the tensor data. Shape information of the tensor data can be used to determine the data address of the tensor data corresponding to the operand in the data storage space.

Various possible implementations of shape information of tensor data are described in detail below in conjunction with the figures.

Tensors may contain multiple forms of data composition. The tensors may be of different dimensions, e.g. a scalar may be regarded as a 0-dimensional tensor, a vector may be regarded as a 1-dimensional tensor, and a matrix may be a 2-or higher-than-2-dimensional tensor. The shape of the tensor includes information such as the dimensions of the tensor, the sizes of the dimensions of the tensor, and the like. For example, for a three-dimensional tensor:

x₃＝[[[1，2，3]，[4，5，6]]；[[7，8，9]，[10，11，12]]]

the shape or dimension of the tensor can be expressed as X₃That is, the tensor is expressed as a three-dimensional tensor by three parameters, and the size of the tensor in the first dimension is 2, the size of the tensor in the second dimension is 2, and the size of the tensor in the third dimension is 3. When storing tensor data in a memory, the shape of the tensor data cannot be determined according to the data address (or storage area) of the tensor data, and further, relevant information such as the interrelation among a plurality of tensor data cannot be determined, so that the access efficiency of the processor to the tensor data is highLow.

In one possible implementation, the shape of the N-dimensional tensor data may be indicated by a descriptor, N being a positive integer, e.g., N ═ 1, 2, or 3, or zero. The three-dimensional tensor in the above example can be represented by descriptor (2,2, 3). It should be noted that the present disclosure is not limited to the way the descriptors indicate the tensor shape.

In one possible implementation, the value of N may be determined according to the dimension (also referred to as the order) of the tensor data, or may be set according to the usage requirement of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor may be used to indicate the shape (e.g., offset, size, etc.) of the three-dimensional tensor data in three dimensional directions. It should be understood that the value of N can be set by those skilled in the art according to practical needs, and the disclosure does not limit this.

Although tensor data can be multidimensional, there is a correspondence between tensors and storage on memory because the layout of memory is always one-dimensional. Tensor data is typically allocated in contiguous memory space, i.e., the tensor data can be one-dimensionally expanded (e.g., line first) for storage on memory.

This relationship between the tensor and the underlying storage may be represented by an offset of a dimension (offset), a size of a dimension (size), a step size of a dimension (stride), and so on. The offset of a dimension refers to the offset in that dimension from a reference position. The size of a dimension refers to the size of the dimension, i.e., the number of elements in the dimension. The step size of a dimension refers to the interval between adjacent elements in the dimension, for example, the step size of the above three-dimensional tensor is (6,3,1), that is, the step size of the first dimension is 6, the step size of the second dimension is 3, and the step size of the third dimension is 1.

FIG. 4A shows a schematic diagram of a data storage space according to an embodiment of the present disclosure. As shown in fig. 4A, the data storage space 41 stores a two-dimensional data in a line-first manner, which can be represented by (X, Y) (wherein the X axis is horizontally to the right and the Y axis is vertically to the bottom). The size in the X-axis direction (the size of each row, or the total number of columns) is ori _ X (not shown), the size in the Y-axis direction (the total number of rows) is ori _ Y (not shown), and the starting address PA _ start (base address) of the data storage space 41 is the physical address of the first data block 42. The data block 43 is partial data in the data storage space 41, and its offset amount 45 in the X-axis direction is denoted as offset _ X, the offset amount 44 in the Y-axis direction is denoted as offset _ Y, the size in the X-axis direction is denoted as size _ X, and the size in the Y-axis direction is denoted as size _ Y.

In a possible implementation manner, when the data block 43 is defined by using a descriptor, the data reference point of the descriptor may use the first data block of the data storage space 41, and the reference address of the descriptor may be agreed as the starting address PA _ start of the data storage space 41. The content of the descriptor of the data block 43 may then be determined in combination with the size ori _ X of the data storage space 41 in the X axis, the size ori _ Y in the Y axis, and the offset amount offset _ Y of the data block 43 in the Y axis direction, the offset amount offset _ X in the X axis direction, the size _ X in the X axis direction, and the size _ Y in the Y axis direction.

In one possible implementation, the content of the descriptor can be represented using the following formula (1):

it should be understood that although the content of the descriptor is represented by a two-dimensional space in the above examples, a person skilled in the art can set the specific dimension of the content representation of the descriptor according to practical situations, and the disclosure does not limit this.

In one possible implementation manner, a reference address of the data reference point of the descriptor in the data storage space may be appointed, and based on the reference address, the content of the descriptor of the tensor data is determined according to the positions of at least two vertexes located at diagonal positions in the N dimensional directions relative to the data reference point.

For example, a reference address PA _ base of a data reference point of the descriptor in the data storage space may be agreed. For example, one data (for example, data with a position of (2, 2)) may be selected as a data reference point in the data storage space 41, and a physical address of the data in the data storage space may be used as a reference address PA _ base. The content of the descriptor of the data block 43 in fig. 4A can be determined from the positions of the two vertices of the diagonal position with respect to the data reference point. First, the positions of at least two vertices of the diagonal positions of the data block 43 relative to the data reference point are determined, for example, the positions of the diagonal position vertices relative to the data reference point in the top-left-to-bottom-right direction are used, wherein the relative position of the top-left vertex is (x _ min, y _ min), and the relative position of the bottom-right vertex is (x _ max, y _ max), and then the content of the descriptor of the data block 43 can be determined according to the reference address PA _ base, the relative position of the top-left vertex (x _ min, y _ min), and the relative position of the bottom-right vertex (x _ max, y _ max).

In one possible implementation, the content of the descriptor (with reference to PA _ base) can be represented using the following equation (2):

it should be understood that although the above examples use the vertex of two diagonal positions of the upper left corner and the lower right corner to determine the content of the descriptor, the skilled person can set the specific vertex of at least two vertices of the diagonal positions according to the actual needs, and the disclosure does not limit this.

In one possible implementation, the content of the descriptor of the tensor data can be determined according to the reference address of the data reference point of the descriptor in the data storage space and the mapping relation between the data description position and the data address of the tensor data indicated by the descriptor. For example, when tensor data indicated by the descriptor is three-dimensional space data, the mapping relationship between the data description position and the data address may be defined by using a function f (x, y, z).

In one possible implementation, the content of the descriptor can be represented using the following equation (3):

in one possible implementation, the descriptor is further used to indicate an address of the N-dimensional tensor data, wherein the content of the descriptor further includes at least one address parameter representing the address of the tensor data, for example, the content of the descriptor may be the following formula (4):

where PA is the address parameter. The address parameter may be a logical address or a physical address. When the descriptor is analyzed, the PA may be used as any one of a vertex, a middle point, or a preset point of the vector shape, and the corresponding data address may be obtained by combining the shape parameters in the X direction and the Y direction.

In one possible implementation, the address parameter of the tensor data comprises a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address comprises a start address of the data storage space.

In one possible implementation, the descriptor may further include at least one address parameter representing an address of the tensor data, for example, the content of the descriptor may be the following equation (5):

wherein PA _ start is a reference address parameter, which is not described again.

It should be understood that, the mapping relationship between the data description location and the data address can be set by those skilled in the art according to practical situations, and the disclosure does not limit this.

In a possible implementation manner, a default base address can be set in a task, the base address is used by descriptors in instructions in the task, and shape parameters based on the base address can be included in the descriptor contents. This base address may be determined by setting an environmental parameter for the task. The relevant description and usage of the base address can be found in the above embodiments. In this implementation, the contents of the descriptor can be mapped to the data address more quickly.

In one possible implementation, the reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the mode of setting a common reference address by using the environment parameters, each descriptor in the mode can describe data more flexibly and use a larger data address space.

In one possible implementation, the data address in the data storage space of the data corresponding to the operand of the processing instruction may be determined according to the content of the descriptor. The calculation of the data address is automatically completed by hardware, and the calculation methods of the data address are different when the content of the descriptor is represented in different ways. The present disclosure does not limit the specific calculation method of the data address.

For example, the content of the descriptor in the operand is expressed by formula (1), the amount of shift of the tensor data indicated by the descriptor in the data storage space is offset _ x and offset _ y, respectively, and the size is size _ x × size _ y, then the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is_(x，y)The following equation (6) may be used to determine:

PA1_(x，y)＝PA_start+(offset_y-1)*ori_x+offset_x (6)

the data start address PA1 determined according to the above equation (6)_(x，y)In combination with the offsets offset _ x and offset _ y and the sizes size _ x and size _ y of the storage area, the storage area of the tensor data indicated by the descriptor in the data storage space can be determined.

In a possible implementation manner, when the operand further includes a data description location for the descriptor, a data address of data corresponding to the operand in the data storage space may be determined according to the content of the descriptor and the data description location. In this way, a portion of the data (e.g., one or more data) in the tensor data indicated by the descriptor may be processed.

For example, the content of the descriptor in the operand is expressed by formula (2), the tensor data indicated by the descriptor is respectively offset in the data storage space by offset _ x and offset _ y, the size is size _ x × size _ y, and the data description position for the descriptor included in the operand is (x) x_q，y_q) Then, the data address PA2 of the tensor data indicated by the descriptor in the data storage space_(x，y)The following equation (7) may be used to determine:

PA2_(x，y)＝PA_start+(offset_y+y_q-1)*ori_x+(offset_x+x_q) (7)

in one possible implementation, the descriptor may indicate the data of the block. The data partitioning can effectively accelerate the operation speed and improve the processing efficiency in many applications. For example, in graphics processing, convolution operations often use data partitioning for fast arithmetic processing.

FIG. 4B shows a schematic diagram of data chunking in a data storage space, according to an embodiment of the disclosure. As shown in FIG. 4B, the data storage space 46 also stores two-dimensional data in a row-first manner, which may be represented by (X, Y) (where the X-axis is horizontally to the right and the Y-axis is vertically down). The dimension in the X-axis direction (the dimension of each row, or the total number of columns) is ori _ X (not shown), and the dimension in the Y-axis direction (the total number of rows) is ori _ Y (not shown). Unlike the tensor data of fig. 4A, the tensor data stored in fig. 4B includes a plurality of data blocks.

In this case, the descriptor requires more parameters to represent the data blocks. Taking the X axis (X dimension) as an example, the following parameters may be involved: ori _ x, x.tile.size (size in tile 47), x.tile.stride (step size in tile 48, i.e. the distance between the first point of the first tile and the first point of the second tile), x.tile.num (number of tiles, shown as 3 tiles in fig. 4B), x.stride (overall step size, i.e. the distance from the first point of the first row to the first point of the second row), etc. Other dimensions may similarly include corresponding parameters.

In one possible implementation, the descriptor may include an identification of the descriptor and/or the content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be its number; the content of the descriptor may include at least one shape parameter representing a shape of the tensor data. For example, the tensor data is 3-dimensional data, of three dimensions of the tensor data, in which shape parameters of two dimensions are fixed, the content of the descriptor thereof may include a shape parameter representing another dimension of the tensor data.

In one possible implementation, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, separate data storage spaces may be divided for tensor data, each of which has a one-to-one correspondence with descriptors at the start address of the data storage space. In this case, a circuit or module (e.g., an entity external to the disclosed computing device) responsible for parsing the computation instruction may determine the data address in the data storage space of the data corresponding to the operand from the descriptor.

In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor may be further used to indicate an address of the N-dimensional tensor data, wherein the content of the descriptor may further include at least one address parameter indicating the address of the tensor data. For example, the tensor data is 3-dimensional data, when the descriptor points to an address of the tensor data, the content of the descriptor may include one address parameter indicating the address of the tensor data, such as a starting physical address of the tensor data, or may include a plurality of address parameters of the address of the tensor data, such as a starting address of the tensor data + an address offset, or the tensor data is based on the address parameters of each dimension. The address parameters can be set by those skilled in the art according to practical needs, and the disclosure does not limit this.

In one possible implementation, the address parameter of the tensor data may include a reference address of a data reference point of the descriptor in a data storage space of the tensor data. Wherein the reference address may be different according to a variation of the data reference point. The present disclosure does not limit the selection of data reference points.

In one possible implementation, the base address may comprise a start address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the start address of the data storage space. When the data reference point of the descriptor is data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

In one possible implementation, the shape parameters of the tensor data include at least one of: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertexes at diagonal positions of the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of tensor data indicated by the descriptor and the data address. Where the data description position is a mapping position of a point or a region in the tensor data indicated by the descriptor, for example, when the tensor data is 3-dimensional data, the descriptor may represent a shape of the tensor data using a three-dimensional coordinate space (x, y, z), and the data description position of the tensor data may be a position of a point or a region in the tensor data mapped in the three-dimensional space, which is represented using the three-dimensional coordinate (x, y, z).

It should be understood that shape parameters representing tensor data can be selected by one skilled in the art based on practical considerations, which are not limited by the present disclosure. By using the descriptor in the data access process, the association between the data can be established, thereby reducing the complexity of data access and improving the instruction processing efficiency.

Fig. 5 is a block diagram illustrating a combined processing device 500 according to an embodiment of the present disclosure. As shown in fig. 5, the combined processing device 500 includes a computing processing device 502, an interface device 504, other processing devices 506, and a storage device 508. Depending on the application scenario, one or more computing devices 510 may be included in the computing processing device, which may be configured as a multi-core processor as shown in fig. 1, for implementing the operations described herein in conjunction with fig. 3A-3B thereon.

In various embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core, computing processing devices of the present disclosure may be considered to have a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure may interact with other processing devices through an interface device to collectively perform user-specified operations. Other Processing devices of the present disclosure may include one or more types of general and/or special purpose processors, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), and artificial intelligence processors, depending on the implementation. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, etc., and the number may be determined based on actual needs. As previously mentioned, the computing processing device of the present disclosure may be viewed as having a homogeneous multi-core structure only. However, when considered together, a computing processing device and other processing devices may be considered to form a heterogeneous multi-core structure.

In one or more embodiments, the other processing device can interface with external data and controls as a computational processing device of the present disclosure (which can be embodied as an artificial intelligence, e.g., a computing device associated with neural network operations), performing basic controls including, but not limited to, data handling, starting and/or stopping of the computing device, and the like. In further embodiments, other processing devices may also cooperate with the computing processing device to collectively perform computational tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing processing device may obtain input data from other processing devices via the interface device, and write the input data into a storage device (or memory) on the computing processing device. Further, the computing processing device may obtain the control instruction from the other processing device via the interface device, and write the control instruction into the control cache on the computing processing device slice. Alternatively or optionally, the interface device may also read data from the memory device of the computing processing device and transmit the data to the other processing device.

Additionally or alternatively, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage means is connected to the computing processing means and the further processing means, respectively. In one or more embodiments, the storage device may be used to hold data for the computing processing device and/or the other processing devices. For example, the data may be data that is not fully retained within internal or on-chip storage of a computing processing device or other processing device.

In some embodiments, the present disclosure also discloses a chip (e.g., chip 602 shown in fig. 6). In one implementation, the Chip is a System on Chip (SoC) and is integrated with one or more combinatorial processing devices as shown in fig. 5. The chip may be connected to other associated components through an external interface device, such as external interface device 606 shown in fig. 6. The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interfaces) and/or the like may be integrated on the chip. In some embodiments, the disclosure also discloses a chip packaging structure, which includes the chip. In some embodiments, the present disclosure also discloses a board card including the above chip packaging structure. The board will be described in detail below with reference to fig. 6.

Fig. 6 is a schematic diagram illustrating a structure of a board card 600 according to an embodiment of the disclosure. As shown in fig. 6, the board includes a memory device 604 for storing data, which includes one or more memory cells 610. The memory device may be coupled to and communicate data with control device 608 and chip 602 described above, for example, via a bus. Further, the board card further includes an external interface device 606 configured for data relay or transfer function between the chip (or the chip in the chip package structure) and an external device 612 (such as a server or a computer). For example, the data to be processed may be transferred to the chip by an external device through an external interface means. For another example, the calculation result of the chip may be transmitted back to an external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface or the like.

In one or more embodiments, the control device in the disclosed card may be configured to regulate the state of the chip. Therefore, in an application scenario, the control device may include a single chip Microcomputer (MCU) for controlling the operating state of the chip.

From the above description in conjunction with fig. 5 and 6, it will be understood by those skilled in the art that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above boards, one or more of the above chips and/or one or more of the above combination processing devices.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, a terminal of the internet of things, a mobile terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in which acts or modules are involved, which are not necessarily required to practice one or more aspects of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one skilled in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are divided based on the logic functions, and there may be other dividing manners in actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In view of this, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause 1. a processing unit comprising at least a first core, wherein:

the first core is configured to:

querying, in response to a first synchronization instruction associated with a second core, whether there is an unprocessed synchronization event associated with the second core; and

and executing corresponding synchronous operation based on the query result.

Clause 2. the processing unit of clause 1, wherein the first core is further configured to:

when the unprocessed synchronous event exists, transmitting the data needing to be synchronized to the second core; and

sending the data transfer end signal to the second core when the data transfer ends.

Clause 3. the processing unit of clause 2, wherein the first core is configured to semaphore-wise transmit the data transfer end signal.

Clause 4. the processing unit of any of clauses 1-3, wherein the first core is further configured to:

waiting for a synchronization request signal from the second core when the unprocessed synchronization event is not queried; and

recording the synchronization event in response to receiving the synchronization request signal from the second core.

Clause 5. the processing unit of any of clauses 1-4, wherein,

the first core is further configured to transfer data requiring synchronization to a predetermined address of the second core.

Clause 6. the processing unit of any of clauses 1-5, wherein,

the first core is further configured to: in response to receiving an acknowledgement signal from the second core indicating completion of synchronization, ending the synchronization operation.

Clause 7. the processing unit of any of clauses 1-6, wherein,

the first core and the second core are respectively storage cores of different clusters in a multi-core processor architecture; or

The first core and the second core are respectively a processor core or a storage core in the same cluster in a multi-core processor architecture.

Clause 8. the processing unit of any of clauses 1-7, wherein,

the first synchronization instruction is a Send (Send) instruction indicating that the sender of the data to be synchronized of the relevant synchronization event is ready.

Clause 9. a processing unit comprising at least one second core, wherein:

the second core is configured to:

in response to a second synchronization instruction associated with a first core, sending a synchronization request signal to the first core to indicate a pending synchronization event; and

acquiring the transmitted data to be synchronized in response to receiving a data transmission end signal from the first core.

Clause 10. the processing unit of clause 9, wherein the second core is further configured to:

determining a destination address of data to be synchronized based on the second synchronization instruction in response to the data transfer end signal;

reading the transferred data to be synchronized from a predetermined address for receiving the data to be synchronized transferred from the first core; and

and writing the read data to be synchronized into the destination address.

Clause 11 the processing unit according to any of clauses 9-10, wherein the data to be synchronized is tensor data, the second synchronization instruction comprises descriptors of the tensor data, and,

the second core is configured to determine the destination address based on the descriptor.

Clause 12. the processing unit of clause 11, wherein the descriptor includes at least shape information of the tensor data.

Clause 13. the processing unit of any of clauses 9-12, wherein the second core is further configured to:

in response to receiving a data transfer end signal from the first core, sending an acknowledgement signal to the first core to indicate synchronization completion.

Clause 14. the processing unit of any of clauses 9-13, wherein the second core is configured to semaphore-wise transmit the synchronization request signal.

Clause 15. the processing unit of any of clauses 9-14, wherein,

the second core and the first core are respectively storage cores of different clusters in a multi-core processor architecture; or

The second core and the first core are respectively a processor core or a storage core in the same cluster in a multi-core processor architecture.

Clause 16. the processing unit of any of clauses 9-15, wherein,

the second synchronization instruction is a Receive (Receive) instruction indicating that a receiver of data to be synchronized of the related synchronization event is ready.

Clause 17. a multicore processor, comprising the processing unit of any one of clauses 1 to 8 and the processing unit of any one of clauses 9 to 16.

Clause 18. a chip, wherein the chip has encapsulated therein the processing unit of any of clauses 1-8, or the processing unit of any of clauses 9-16, or the multicore processor of clause 17.

Clause 19. a card, wherein the card includes the chip of clause 18.

Clause 20. a synchronization method for a processing unit, the processing unit including at least a first core, the method comprising:

the first core, in response to a first synchronization instruction associated with a second core, querying whether there is an unprocessed synchronization event associated with the second core; and

and the first core executes corresponding synchronous operation based on the query result.

Clause 21. the synchronization method of clause 20, wherein the method further comprises:

Clause 22. the synchronization method of clause 21, wherein the data transfer end signal is signaled.

Clause 23. the synchronization method according to any of clauses 20-22, wherein the method further comprises:

Clause 24. the synchronization method according to any of clauses 20-23, wherein the method further comprises:

the first core transfers data to be synchronized to a predetermined address of the second core.

Clause 25. the synchronization method according to any of clauses 20-24, wherein the method further comprises:

the first core ends the synchronization operation in response to receiving an acknowledgement signal from the second core indicating completion of synchronization.

Clause 26. the synchronization method according to any of clauses 20-25, wherein,

Clause 27. the synchronization method according to any of clauses 20-26, wherein,

Clause 28. a synchronization method for a processing unit, the processing unit including at least one second core, the method comprising:

the second core transmitting a synchronization request signal to the first core to indicate a pending synchronization event in response to a second synchronization instruction associated with the first core; and

the second core acquires the transmitted data to be synchronized in response to receiving a data transmission end signal from the first core.

Clause 29. the synchronization method of clause 28, wherein the method further comprises:

the second core responds to the data transmission ending signal and determines a destination address of data to be synchronized based on the second synchronization instruction;

the second core reads the transferred data to be synchronized from a predetermined address for receiving the data to be synchronized transferred from the first core; and

and the second core writes the read data to be synchronized into the destination address.

Clause 30. the synchronization method according to any of clauses 28-29, wherein the data to be synchronized is tensor data, the second synchronization instruction comprises a descriptor of the tensor data, and,

the second core determining a destination address includes determining the destination address based on the descriptor.

Clause 31. the synchronization method according to clause 30, wherein the descriptor comprises at least shape information of the tensor data.

Clause 32. the synchronization method according to any of clauses 28-31, wherein the method further comprises:

the second core transmits an acknowledgement signal to the first core to indicate synchronization completion in response to receiving a data transfer end signal from the first core.

Clause 33. the synchronization method according to any of clauses 28-32, wherein the synchronization request signal is transmitted in a semaphore manner.

Clause 34. the synchronization method according to any of clauses 28-33, wherein,

Clause 35. the synchronization method according to any of clauses 28-34, wherein,

Clause 36. a synchronization method for a multi-core processor, wherein the multi-core processor includes a first processing unit and a second processing unit, the method comprising:

the first processing unit performing the synchronization method according to any of clauses 20-27; and

the second processing unit performs the synchronization method according to any of clauses 28-35.

Claims

1. A processing unit comprising at least a first core, wherein:

the first core is configured to:

and executing corresponding synchronous operation based on the query result.

2. The processing unit of claim 1, wherein the first core is further configured to:

3. The processing unit of claim 2, wherein the first core is configured to semaphorically transmit the data transfer end signal.

4. The processing unit of any of claims 1-3, wherein the first core is further configured to:

5. The processing unit of any of claims 1-4,

6. The processing unit of any of claims 1-5,

7. The processing unit of any of claims 1-6,

8. The processing unit of any of claims 1-7,

9. A processing unit comprising at least one second core, wherein:

the second core is configured to:

10. The processing unit of claim 9, wherein the second core is further configured to:

and writing the read data to be synchronized into the destination address.

11. The processing unit of any of claims 9-10, wherein the data to be synchronized is tensor data, the second synchronization instruction includes descriptors of the tensor data, and,

12. The processing unit of claim 11, wherein the descriptors include at least shape information of the tensor data.

13. The processing unit of any of claims 9-12, wherein the second core is further configured to:

14. The processing unit of any of claims 9-13, wherein the second core is configured to send the synchronization request signal in a semaphore manner.

15. The processing unit of any of claims 9-14,

16. The processing unit of any of claims 9-15,

17. A multi-core processor comprising a processing unit according to any of claims 1-8 and a processing unit according to any of claims 9-16.

18. A chip having encapsulated therein a processing unit according to any one of claims 1 to 8, or a processing unit according to any one of claims 9 to 16, or a multi-core processor according to claim 17.

19. A card comprising the chip of claim 18.

20. A synchronization method for a processing unit, the processing unit including at least a first core, the method comprising:

21. The synchronization method of claim 20, wherein the method further comprises:

22. The synchronization method of claim 21, wherein the data transfer end signal is signaled in a semaphore.

23. The synchronization method according to any one of claims 20-22, wherein the method further comprises:

24. The synchronization method according to any one of claims 20-23, wherein the method further comprises:

25. The synchronization method according to any one of claims 20-24, wherein the method further comprises:

26. The synchronization method according to any one of claims 20 to 25,

27. The synchronization method according to any one of claims 20 to 26,

28. A synchronization method for a processing unit, the processing unit including at least one second core, the method comprising:

29. The synchronization method of claim 28, wherein the method further comprises:

30. The synchronization method according to any of claims 28-29, wherein the data to be synchronized is tensor data, the second synchronization instruction comprises descriptors of the tensor data, and,

31. The synchronization method of claim 30, wherein the descriptors include at least shape information of the tensor data.

32. A synchronization method according to any one of claims 28-31, wherein the method further comprises:

33. A synchronization method as claimed in any one of claims 28 to 32, wherein the synchronization request signal is transmitted in a semaphore manner.

34. The synchronization method according to any one of claims 28 to 33,

35. The synchronization method according to any one of claims 28 to 34,

36. A synchronization method for a multi-core processor, wherein the multi-core processor includes a first processing unit and a second processing unit, the method comprising:

the first processing unit performing the synchronization method according to any of claims 20-27; and

the second processing unit performs the synchronization method according to any of claims 28-35.