CN114281531B - Method, system, storage medium and equipment for distributing CPU cores - Google Patents
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Abstract
The application provides a method, a system, a storage medium and equipment for distributing CPU cores, wherein the method comprises the following steps: the CPU utilization rate and the performance data value of the system are sent to a core expansion management module in real time; confirming a current service scene through a core expansion management module, calculating a first variation of the CPU utilization rate and a second variation of a corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and calculating the ratio of the first variation to the second variation to obtain a current ratio; and obtaining the deviation degree based on the preset standard proportion and the current proportion, and determining the number of CPU cores of the key application based on the deviation degree and the current service scene so as to allocate the number of CPU cores for the key application. The application avoids the situation that the increasing amplitude of the CPU utilization rate is seriously deviated from the increasing amplitude of the performance, so that the CPU utilization rate is increased higher after the number of CPU cores is increased, and the situation that the system performance is not obviously increased is avoided.
Description
Technical Field
The present application relates to the field of server technologies, and in particular, to a method, a system, a storage medium, and an apparatus for distributing CPU cores.
Background
Currently, in order to improve the performance of the whole storage system, a policy of binding a plurality of CPU (central processing unit) cores is generally adopted. The application of the key service is bound on the appointed CPU core, so that the frequent loading of instructions and data in the cache can be reduced, and the condition of remote memory access can be effectively reduced.
However, the CPU utilization rate increase amplitude is obviously larger than the performance improvement amplitude under the unit IOPS easily appears on the CPU core binding, especially on the multi-CPU core binding, so that the system power consumption is seriously wasted, and the usability of the whole system is influenced.
Disclosure of Invention
In view of the above, the present application is directed to a method, a system, a storage medium and a device for allocating CPU cores, which are used for solving the problem that the increasing amplitude of CPU utilization rate and the increasing amplitude of performance are seriously deviated after a certain number of CPU cores are allocated for key applications in the prior art.
Based on the above object, the present application provides a method for allocating CPU cores, comprising the steps of:
the CPU utilization rate and the performance data value of the system are sent to a core expansion management module in real time;
confirming a current service scene through a core expansion management module, calculating a first variation of the CPU utilization rate and a second variation of a corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and calculating the ratio of the first variation to the second variation to obtain a current ratio;
and obtaining the deviation degree based on the preset standard proportion and the current proportion, and determining the number of CPU cores of the key application based on the deviation degree and the current service scene so as to allocate the number of CPU cores for the key application.
In some embodiments, calculating the first amount of change in CPU utilization and the corresponding second amount of change in performance data value for a preset period of time before the current time based on the CPU utilization and the performance data value received in real time includes:
in response to the kernel expansion management module receiving a first CPU utilization rate and a corresponding first performance data value at a time previous to a current time interval by a preset time period and receiving a second CPU utilization rate and a corresponding second performance data value at the current time, calculating a difference between the second CPU utilization rate and the first CPU utilization rate to obtain a first variation, and calculating a difference between the second performance data value and the first performance data value to obtain a second variation.
In some embodiments, deriving the degree of deviation based on the preset standard scale and the current scale comprises:
and obtaining the deviation degree based on the ratio of the preset standard proportion to the current proportion.
In some embodiments, validating the current traffic scenario by the core expansion management module comprises:
and acquiring information about the service scene through the core expansion management module, and confirming that the current service scene is a performance sensitive scene or a power consumption sensitive scene based on the information.
In some embodiments, the method further comprises:
responding to the current service scene as a performance sensitive scene, wherein the deviation degree does not exceed a preset value, and setting the performance parameters of a power supply module and a heat dissipation module in the system as corresponding performance full-load parameters respectively; or alternatively
And respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding preset performance overload parameters in response to the current service scene being a performance sensitive scene and the deviation exceeding a preset value.
In some embodiments, the method further comprises:
and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding performance full-load parameters in response to the current service scene being a power consumption sensitive scene.
In some embodiments, the performance data value comprises IOPS.
In another aspect of the present application, there is also provided a system for allocating CPU cores, including:
the sending module is configured to send the CPU utilization rate and the performance data value of the system to the core expansion management module in real time;
the computing module is configured to confirm the current service scene through the core expansion management module, compute a first variable quantity of the CPU utilization rate and a second variable quantity of the corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and compute the ratio of the first variable quantity to the second variable quantity to obtain the current proportion; and
the CPU core distribution module is configured to obtain the deviation degree based on a preset standard proportion and a current proportion, and determine the number of CPU cores of the key application based on the deviation degree and the current service scene so as to distribute the number of CPU cores for the key application.
In yet another aspect of the present application, there is also provided a computer readable storage medium storing computer program instructions which, when executed by a processor, implement the above-described method.
In yet another aspect of the present application, there is also provided a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, performs the above method.
The application has at least the following beneficial technical effects:
according to the application, the core expansion strategy of the whole system is controlled by the core expansion management module, different core expansion strategy adjustment is carried out under different scenes, the situation that the increasing amplitude of the CPU utilization rate deviates seriously from the increasing amplitude of the performance is avoided to the greatest extent, so that the CPU utilization rate is increased higher after the number of CPU cores is increased, and the situation that the system performance is not increased obviously is avoided; and the power consumption waste of the system is reduced; thereby improving the usability of the whole system.
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In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a method for allocating CPU cores according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a method for implementing CPU core allocation according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a system for distributing CPU cores provided in accordance with an embodiment of the present application;
FIG. 4 is a schematic diagram of a computer-readable storage medium embodying a method of allocating CPU cores according to an embodiment of the present application;
fig. 5 is a schematic hardware structure of a computer device for executing a method for allocating CPU cores according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the following embodiments of the present application will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present application, all the expressions "first" and "second" are used to distinguish two non-identical entities with the same name or non-identical parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present application. Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, article, or other step or unit that comprises a list of steps or units.
In view of the above object, a first aspect of the embodiments of the present application proposes an embodiment of a method of allocating CPU cores. FIG. 1 is a schematic diagram illustrating an embodiment of a method for allocating CPU cores provided by the present application. As shown in fig. 1, the embodiment of the present application includes the following steps:
step S10, the CPU utilization rate and the performance data value of the system are sent to a core expansion management module in real time;
step S20, confirming a current service scene through a core expansion management module, calculating a first variable quantity of the CPU utilization rate and a second variable quantity of a corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and calculating the ratio of the first variable quantity to the second variable quantity to obtain a current proportion;
and step S30, obtaining the deviation degree based on a preset standard proportion and a current proportion, and determining the number of CPU cores of the key application based on the deviation degree and the current service scene so as to allocate the number of CPU cores for the key application.
The CPU (central processing unit ) is used as the operation and control core of the computer system and is the final execution unit for information processing and program running.
The CPU core, namely the CPU core, is a core chip in the middle of the CPU, is made of monocrystalline silicon, is used for completing all calculation, receiving/storing commands, processing data and the like, and is a digital processing core. The CPU core is the most important component of the CPU. Various CPU cores have fixed logic structures, and logic units such as a first-level cache, a second-level cache, an execution unit, an instruction-level unit, a bus interface and the like have scientific layout.
According to the embodiment of the application, the core expansion management module is used for controlling the core expansion strategy of the whole system, different core expansion strategy adjustment is carried out under different scenes, the situation that the increasing amplitude of the CPU utilization rate deviates seriously from the increasing amplitude of the performance is avoided to the greatest extent, and the situation that the system performance does not increase obviously while the CPU utilization rate increases higher after the number of CPU cores is increased is avoided; and the power consumption waste of the system is reduced; thereby improving the usability of the whole system.
In some embodiments, calculating the first amount of change in CPU utilization and the corresponding second amount of change in performance data value for a preset period of time before the current time based on the CPU utilization and the performance data value received in real time includes: in response to the kernel expansion management module receiving a first CPU utilization rate and a corresponding first performance data value at a time previous to a current time interval by a preset time period and receiving a second CPU utilization rate and a corresponding second performance data value at the current time, calculating a difference between the second CPU utilization rate and the first CPU utilization rate to obtain a first variation, and calculating a difference between the second performance data value and the first performance data value to obtain a second variation.
In some embodiments, deriving the degree of deviation based on the preset standard scale and the current scale comprises: and obtaining the deviation degree based on the ratio of the preset standard proportion to the current proportion.
In some embodiments, validating the current traffic scenario by the core expansion management module comprises: and acquiring information about the service scene through the core expansion management module, and confirming that the current service scene is a performance sensitive scene or a power consumption sensitive scene based on the information.
In some embodiments, the method further comprises: responding to the current service scene as a performance sensitive scene, wherein the deviation degree does not exceed a preset value, and setting the performance parameters of a power supply module and a heat dissipation module in the system as corresponding performance full-load parameters respectively; or respectively setting the performance parameters of the power supply module and the heat dissipation module to corresponding preset performance overload parameters in response to the current service scene being a performance sensitive scene and the deviation exceeding a preset value.
In some embodiments, the method further comprises: and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding performance full-load parameters in response to the current service scene being a power consumption sensitive scene.
In some embodiments, the performance data value comprises IOPS.
IOPS (Input/Output Operations Per Second) is a measurement method for testing performance of a computer storage device (such as a hard disk (HDD), a Solid State Disk (SSD) or a Storage Area Network (SAN)), and can be regarded as the number of read/write operations per second.
Fig. 2 shows a schematic configuration diagram of a method of implementing allocation of CPU cores. As shown in fig. 2, the respective modules function as follows:
and the core expansion management module is used for: the module is positioned on the board card and mainly applied to programmable logic devices such as ARM and the like. The module judges the current service scene by acquiring instructions or preset information of the OS module and the serial port module. And acquiring the CPU utilization rate and the overall performance data under the current unit IOPS through a performance module, and fitting the deviation degree of the increase amplitude of the CPU utilization rate and the increase amplitude of the performance under the unit IOPS according to a preset CPU utilization rate-performance curve. For example: normally, the CPU utilization and the performance improvement amplitude are in positive correlation, and the proportion parameter K1 (i.e., a preset standard proportion) is maintained within a product definition range (k=the amplitude of increase in CPU utilization per unit IOPS/the performance improvement amplitude). And if the ratio parameter K2 (namely the current ratio) of the increase amplitude of the CPU utilization ratio and the increase amplitude of the performance under the unit IOPS fitted by the kernel expansion management module falls outside the product definition range, the deviation is shown, and the deviation=1- (K1/K2). In a performance sensitive scene, the deviation degree is not more than m%, the core expansion of key performance application can be continuously carried out, the upper limit of the core number is a% of the physical core number of the system, and at the moment, the power supply module and the heat dissipation module are both defaults to the performance full-load parameters. When the deviation exceeds m%, the core number is limited to b% of the physical core number of the system, and the power supply module and the heat dissipation module default to the performance overload parameters. In a power consumption sensitive scene, the deviation degree is not more than n% and the key application can be continuously performed, and the upper limit of the core number is c% of the physical core number of the system. When the deviation exceeds n%, the number of cores is defined as d% of the number of physical cores of the system. The power supply module and the fan module default to performance full parameters in a power consumption sensitive scene no matter what the deviation degree is. Wherein, each parameter can be preset through the serial port module and the OS module. The deviation of the increasing amplitude of the CPU utilization ratio and the increasing amplitude of the performance under the unit IOPS is strictly controlled by the core expansion management module, so that the large-scale deviation is prevented, the power consumption waste of the cluster is reduced, and the usability of the whole system is further improved.
An exemplary embodiment regarding the processing of CPU utilization and performance data values by the core expansion management module is as follows:
in a performance sensitive scene, the deviation degree is not more than 70%, the core expansion of key performance application can be continuously carried out, the upper limit of the core number is 80% of the physical core number of the system, and the power supply module and the fan module are default to be performance full-load parameters. When the deviation exceeds 70%, the core number is defined as 100% of the physical core number of the system, and the power supply module and the heat dissipation module default to the performance overload parameters. In a power consumption sensitive scene, the deviation degree is not more than 30%, the core expansion of key application can be continuously carried out, and the upper limit of the core number is 65% of the physical core number of the system. When the deviation exceeds 30%, the core number is defined as 75% of the physical core number of the system. Regardless of the degree of deviation, the power supply module and the heat dissipation module default to performance full-load parameters in a power consumption sensitive scene.
In this exemplary embodiment, the performance-sensitive scenario represents a scenario that is relatively sensitive to performance, i.e., high performance is sought, allowing high power consumption. When the number of CPU cores is larger, the power consumption of the system is larger, but the performance is also improved. While a power consumption sensitive scenario represents a scenario that is relatively sensitive to power consumption, i.e., low power consumption is pursued, so the number of CPU cores allowed to be extended is relatively small.
OS module: namely a complete machine system module, which can transmit the service scene instruction to the core expansion management module.
Performance module: the module is positioned on the board card, and can send CPU utilization rate and complete machine performance data under unit IOPS to the core expansion management module in real time.
And a power supply module: default is a performance full parameter, such as OCP (Over Current Protection, over-current protection) among others. Performance overload parameters are preset under which only fixed time services can be provided by default. The service time and the preset performance overload parameters are controlled by the core expansion management module and the serial port module.
And the heat radiation module comprises: the default is a performance full parameter, such as a maximum fan speed among others. Performance overload parameters are preset under which only fixed time services can be provided by default. The service time and the preset performance parameters are controlled by the core expansion management module and the serial port module.
An indication module: the module is positioned on the board and is directly controlled by the serial port module to externally indicate the real-time state of the current nuclear expansion management module.
And a wireless module: the serial port module signals can be converted into wireless signals such as WIFI and the like, and the outside can interact information with the nuclear expansion management module without using an entity serial port line.
Serial port module: the serial port module can be used for carrying out information interaction between the outside and the core expansion management module, parameter presetting and opening of related functions.
In a second aspect of the embodiment of the present application, a system for distributing CPU cores is also provided. FIG. 3 is a schematic diagram illustrating one embodiment of a system for distributing CPU cores provided by the present application. As shown in fig. 3, a system for allocating CPU cores includes: a transmitting module 10 configured to transmit the CPU utilization and the performance data value of the system to the core expansion management module in real time; the calculating module 20 is configured to confirm the current service scenario through the core expansion management module, calculate a first variation of the CPU utilization and a second variation of the corresponding performance data value in a preset time period before the current time based on the CPU utilization and the performance data value received in real time, and calculate a ratio of the first variation to the second variation to obtain a current ratio; and a CPU core allocation module 30 configured to obtain the deviation degree based on a preset standard proportion and a current proportion, and determine the number of CPU cores of the key application based on the deviation degree and the current service scene, so as to allocate the number of CPU cores for the key application.
In some embodiments, the calculation module 20 includes a variation calculation module configured to calculate a difference between the second CPU utilization and the first CPU utilization to obtain a first variation and calculate a difference between the second performance data value and the first performance data value to obtain a second variation in response to the kernel expansion management module receiving the first CPU utilization and the corresponding first performance data value at a time prior to a time interval of a preset time period and receiving the second CPU utilization and the corresponding second performance data value at the current time.
In some embodiments, the CPU core allocation module 30 includes a deviation module configured to derive a deviation based on a ratio of a preset standard ratio to a current ratio.
In some embodiments, the computing module 20 further includes a scenario confirmation module configured to obtain information about the traffic scenario through the kernel expansion management module, and confirm that the current traffic scenario is a performance sensitive scenario or a power consumption sensitive scenario based on the information.
In some embodiments, the system further includes a first parameter setting module configured to set performance parameters of the power supply module and the heat dissipation module in the system to corresponding performance full-load parameters, respectively, in response to the current service scenario being a performance sensitive scenario and the degree of deviation not exceeding a preset value; or respectively setting the performance parameters of the power supply module and the heat dissipation module to corresponding preset performance overload parameters in response to the current service scene being a performance sensitive scene and the deviation exceeding a preset value.
In some embodiments, the system further includes a second parameter setting module configured to set performance parameters of the power supply module and the heat dissipation module to corresponding performance loading parameters, respectively, in response to the current service scenario being a power consumption sensitive scenario.
In some embodiments, the performance data value comprises IOPS.
In a third aspect of the embodiment of the present application, there is further provided a computer readable storage medium, and fig. 4 is a schematic diagram of a computer readable storage medium for implementing a method for allocating CPU cores according to an embodiment of the present application. As shown in fig. 4, the computer-readable storage medium 3 stores computer program instructions 31. The computer program instructions 31 when executed by a processor implement the steps of:
the CPU utilization rate and the performance data value of the system are sent to a core expansion management module in real time;
confirming a current service scene through a core expansion management module, calculating a first variation of the CPU utilization rate and a second variation of a corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and calculating the ratio of the first variation to the second variation to obtain a current ratio;
and obtaining the deviation degree based on the preset standard proportion and the current proportion, and determining the number of CPU cores of the key application based on the deviation degree and the current service scene so as to allocate the number of CPU cores for the key application.
In some embodiments, calculating the first amount of change in CPU utilization and the corresponding second amount of change in performance data value for a preset period of time before the current time based on the CPU utilization and the performance data value received in real time includes:
in response to the kernel expansion management module receiving a first CPU utilization rate and a corresponding first performance data value at a time previous to a current time interval by a preset time period and receiving a second CPU utilization rate and a corresponding second performance data value at the current time, calculating a difference between the second CPU utilization rate and the first CPU utilization rate to obtain a first variation, and calculating a difference between the second performance data value and the first performance data value to obtain a second variation.
In some embodiments, deriving the degree of deviation based on the preset standard scale and the current scale comprises:
and obtaining the deviation degree based on the ratio of the preset standard proportion to the current proportion.
In some embodiments, validating the current traffic scenario by the core expansion management module comprises:
and acquiring information about the service scene through the core expansion management module, and confirming that the current service scene is a performance sensitive scene or a power consumption sensitive scene based on the information.
In some embodiments, the steps further comprise:
responding to the current service scene as a performance sensitive scene, wherein the deviation degree does not exceed a preset value, and setting the performance parameters of a power supply module and a heat dissipation module in the system as corresponding performance full-load parameters respectively; or alternatively
And respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding preset performance overload parameters in response to the current service scene being a performance sensitive scene and the deviation exceeding a preset value.
In some embodiments, the steps further comprise:
and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding performance full-load parameters in response to the current service scene being a power consumption sensitive scene.
In some embodiments, the performance data value comprises IOPS.
It should be understood that all of the embodiments, features and advantages set forth above with respect to the method of allocating CPU cores according to the application equally apply to the system and storage medium of allocating CPU cores according to the application, without conflicting therewith.
In a fourth aspect of the embodiment of the present application, there is also provided a computer device, including a memory 402 and a processor 401 as shown in fig. 5, where the memory 402 stores a computer program, and the computer program is executed by the processor 401 to implement the method of any one of the embodiments above.
As shown in fig. 5, a hardware configuration diagram of an embodiment of a computer device for performing a method for allocating CPU cores according to the present application is shown. Taking the example of a computer device as shown in fig. 5, a processor 401 and a memory 402 are included in the computer device, and may further include: an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 may be connected by a bus or otherwise, for example in fig. 5. The input device 403 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the system to which the CPU core is assigned. The output 404 may include a display device such as a display screen.
The memory 402 is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs, and modules, such as program instructions/modules corresponding to the method of allocating CPU cores in the embodiments of the present application. Memory 402 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created by the use of a method of allocating a CPU core, and the like. In addition, memory 402 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 401 executes various functional applications of the server and data processing, that is, implements the method of allocating CPU cores of the above-described method embodiment by running nonvolatile software programs, instructions, and modules stored in the memory 402.
Finally, it should be noted that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP and/or any other such configuration.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The foregoing embodiment of the present application has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the application, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the application, and many other variations of the different aspects of the embodiments of the application as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present application.
Claims (6)
1. A method of allocating CPU cores, comprising the steps of:
the CPU utilization rate and the performance data value of the system are sent to a core expansion management module in real time;
confirming a current service scene through the core expansion management module, calculating a first variation of the CPU utilization rate and a second variation of the corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and calculating the ratio of the first variation to the second variation to obtain a current ratio;
obtaining a deviation degree based on a preset standard proportion and the current proportion, and determining the number of CPU cores of a key application based on the deviation degree and the current service scene so as to allocate the number of CPU cores for the key application;
wherein obtaining the deviation degree based on the preset standard proportion and the current proportion comprises: obtaining a deviation degree based on the ratio of a preset standard proportion to the current proportion, wherein the deviation degree=1- (K1/K2), K1 is the preset standard proportion, and K2 is the current proportion;
the step of confirming the current service scene through the core expansion management module comprises the following steps: acquiring information about a service scene through the core expansion management module, and confirming that the current service scene is a performance sensitive scene or a power consumption sensitive scene based on the information;
responding to the current service scene as the performance sensitive scene, wherein the deviation degree does not exceed a preset value, and setting the performance parameters of a power supply module and a heat dissipation module in the system as corresponding performance full-load parameters respectively; or alternatively
Responding to the current service scene as the performance sensitive scene and the deviation degree exceeding the preset value, and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding preset performance overload parameters;
and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding performance full-load parameters in response to the current service scene being the power consumption sensitive scene.
2. The method of claim 1, wherein calculating a first amount of change in CPU utilization and a corresponding second amount of change in performance data value over a preset time period prior to a current time based on CPU utilization and performance data values received in real time comprises:
and responding to the first CPU utilization rate and the corresponding first performance data value of the moment before the moment which is separated from the current moment by a preset time period and the second CPU utilization rate and the corresponding second performance data value of the moment, calculating the difference value of the second CPU utilization rate and the first CPU utilization rate to obtain a first variation, and calculating the difference value of the second performance data value and the first performance data value to obtain a second variation.
3. The method of claim 1, wherein the performance data value comprises IOPS.
4. A system for allocating CPU cores, comprising:
the sending module is configured to send the CPU utilization rate and the performance data value of the system to the core expansion management module in real time;
the computing module is configured to confirm the current service scene through the core expansion management module, compute a first variation of the CPU utilization rate and a second variation of the corresponding performance data value in a preset time period before the current moment based on the CPU utilization rate and the performance data value received in real time, and compute the ratio of the first variation to the second variation to obtain the current ratio; and
the CPU core distribution module is configured to obtain a deviation degree based on a preset standard proportion and the current proportion, and determine the number of CPU cores of a key application based on the deviation degree and the current service scene so as to distribute the number of CPU cores for the key application;
wherein obtaining the deviation degree based on the preset standard proportion and the current proportion comprises: obtaining a deviation degree based on the ratio of a preset standard proportion to the current proportion, wherein the deviation degree=1- (K1/K2), K1 is the preset standard proportion, and K2 is the current proportion;
the step of confirming the current service scene through the core expansion management module comprises the following steps: acquiring information about a service scene through the core expansion management module, and confirming that the current service scene is a performance sensitive scene or a power consumption sensitive scene based on the information;
responding to the current service scene as the performance sensitive scene, wherein the deviation degree does not exceed a preset value, and setting the performance parameters of a power supply module and a heat dissipation module in the system as corresponding performance full-load parameters respectively; or alternatively
Responding to the current service scene as the performance sensitive scene and the deviation degree exceeding the preset value, and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding preset performance overload parameters;
and respectively setting the performance parameters of the power supply module and the heat dissipation module as corresponding performance full-load parameters in response to the current service scene being the power consumption sensitive scene.
5. A computer readable storage medium, characterized in that computer program instructions are stored, which, when executed by a processor, implement the method of any of claims 1-3.
6. A computer device comprising a memory and a processor, wherein the memory has stored therein a computer program which, when executed by the processor, performs the method of any of claims 1-3.
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| CN113448516A (en) * | 2021-06-04 | 2021-09-28 | 山东英信计算机技术有限公司 | Data processing method, system, medium and equipment based on RAID card |
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| CN105528330A (en) * | 2014-09-30 | 2016-04-27 | 杭州华为数字技术有限公司 | Load balancing method and device, cluster and many-core processor |
| CN111984407A (en) * | 2020-08-07 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Data block read-write performance optimization method, system, terminal and storage medium |
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