CN114281302A

CN114281302A - Random number generation device, method and related product

Info

Publication number: CN114281302A
Application number: CN202011035413.5A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2020-09-27
Filing date: 2020-09-27
Publication date: 2022-04-05

Abstract

The disclosure discloses a random number generation device, a calculation device, an integrated circuit chip, a board card, an electronic apparatus, and a method for generating a random number using the aforementioned random number generation device. Wherein the computing means may be comprised in a combined processing means which may further comprise interface means and other processing means. The computing device interacts with other processing devices to jointly complete computing operations specified by a user. The combined processing means may further comprise storage means connected to the device and the other processing means, respectively, for storing data of the device and the other processing means. The scheme disclosed by the invention can improve the generation efficiency of the random number and increase the data throughput of the random number.

Description

Random number generation device, method and related product

Technical Field

The present disclosure relates generally to the field of random numbers. More particularly, the present disclosure relates to a random number generation apparatus, a calculation apparatus, an integrated circuit chip, a board, an electronic device, and a method.

Background

Random numbers have a wide application base in many scenarios like statistical applications, experimental tests, etc. As the amount of statistical or test data increases, there is also a higher demand for the data amount and generation efficiency of random numbers. Because the generation algorithm of the random number has a large amount of data iterative operation, the related data amount is relatively large, and the hardware architecture for generating the random number has higher and higher requirements. In a conventional random number generation method, a random number is generally generated by a general-purpose processor such as a central processing unit ("CPU"). However, in order to ensure the versatility of such processors, the redundancy in the processors is relatively more designed, and the overhead caused thereby is relatively large, thereby resulting in relatively low efficiency of generating random numbers.

Disclosure of Invention

To solve the above-mentioned problems in the prior art, the present disclosure provides a hardware architecture having one or more pipelined arithmetic circuits supporting multiple stages of pipelined arithmetic. By utilizing the hardware architecture to execute computing instructions including generating random numbers, aspects of the present disclosure may achieve technical advantages in a number of aspects including enhancing processing performance of hardware, reducing power consumption, improving execution efficiency of computing operations, and avoiding computational overhead.

In a first aspect, the present disclosure provides a random number generation apparatus comprising:

at least one multi-stage pipelined arithmetic circuit comprising a plurality of arithmetic circuits arranged stage by stage and configured to perform a multi-stage pipelined arithmetic operation for generating a random number in accordance with a random number instruction, wherein the multi-stage pipelined arithmetic circuit comprises an update-stage arithmetic circuit and a generation-stage arithmetic circuit, and the random number instruction comprises an update instruction and/or a generation instruction,

wherein the update stage operational circuitry is configured to:

reading at least one state vector from a state space of a random number according to the update instruction;

obtaining an updated state vector by an update operation based on the at least one state vector; and

updating the state space with the updated state vector,

wherein the generation stage operational circuitry is configured to:

reading at least one state vector from the updated state space according to the generating instruction; and

performing a generating operation based on at least one state vector read from the updated state space to generate the random number.

In a second aspect, the present disclosure provides a computing device comprising: a control circuit configured to parse the received calculation instruction to obtain the random number instruction; and a random number generating device as described above and discussed in various embodiments below, configured to generate a random number according to the random number instruction.

In a third aspect, the present disclosure provides an integrated circuit chip comprising a random number generation device or a computing device as described above and in a number of embodiments below.

In a fourth aspect, the present disclosure provides a board card comprising an integrated circuit chip as described above and in the following embodiments.

In a fifth aspect, the present disclosure provides an electronic device comprising an integrated circuit chip as described above and in the following embodiments.

In a sixth aspect, the present disclosure provides a method of generating a random number using a random number generation apparatus comprising at least one multi-stage pipelined arithmetic circuit comprising a plurality of arithmetic circuits arranged stage by stage and configured to perform a multi-stage pipelined operation for generating a random number according to a random number instruction, wherein the multi-stage pipelined arithmetic circuit comprises an update stage arithmetic circuit and a generation stage arithmetic circuit, and the random number instruction comprises an update instruction and/or a generation instruction, the method comprising:

using the update stage arithmetic circuitry to read at least one state vector from a state space of a random number according to the update instruction and obtain an updated state vector by an update operation and update the state space with the updated state vector; and

performing a generating operation using the generating stage arithmetic circuitry to read at least one state vector from an updated state space in accordance with the generating instruction, so as to generate the random number.

By utilizing the disclosed random number generation device, computing device, integrated circuit chip, board card, electronic device and method, pipelined operations, particularly various multi-stage pipelined operations in the field of artificial intelligence, can be performed efficiently. Further, the disclosed scheme may enable efficient random number generation operations by means of a unique hardware architecture, thereby improving the overall performance of the hardware and reducing computational overhead.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts and in which:

FIG. 1 is a block diagram illustrating a random number generation apparatus according to one embodiment of the present disclosure;

FIG. 2 is a block diagram illustrating a random number generation apparatus according to another embodiment of the present disclosure;

FIG. 3 is a block diagram illustrating a random number generation apparatus according to yet another embodiment of the present disclosure;

FIG. 4 is a diagram illustrating indexing of state vectors within a state space according to an embodiment of the present disclosure;

FIG. 5 is a block diagram illustrating a computing device according to an embodiment of the present disclosure;

FIG. 6 is a simplified flow diagram illustrating a method of generating random numbers using a random number generation apparatus in accordance with an embodiment of the present disclosure;

FIG. 7 is a block diagram illustrating a combined treatment device according to an embodiment of the present disclosure; and

fig. 8 is a schematic diagram illustrating a structure of a board according to an embodiment of the disclosure.

Detailed Description

The disclosed solution provides a hardware architecture that supports multi-level pipelined arithmetic. When the hardware architecture is implemented in a random number generating device, the random number generating device at least comprises one or more multi-stage pipelined arithmetic circuits, wherein each multi-stage pipelined arithmetic circuit can form a disclosed multi-stage arithmetic pipeline. In the multistage operation pipeline, a plurality of operation circuits arranged stage by stage may be included. In one embodiment, when a plurality of random number instructions are received, each stage of arithmetic circuitry in the aforementioned multi-stage arithmetic pipeline may be configured to execute a corresponding one of the plurality of random number instructions. By means of the hardware architecture and random number instructions of the present disclosure, parallel random number generation operations may be performed efficiently, expanding the application scenarios of computations and reducing computational overhead.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

Fig. 1 is a block diagram illustrating a random number generation apparatus 100 according to one embodiment of the present disclosure. As shown in fig. 1, the random number generation apparatus 100 of the present disclosure includes at least one multi-stage pipelined arithmetic circuit (shown as 302 in fig. 3, described in detail later). The multi-stage pipelined arithmetic circuit may include an update stage arithmetic circuit 102 and a generate stage arithmetic circuit 104. In one or more application scenarios, one of the multi-stage pipelined arithmetic circuits may constitute a multi-stage arithmetic pipeline in the context of this disclosure. In view of this, the update stage operation circuit 102 and the generation stage operation circuit 104 can be regarded as two-stage operation circuits in one multi-stage pipeline. In each stage of the two-stage arithmetic circuit, one or more identical or different arithmetic circuits may be included. In one embodiment, the multi-stage operation pipeline may perform a multi-stage pipelined operation for generating random numbers in accordance with a random number instruction. The random number instruction may include an update instruction and/or a generate instruction. For example, in a multi-stage operation pipeline, the update stage operation circuit may perform a corresponding update operation according to the update instruction, and the generation stage operation circuit may perform a generation operation according to the generation instruction so as to generate the random number.

In one embodiment, the update stage arithmetic circuitry may be configured to read at least one state vector from a state space of a random number (which may be, for example, a cyclically utilized memory space) in accordance with the update instruction, and may obtain an updated state vector by an update operation based on the at least one state vector. Further, after obtaining the updated state vector, the state space may be updated with the updated state vector.

In one or more application scenarios, the update stage arithmetic circuitry may read a plurality of state vectors (e.g., a plurality of equal length vector data) from the state space in accordance with the update instruction and perform an update operation based on the plurality of state vectors to obtain an updated state vector. For example, according to the "Mersene twist for Graphic Processor Dynamic Creator," MTGPDC "random number generation algorithm, a L-length state vector R0 in the state space may be read. Next, two state vectors R1 and Rm of the same length as R0 in the state space can be read. Then, according to the update instruction, the corresponding update operation is performed using the three state vectors and the state parameters, thereby obtaining an updated state vector R0' having the same length as R0. Finally, the updated state vector R0' may be written back to the original address of R0 in the state space to update the state vector (or state space).

After performing the update operation, a random number generation operation may be performed in accordance with the generation instruction. In one embodiment, the generation stage arithmetic circuitry may read at least one state vector from the updated state space in accordance with a generation instruction, and may perform a generation operation in accordance with the at least one state vector read from the updated state space to generate the random number.

In one application scenario, the generation stage arithmetic circuitry may be configured to perform the random number generation operation to generate the random number in dependence on the updated state vector and a state vector read from the updated state space. Still taking the aforementioned "MTGPDC" random number generation algorithm as an example, the updated state vector R0 'obtained in the aforementioned update operation and another state vector R (m-1) having the same length L as R0' can be read from the state space. Operations associated with the generation operation may then be performed using the two state vectors to generate random numbers.

In one embodiment, the updating instructions and/or the generating instructions perform corresponding pipeline operations associated with the indexing of the plurality of state vectors in the state space. In one operational scenario, by using different state vectors in the state space, performing an update operation or a generation operation may obtain different updated state vectors or generate random numbers.

Further, the update-stage operation circuit and the generation-stage operation circuit may update different numbers of state vectors and/or generate different numbers of random numbers, respectively, according to different indexing manners of the plurality of state vectors in the state space. In one application scenario, the multi-stage arithmetic pipeline may selectively output random numbers for state vectors in a state space. For example, after the update stage operation circuits in the multistage operation pipeline perform the update operation, only some internal states (e.g., updated state vectors) may be output to the state space to update the state space, and at this time, the corresponding generation stage operation circuits may not perform the operation of generating the random numbers temporarily, i.e., may not generate the random numbers temporarily. Alternatively, the generation-stage operation circuit may re-execute the operation of generating the random number from a certain pre-selected state vector in the state space in accordance with the update operation of the update-stage operation circuit.

The hardware architecture of the update stage operation circuit or the generation stage operation circuit is realized through the multistage operation assembly line, and the update or generation operation can be executed through a plurality of same or different operators of each stage which are arranged stage by stage according to the update instruction or the generation instruction. The application of the hardware architecture can improve the overall performance of the random number generating device to a certain extent, reduce the calculation cost and reduce the power consumption.

Fig. 2 is a block diagram illustrating a random number generation apparatus 200 according to another embodiment of the present disclosure. As seen from fig. 2, the random number generation apparatus 200 includes not only the update stage operation circuit 102 and the generation stage operation circuit 104 of the random number generation apparatus 100 in fig. 1, but also further illustrates a plurality of other circuits. Since the functions of the update stage operation circuit and the generation stage operation circuit have been described in detail in conjunction with fig. 1, they will not be described in detail below.

As shown in fig. 2, the aforementioned multi-stage pipeline operation circuit of the present disclosure may further include an initialization stage operation circuit 202. According to some application scenarios of the present disclosure, an initialization operation may also be performed by the initialization-stage operational circuitry before the update-stage operational circuitry performs an update operation. In view of this, the aforementioned random number instructions may also include an initialization instruction. In one embodiment, the initialization stage operational circuitry may perform an initialization operation in accordance with the initialization instruction. In particular, the initialization stage operational circuitry obtains a random number seed from the initialization instruction and generates the state space comprising a plurality of state vectors based on the random number seed. In one application scenario, the initialization stage operational circuitry may perform a plurality of iterative operations (e.g., multiplication operations and/or logic operations, etc.) using the acquired random number seed to generate a plurality of state vectors to form a state space. Additionally or alternatively, the multi-stage pipelined arithmetic circuit may further comprise a cancellation circuit. Correspondingly, the random number instruction may further include an elimination instruction. After the initialization-stage operational circuit, the refresh-stage operational circuit and the generation-stage operational circuit complete random number generation operation, the elimination circuit can eliminate the influence generated after the multi-stage pipeline operational circuit executes related operations according to the elimination instruction. For example, the address pointer location of the state space of the entire random number generation operation is cleared to zero in order to perform the next operation according to the new random number instruction.

To implement the data storage operation, the random number generation apparatus 200 of the present disclosure may further include a memory 204, which may store a plurality of state vectors in the aforementioned state space, and after the random number instruction is executed, the state space is sorted for the execution of the next random number instruction. In one implementation scenario, the memory of the present disclosure may include a main storage module and/or a main cache module, wherein the main storage module may be configured to store a state vector and a state parameter for performing a multi-stage pipeline operation and a random number generated after performing a corresponding operation, and the main cache module may be configured to cache an intermediate operation result after performing an operation in the multi-stage pipeline operation. In addition, the memory may also have an interface for data transfer with an off-chip storage medium, so that data transfer between on-chip and off-chip systems may be achieved.

The architectural functions of the random number generation apparatus of the present disclosure including a multi-stage pipelined arithmetic circuit (i.e., a multi-stage arithmetic pipeline) are described above in conjunction with fig. 1 and 2. The architectural functions of the random number generating apparatus of the present disclosure, including one or more multi-stage pipelined arithmetic circuits, will be further described below in conjunction with fig. 3.

Fig. 3 is a block diagram illustrating a random number generation apparatus 300 according to yet another embodiment of the present disclosure. As shown in fig. 3, the random number generating apparatus 300 may include one or more multi-stage pipelined arithmetic circuits, such as the 1 st multi-stage pipelined arithmetic circuit 302, the 2 nd multi-stage pipelined arithmetic circuit 304, and the 3 rd multi-stage pipelined arithmetic circuit 306 shown in the figure, wherein each of the multi-stage pipelined arithmetic circuits may constitute one of the multi-stage arithmetic pipelines described in connection with fig. 1. Taking the 1 st multi-stage pipeline 302 constituting the 1 st multi-stage pipeline as an example, the 1 st multi-stage pipeline can perform pipeline operations including 1 st to 1 st stage pipeline operations, 1 st to 2 nd stage pipeline operations, and 1 st to 3 rd stage pipeline operations … …, which are N stages in total. Similarly, the 2 nd and 3 rd multi-stage pipelining circuits also have a structure that supports N-stage pipelining.

Assuming that the 1 st multistage operation pipeline is taken as an example, the initialization stage operation circuit may be regarded as a1 st-1 st stage pipeline operation, the update stage operation circuit may be regarded as a1 st-2 nd stage pipeline operation, and the generation stage operation circuit may be regarded as a1 st-3 rd stage pipeline operation. With such an exemplary architecture, those skilled in the art will appreciate that the multiple, multi-stage pipelined arithmetic circuits of the present disclosure may constitute multiple, multi-stage arithmetic pipelines, and that the multiple, multi-stage arithmetic pipelines may execute respective multiple random number instructions in parallel. By performing the updating or generating operation to generate the random number through the hardware architecture of the plurality of multistage operation pipelines, the operation of generating the random number can be performed in parallel by forming multiple state spaces, so that the generation efficiency of the random number can be improved and the data throughput can be increased.

To perform each stage of the pipelined operation described above, an arithmetic circuit including one or more operators may be arranged at each stage to execute a corresponding random number instruction to implement a corresponding operation at the stage. In one embodiment, in response to receiving a plurality of random number instructions, one or more multi-stage pipelined arithmetic circuits of the present disclosure may be configured to perform multiple data operations, such as executing single instruction multiple data ("SIMD") instructions. In another embodiment, the plurality of operations performed by the operation circuits of each stage are predetermined according to functions supported by the plurality of operation circuits arranged stage by stage in the multistage operation pipeline.

In the disclosed solution, each multi-stage pipeline arithmetic circuit, in addition to performing the step-by-step arithmetic operations in the one multi-stage arithmetic pipeline it constitutes, may be configured to selectively connect according to a plurality of random number instructions to complete a corresponding plurality of random number instructions. In one implementation scenario, the plurality of multi-stage operation pipelines of the present disclosure may include a first multi-stage operation pipeline and a second multi-stage operation pipeline, wherein an output of an operational circuit of one or more stages of the first multi-stage operation pipeline is configured to be connected to an input of an operational circuit of one or more stages of the second multi-stage operation pipeline according to the random number instruction. For example, the 1 st to 2 nd stage pipeline operations in the 1 st multistage operation pipeline shown in the figure may input their operation results into the 2 nd to 3 rd stage pipeline operations in the 2 nd multistage operation pipeline according to a random number instruction. Similarly, the 2 nd-1 st stage pipeline operations in the 2 nd multistage operation pipeline shown in the figure may input their operation results to the 3 rd-3 rd stage pipeline operations in the 3 rd multistage operation pipeline according to random number instructions. In some scenarios, depending on the random number instruction, two-stage pipelining in different pipelines may enable bidirectional transfer of operation results, e.g., between the 2 nd-2 nd pipelined operation in the 2 nd multi-stage operation pipeline and the 3 rd-2 nd pipelined operation in the 3 rd multi-stage operation pipeline as shown.

From the foregoing, it can be seen that in order to enable the transfer of data (e.g., state vectors and state parameters) between the same operation pipeline and different operation pipelines, each of the plurality of multi-stage operation pipelines of the present disclosure may have an input and an output for receiving input data at the operation circuit and outputting the result of the operation circuit. Within a multistage arithmetic pipeline, the output of the arithmetic circuitry of one or more stages is arranged to be connected to the input of the arithmetic circuitry of another stage or stages in accordance with a random number instruction to execute the random number instruction. For example, within the 1 st operation pipeline, the results of the 1 st-1 st stage pipeline operations may be input to the 1 st-3 rd stage pipeline operations within the operation pipeline according to a random number instruction.

In the context of the present disclosure, the aforementioned plurality of random number instructions may be microinstructions or control signals that are executed within one or more multi-stage operation pipelines, which may include (or indicate) one or more operation operations that are to be performed by the multi-stage operation pipelines. Depending on different operational scenarios, the operational operations may include, but are not limited to, arithmetic operations such as addition operations, multiplication operations, or modulo operations, logical operations such as and operations, xor operations, or operations, shift operations, or any combination of the foregoing types of operational operations.

In some application scenarios, as described above, the solution of the present disclosure may perform a bypass operation on one or more stages of the pipelined arithmetic circuit that will not be used in the arithmetic operation, i.e., one or more stages of the pipelined arithmetic circuit may be selectively used according to the needs of the arithmetic operation without having the arithmetic operation go through all of the pipelined operations. For example, the aforementioned multi-stage pipeline arithmetic circuit can selectively output some random numbers. Specifically, after the update stage operation circuit in the multi-stage operation pipeline circuit performs the update operation, only some internal states (e.g., updated state vectors) may be output into the state space to update the state space, and at this time, the corresponding generation stage operation circuit may not perform the operation of generating the random number temporarily. Accordingly, for unused pipelined arithmetic circuits, bypass may be made before or during pipelined arithmetic operations.

Further, the random number generating apparatus 300 further includes a memory 204 that may store a plurality of state vectors in a state space of the plurality of multistage pipelines and a plurality of multistage pipelines and intermediate operation results therebetween. The memory has a similar structure and function to the memory described in connection with fig. 2, and thus is not described in detail.

FIG. 4 is a diagram illustrating indexing of state vectors within a state space according to an embodiment of the disclosure. In order to better understand the process of generating random numbers for the random number generation apparatus, the process of the update stage and the generation stage arithmetic circuit of the present disclosure performing corresponding operations to generate random numbers will be described below by taking "MTGPDC" random number generation algorithm as an example. Further, it is assumed that the random number generation apparatus used in this example includes a three-stage operation pipeline, and the aforementioned initialization-stage operation circuit, update-stage operation circuit, and generation-stage operation circuit are the 1 st stage, 2 nd stage, and 3 rd stage pipeline operation circuits in the three-stage operation pipeline, respectively.

As shown in fig. 4, the initialization stage operational circuit may generate a state space X with a length N (or including N state vectors) according to a random number of seeds. For example, a plurality of state vectors X (i), X (i +1), and X (i + M) whose address pointers are i, i +1, and i + M.

After the initialization setting is executed, the corresponding update operation can be executed through the 2 nd-stage pipeline operation circuit (i.e., the update-stage operation circuit) according to the address pointer pre-selected in the update instruction. Based on the aforementioned "MTGPDC" random number generation algorithm, 3 state vectors X (i), X (i +1), and X (i + M) of length L1 can be read from the state space, respectively. Where i, i +1, i + M are the distance of the state vector to the first address of the state space X (i.e., the address pointer for each state vector). After the corresponding operation is executed by the stage of the pipelined arithmetic circuit, a state vector X (i + N) with the length of L1 can be generated. Assuming that the last address pointer in the state space plus 1 is N, then i and (i + N) are the same address bits. According to the update instruction, X (i + N) may be updated to the address of X (i) to update the state vector X (i) in the state space. The following description will be given by taking a section of source code to execute the aforementioned "MTGPDC" random number generation algorithm, and describing the operation process performed by the update-stage operation circuit to obtain the updated state vector X (i + N) by using 3 state vectors X (i), X (i +1), and X (i + M):

t＝X[i+1]^(x[i]|mask)；

t＝t^(t<<sh1)；

u＝t^(X[i+M]>>sh2)；

X[i+N]＝u^(R_table[u&0xF])。

further, after obtaining the updated state vector X (i + N), a state vector X [ i + (m-1) ] can be read from the state space X based on the aforementioned "MTGPDC" random number generation algorithm. And generating a random number by using the two state vectors X [ i + (m-1) ] and X (i + N) through a3 rd-stage running water operation circuit and performing correlation operation of generation operation according to a generation instruction. Where [ i + (m-1) ] represents the distance of the state vector to the head address of the state space X. The following takes the following source code as an example to execute the aforementioned "MTGPDC" random number generation algorithm, and describes the operation process performed by the generation-stage operation circuit to generate a random number by using the state vectors X [ i + (m-1) ] and X (i + N):

t＝X[i+(M-1)]^(X[i+(M-1)])；

t＝t^(t>>8)；

O[i]＝X[i+N]^T_table[t&0x4]。

the operation process of generating the random number is described above by taking the "MTGPDC" random number generation algorithm as an example, and performing the initialization operation, the update operation, and the generation operation according to different random number instructions through the three-stage pipeline operation circuit. In one embodiment, in the process of executing the multi-stage pipeline operation, the updating operation and/or the generating operation can be circularly executed from the first address of the state space according to the initialization instruction so as to update the N state vectors and generate the random number.

As previously mentioned, the solution of the present disclosure is to achieve its infinity by recycling a range of state spaces. I.e. a cyclic access to the state vector in state space X is possible. In one embodiment, the indexing may include performing a modulo operation on the updated state vector modulo the number N of all state vectors in the state space to establish an index for the state space. In some application scenarios, during the operation of the update operation or the generation operation, each state vector X (j) may be regarded as X [ (j)% N ],% represents the modulo operation. In addition, different state vectors in state space X can be updated cyclically by setting different indexing schemes (i.e., selecting different address pointers).

Taking the aforementioned "MTGPDC" random number generation algorithm as an example, the update stage arithmetic circuit or the generation stage arithmetic circuit of the present disclosure may select four state vectors X (i), X (i +1), X [ i + (M-1) ] and X (i + M) according to an update instruction or a generation instruction (implemented as, for example, one or more microinstructions), thereby performing a process of an update or generation operation. Since the aforementioned state space X supports cyclic access, the relative position relationship of the address pointers corresponding to the four state vectors will also change accordingly. Different state vector results are obtained when the address pointers of the four state vectors have different relative position relationships.

For purposes of simplicity and ease of discussion, the four state vectors X [ i ] above may be used]、X[i+1]、X[i+(M-1)]And X [ i + M]Abbreviated by the symbols "0, 1,MAnd M ", the four symbol values representing the distance of the four address pointers from the head address of the state space X. As mentioned above, the last address pointer of state space X +1 has an address pointer N. In the process of circularly updating the N state vectors and generating the random numbers by using the operation pipeline, the relative positions of the four address pointers in the state space X have the following four different relative position relationships from (1) to (4). In order to be able to successfully perform an update operation at different relative positional relationships (e.g. to prevent an updated state vector from overwriting a state vector to be subsequently used or from exceeding a state null)The length N of X) and the number of state vectors that can be read from state space X by the generating operation also have a corresponding variation:

(1) the relative position relationship of the four address pointers is 0<1<M<M, the number of state vectors that can be read by performing the update operation and the generate operation is: min (M0, N-M), i.e. min: (M-0, N-M) pseudo random numbers, min () representing the lesser of the two, where (MM-0) represents a position inMAnd 0, and N-M represents the number of state vectors located between the last address pointer N and the M address pointer of state space X;

(2) the relative position relationship of the four address pointers is M<0<1<MThe number of state vectors that can be read by performing the update operation and the generate operation is: (N-1) or (M-0), i.e. to form (N-1) or (M-0)M-0) pseudo random numbers, when (N-1) equals (A:)M-0), where (N-1) represents the number of state vectors located between the two address pointers of the last address pointer N and 1, and (b) ((d)M-0) represents a position inMAnd 0 number of state vectors between two address pointers;

(3) the relative position relationship of the four address pointers isM<M<0<At time 1, the number of state vectors that can be read by performing the update operation and the generate operation is min (N-1, 0-M) I.e., min (N-1, 0-M) A pseudo random number where (N-1) is equal to (0-M) Where (N-1) represents the number of state vectors between the two address pointers of the last address pointer N and 1, and (0-M) Indicates that is located at 0 andMthe number of state vectors between two address pointers;

(4) the relative position relationship of the four address pointers is 1<M<M<At 0, the number of state vectors that can be read by performing the update operation and the generate operation is 1, i.e., a pseudo-random number is generated.

When the relative position relationship is the above-mentioned (4) th position relationship, since the address pointer of "0" is located at the last address bit (i.e. one bit before the N bit) of the whole state space X, only one unit can be executedI.e. generating a pseudo-random number. After the corresponding operation in the position relationship is executed, the relative positions of the four address pointers are restored to the initial 0<1<M<The positional relationship of M, i.e., the (1) th relative positional relationship.

Fig. 5 is a block diagram illustrating a computing device 500 according to an embodiment of the present disclosure. As seen in fig. 5, the computing apparatus 500 includes not only the random number generating apparatus 300, but also further includes a control circuit 502. Since the structure and function of the random number generating apparatus are described in detail in the foregoing with reference to fig. 1 to 4, detailed description thereof will be omitted.

As shown in fig. 5, the control circuit may be configured to parse the received calculation instruction to obtain the random number instruction. According to aspects of the present disclosure, the compute instruction may be a form of hardware instruction and include one or more opcodes, and each opcode may represent one or more specific operations to be performed by the initialize, update, and generate stage operational circuits. The operations may include different types of operations according to application scenarios, and may include, for example, arithmetic operations such as addition operations or multiplication operations, logical operations such as and, xor, shift operations, or any of various combinations of the foregoing types of operation operations.

Accordingly, the random number instruction of the disclosed solution may be one or more microinstructions executed inside the random number generation apparatus, which is parsed from the calculation instruction. Specifically, one or more microinstructions corresponding to an opcode in a compute instruction, which may include an initialize instruction, an update instruction, or a generate instruction, may be included in a random number instruction, representing a plurality of operations performed by the multi-stage pipelined arithmetic circuitry, such as one or more of an initialize operation, an update operation, or a generate operation. In one embodiment, the random number generation apparatus may further obtain and parse the calculation instruction to obtain the plurality of operation instructions corresponding to the plurality of operations, where the operation instruction includes the random number instruction.

Fig. 6 is a simplified flow diagram illustrating a method 600 of generating random numbers using a random number generation apparatus in accordance with an embodiment of the present disclosure. From the foregoing description, it will be appreciated that the random number generation apparatus herein may be the random number generation apparatus described in conjunction with fig. 1-4, having the illustrated internal connections and supporting additional classes of operations.

As shown in fig. 6, at step 602, method 600 may use the update stage arithmetic circuitry to read at least one state vector from a state space of a random number according to the update instruction and obtain an updated state vector by an update operation, and update the state space with the updated state vector. In one embodiment, a plurality of state vectors may be read from the state space using the update stage arithmetic circuitry and an update operation may be performed based on the plurality of state vectors to obtain an updated state vector.

Next, at step 604, method 600 may perform a generation operation using the generation stage operational circuitry to read at least one state vector from the updated state space in accordance with the generation instruction in order to generate the random number. In one embodiment, the generation stage operational circuitry may be utilized to perform the generation operation based on the updated state vector and a state vector read from the updated state space to generate the random number.

In one embodiment, the random number instruction further comprises an initialization instruction, and the multi-stage pipelined arithmetic circuit further comprises an initialization stage arithmetic circuit. The method 600 may utilize the initialization stage operational circuitry to obtain a random number seed from the initialization instruction and generate a state space comprising a plurality of state vectors based on the random number seed. Using the state vectors and parameters in the state space, the method 600 may perform the above-described

steps

602 and 604 sequentially to generate random numbers. Further, the random number generation apparatus also includes a memory, which the method 600 may utilize to store a plurality of state vectors in the state space. After the random number instruction is executed, method 600 may use memory to sort the state space for execution of the next random number instruction.

Fig. 7 is a block diagram illustrating a combined processing device 700 according to an embodiment of the present disclosure. As shown in fig. 7, the combined processing device 700 includes a computing processing device 702, an interface device 704, other processing devices 706, and a storage device 708. Depending on the application scenario, one or more computing devices 710 may be included in the computing processing device and may be configured to perform the operations described herein in conjunction with fig. 1-6.

In various embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or as part of a hardware structure of an artificial intelligence processor core, computing processing devices of the present disclosure may be considered to have a single core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure may interact with other processing devices through an interface device to collectively perform user-specified operations. Other Processing devices of the present disclosure may include one or more types of general and/or special purpose processors, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), and artificial intelligence processors, depending on the implementation. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, etc., and the number may be determined based on actual needs. As previously mentioned, the computing processing device of the present disclosure may be considered to have a single core structure or an isomorphic multi-core structure only. However, when considered together, a computing processing device and other processing devices may be considered to form a heterogeneous multi-core structure.

In one or more embodiments, the other processing device can interface with external data and controls as the computing processing device of the present disclosure, performing basic controls including, but not limited to, data handling, starting and/or stopping of the computing device, and the like. In further embodiments, other processing devices may also cooperate with the computing processing device to collectively perform computational tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing processing device may obtain input data from other processing devices via the interface device, and write the input data into a storage device (or memory) on the computing processing device. Further, the computing processing device may obtain the control instruction from the other processing device via the interface device, and write the control instruction into the control cache on the computing processing device slice. Alternatively or optionally, the interface device may also read data from the memory device of the computing processing device and transmit the data to the other processing device.

Additionally or alternatively, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage means is connected to the computing processing means and the further processing means, respectively. In one or more embodiments, the storage device may be used to hold data for the computing processing device and/or the other processing devices. For example, the data may be data that is not fully retained within internal or on-chip storage of a computing processing device or other processing device.

In some embodiments, the present disclosure also discloses a chip (e.g., chip 802 shown in fig. 8). In one implementation, the Chip is a System on Chip (SoC) and is integrated with one or more combinatorial processing devices as shown in fig. 7. The chip may be connected to other associated components through an external interface device (such as external interface device 806 shown in fig. 8). The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interfaces) and/or the like may be integrated on the chip. In some embodiments, the disclosure also discloses a chip packaging structure, which includes the chip. In some embodiments, the present disclosure also discloses a board or an electronic device including the above chip packaging structure. The board will be described in detail below with reference to fig. 8.

Fig. 8 is a schematic diagram illustrating a structure of a board 800 according to an embodiment of the disclosure. As shown in FIG. 8, the board includes a memory device 804 for storing data, which includes one or more memory cells 810. The memory device may be connected and data transferred to the control device 808 and the chip 802 described above by means of, for example, a bus. Further, the board also includes an external interface device 806 configured for data relay or transfer function between the chip (or the chip in the chip package) and an external device 812 (such as a server or a computer). For example, the data to be processed may be transferred to the chip by an external device through an external interface means. For another example, the calculation result of the chip may be transmitted back to an external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface or the like.

In one or more embodiments, the control device in the disclosed card may be configured to regulate the state of the chip. Therefore, in an application scenario, the control device may include a single chip Microcomputer (MCU) for controlling the operating state of the chip.

From the above description in conjunction with fig. 7 and 8, it will be understood by those skilled in the art that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above boards, one or more of the above chips and/or one or more of the above combination processing devices.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, a terminal of the internet of things, a mobile terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in which acts or modules are involved, which are not necessarily required to practice one or more aspects of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one skilled in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are divided based on the logic functions, and there may be other dividing manners in actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In view of this, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause a1, a random number generating apparatus, comprising:

wherein the update stage operational circuitry is configured to:

updating the state space with the updated state vector,

wherein the generation stage operational circuitry is configured to:

Clause a2, the random number generation apparatus of clause a1, wherein the random number instruction further comprises an initialization instruction, the multi-stage pipelined arithmetic circuitry further comprises initialization stage arithmetic circuitry configured to obtain a random number seed according to the initialization instruction, and to generate the state space comprising a plurality of state vectors based on the random number seed.

Clause A3, the random number generating apparatus of clause a1, wherein the update stage arithmetic circuitry is configured to read a plurality of state vectors from the state space and perform an update operation based on the plurality of state vectors to obtain an updated state vector.

Clause a4, the random number generating device according to clause A3, wherein the generating stage arithmetic circuitry is configured to perform the generating operation according to the updated state vector and one state vector read from the updated state space to generate the random number.

Clause a5, the random number generating apparatus of clause A3, wherein the update instruction and/or generate instruction is associated with an indexing manner of a plurality of state vectors in the state space.

Clause a6, the random number generation apparatus according to clause a5, wherein the update-stage operation circuit and the generation-stage operation circuit respectively update different numbers of state vectors and generate different numbers of random numbers according to different ways of indexing the plurality of state vectors in the state space.

Clause a7, the random number generating apparatus of clause a6, wherein the indexing manner comprises modulo the number of all state vectors in the state space to establish an index for the state space.

Clause A8, the random number generating apparatus of any of clauses a1-a7, further comprising a memory configured to store a plurality of state vectors in the state space, and after execution of the random number instruction is completed, to marshal the state space for execution of a next random number instruction.

Clause a9, the random number generating apparatus according to clause A8, wherein when a plurality of multi-stage pipelined arithmetic circuits are included, the plurality of multi-stage pipelined arithmetic circuits execute respective random number instructions in parallel.

Clause a10, a computing device, comprising:

a control circuit configured to parse the received calculation instruction to obtain the random number instruction; and

the random number generating apparatus of any one of clauses a1-a9, configured to generate random numbers in accordance with the random number instruction.

Clause a11, the computing apparatus of clause a10, wherein the opcode of the computation instruction represents a plurality of operations performed by the multi-stage pipelined arithmetic circuit, the random number generation apparatus being further configured to obtain and parse the computation instruction to obtain the plurality of operation instructions corresponding to the plurality of operations, wherein the operation instruction comprises the random number instruction.

Clause a12, an integrated circuit chip comprising the random number generating device of any one of clauses a1-a9 or the computing device of clauses a10 or a 11.

Clause a13, a board comprising the integrated circuit chip of clause a 12.

Clause a14, an electronic device, comprising the integrated circuit chip of clause a 12.

Clause a15, a method of generating a random number using a random number generation apparatus including at least one multi-stage pipelined arithmetic circuit including a plurality of arithmetic circuits arranged stage by stage and configured to perform a multi-stage pipelined operation for generating a random number according to a random number instruction, wherein the multi-stage pipelined arithmetic circuit includes an update-stage arithmetic circuit and a generation-stage arithmetic circuit, and the random number instruction includes an update instruction and/or a generation instruction, the method comprising:

Clause a16, the method of clause a15, wherein the random number instruction further comprises an initialization instruction, the multi-stage pipelined arithmetic circuit further comprising an initialization stage arithmetic circuit, the method comprising:

the initialization stage operational circuitry is utilized to obtain a random number seed from the initialization instruction and generate a state space comprising a plurality of state vectors based on the random number seed.

Clause a17, the method of clause a15, wherein a plurality of state vectors are read from the state space with the update stage arithmetic circuitry, and an update operation is performed based on the plurality of state vectors to obtain an updated state vector.

Clause a18, the method of clause a17, wherein the generating operation is performed with the generating stage arithmetic circuitry to generate the random number according to the updated state vector and one state vector read from the updated state space.

Clause a19, the method of clause a17, wherein the update instruction and/or generate instruction is associated with an indexing manner of a plurality of state vectors in the state space.

Clause a20, the method of clause a19, wherein the update stage operational circuitry and the generate stage operational circuitry are utilized to update different numbers of state vectors and generate different numbers of random numbers, respectively, according to different ways of indexing the plurality of state vectors in the state space.

Clause a21, the method of clause a20, wherein the indexing manner comprises modulo the number of all state vectors in the state space to establish an index for the state space.

Clause a22, the method of any one of clauses a15-a21, wherein the random number generation apparatus further comprises a memory, the method comprising storing a plurality of state vectors in the state space with the memory, and after execution of the random number instruction is complete, the method reorganizes the state space with the memory for execution of a next random number instruction.

Clause a23, the method of clause a22, wherein when the random number generating apparatus comprises a plurality of multi-stage pipelined arithmetic circuits, the method executes respective random number instructions in parallel using the plurality of multi-stage pipelined arithmetic circuits.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that equivalents or alternatives within the scope of these claims be covered thereby.

Claims

1. A random number generation apparatus, comprising:

wherein the update stage operational circuitry is configured to:

updating the state space with the updated state vector,

wherein the generation stage operational circuitry is configured to:

2. The random number generating device of claim 1, wherein the random number instruction further comprises an initialization instruction, the multi-stage pipelined arithmetic circuit further comprising an initialization stage arithmetic circuit configured to obtain a random number seed from the initialization instruction and generate the state space comprising a plurality of state vectors based on the random number seed.

3. The random number generating device of claim 1, wherein the update stage operational circuitry is configured to read a plurality of state vectors from the state space and perform an update operation based on the plurality of state vectors to obtain an updated state vector.

4. The random number generating apparatus according to claim 3, wherein said generation stage operation circuit is configured to perform said generating operation based on said updated state vector and one state vector read from said updated state space to generate said random number.

5. The random number generating apparatus of claim 3, wherein the update instruction and/or generate instruction is associated with an indexing of a plurality of state vectors in the state space.

6. The random number generating apparatus according to claim 5, wherein said update-stage operation circuit and said generation-stage operation circuit respectively update a different number of state vectors and generate a different number of random numbers according to a difference in an index manner of a plurality of state vectors in said state space.

7. The random number generating device of claim 6, wherein the indexing manner comprises modulo the updated state vector by a number of all state vectors in the state space to establish an index for the state space.

8. The random number generation apparatus of any of claims 1-7, further comprising a memory configured to store a plurality of state vectors in the state space and, after execution of the random number instruction, to clean up the state space for execution of a next random number instruction.

9. The random number generating apparatus of claim 8, wherein when a plurality of multi-stage pipelined arithmetic circuits are included, the plurality of multi-stage pipelined arithmetic circuits execute respective random number instructions in parallel.

10. A computing device, comprising:

the random number generation apparatus of any of claims 1-9, configured to generate a random number according to the random number instruction.

11. The computing device of claim 10, wherein an opcode of the computation instruction represents a plurality of operations performed by the multi-stage pipelined arithmetic circuitry, the random number generation device further comprising control circuitry configured to fetch and parse the computation instruction to obtain the plurality of arithmetic instructions corresponding to the plurality of operations, wherein the arithmetic instruction comprises the random number instruction.

12. An integrated circuit chip comprising a random number generation apparatus according to any one of claims 1 to 9 or a computing apparatus according to claim 10 or 11.

13. A board card comprising the integrated circuit chip of claim 12.

14. An electronic device comprising the integrated circuit chip of claim 12.

15. A method of generating a random number using a random number generation apparatus comprising at least one multi-stage pipelined arithmetic circuit comprising a plurality of arithmetic circuits arranged stage by stage and configured to perform a multi-stage pipelined operation for generating a random number according to a random number instruction, wherein the multi-stage pipelined arithmetic circuit comprises an update-stage arithmetic circuit and a generation-stage arithmetic circuit, and the random number instruction comprises an update instruction and/or a generation instruction, the method comprising:

16. The method of claim 15, wherein the nonce instruction further comprises an initialization instruction, the multi-stage pipelined arithmetic circuit further comprises an initialization stage arithmetic circuit, the method comprising:

17. The method of claim 15, wherein a plurality of state vectors are read from the state space with the update stage arithmetic circuitry and an update operation is performed based on the plurality of state vectors to obtain an updated state vector.

18. The method of claim 17, wherein said generating operation is performed with said generation stage arithmetic circuitry to generate said random number according to said updated state vector and a state vector read from said updated state space.

19. The method of claim 17, wherein the update instruction and/or generate instruction is associated with an indexing of a plurality of state vectors in the state space.

20. The method of claim 19, wherein the update stage operational circuitry and the generate stage operational circuitry are utilized to respectively update different numbers of state vectors and generate different numbers of random numbers according to different ways of indexing a plurality of state vectors in the state space.

21. The method of claim 20, wherein the indexing manner comprises modulo the updated state vector by a number of all state vectors in the state space to establish an index for the state space.

22. A method according to any of claims 15 to 21, wherein the random number generating means further comprises a memory, the method comprising using the memory to store a plurality of state vectors in the state space, and after the random number instruction has completed execution, using the memory to collate the state space for execution of a next random number instruction.

23. The method of claim 22, wherein when the random number generating means comprises a plurality of multi-stage pipelined arithmetic circuits, the method executes respective random number instructions in parallel using the plurality of multi-stage pipelined arithmetic circuits.