CN111353124A - Operation method, operation device, computer equipment and storage medium - Google Patents

Abstract

The present disclosure relates to an arithmetic method, an apparatus, a computer device, and a storage medium. Wherein the combined processing device comprises: a machine learning arithmetic device, a universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with other processing devices to jointly complete the calculation operation designated by the user, wherein the combined processing device further comprises: and the storage device is respectively connected with the machine learning arithmetic device and the other processing devices and is used for storing the data of the machine learning arithmetic device and the other processing devices. The operation method, the operation device, the computer equipment and the storage medium provided by the embodiment of the disclosure have wide application range, high operation processing efficiency and high processing speed.

Description

Operation method, operation device, computer equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a vector instruction processing method and apparatus, a computer device, and a storage medium.

Background

With the continuous development of science and technology, machine learning, especially neural network algorithms, are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the types and the number of involved data operations are increasing. In the related art, the efficiency and speed of performing vector correlation operation on vector data are low.

Disclosure of Invention

In view of the above, the present disclosure provides a vector instruction processing method, apparatus, computer device and storage medium to improve efficiency and speed of performing vector correlation operations on vector data.

According to a first aspect of the present disclosure, there is provided a vector instruction processing apparatus, the apparatus comprising:

the control module is used for analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

the operation module is used for carrying out vector operation on the vector to be operated according to the vector operation type to obtain an operation result and storing the operation result into the target address;

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated on and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more vector instruction processing devices according to the first aspect, configured to obtain a vector to be executed and control information from another processing device, execute a specified machine learning operation, and transmit an execution result to the other processing device through an I/O interface;

when the machine learning arithmetic device comprises a plurality of vector instruction processing devices, the vector instruction processing devices can be connected through a specific structure and transmit data;

the vector instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of vector instruction processing devices share the same control system or own respective control systems; the vector instruction processing devices share a memory or own memories; the interconnection mode of the vector instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided a vector instruction processing method, which is applied to a vector instruction processing apparatus, the method including:

analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

performing vector operation on the vector to be operated according to the vector operation type to obtain an operation result, storing the operation result into the target address,

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated and a target address.

According to a ninth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above vector instruction processing method.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

The device comprises a control module and an operation module, wherein the control module is used for analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction; the operation module is used for carrying out vector operation on the vector to be operated according to the vector operation type to obtain an operation result, and storing the operation result into the target address. The vector instruction processing method, the vector instruction processing device, the computer equipment and the storage medium provided by the embodiment of the disclosure have wide application range, high processing efficiency and high processing speed for vector instructions, and high processing efficiency and high processing speed for vector operation.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 2 a-2 f show block diagrams of a vector instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram illustrating an application scenario of a vector instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 shows a flow diagram of a method of vector instruction processing according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "zero," "first," "second," and the like in the claims, the description, and the drawings of the present disclosure are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Due to the wide use of neural network algorithms, the computing man power of computer hardware is continuously improved, and the types and the number of data operations involved in practical application are continuously improved. Because the programming languages are various in types, in order to implement vector operation in different language environments, in the related art, because no instruction for performing vector operation, which can be widely applied to various programming languages, is available at the present stage, technicians need to customize one or more instructions corresponding to the programming language environments to implement vector operation, which results in low efficiency and low speed of performing vector operation. The present disclosure provides a vector instruction processing method, apparatus, computer device, and storage medium, which can implement vector operations with only one instruction, and can significantly improve the efficiency and speed of performing vector operations.

Fig. 1 shows a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a control module 11 and an operation module 12.

The control module 11 is configured to analyze the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtain a vector to be operated and a target address required for executing the vector instruction according to the operation code and the operation domain, and determine a vector operation type of the vector instruction. The operation code is used for indicating that the operation of the vector instruction on the data is vector operation, and the operation domain comprises a vector address to be operated and a target address.

And the operation module 12 is configured to perform vector operation on the vector to be operated according to the vector operation type to obtain an operation result, and store the operation result in the target address.

In this embodiment, the vector to be calculated may be one or more vectors. The vector operation type may indicate a kind or type of arithmetic operation, logical operation performed on the vector to be operated on. Such as vector addition operations, etc. The vector operation type can be set by those skilled in the art according to actual needs, and the present disclosure does not limit this.

In this embodiment, the control module may obtain the vectors to be calculated from the addresses of the vectors to be calculated, respectively. The control module may obtain instructions and data through a data input output unit, which may be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be a part of an instruction or a field (usually indicated by a code) specified in the computer program to perform an operation, and is an instruction sequence number used to inform a device executing the instruction which instruction needs to be executed specifically. The operation domain may be a source of all data required for executing the corresponding instruction, and all data required for executing the corresponding instruction includes parameters such as a vector to be operated on, a vector operation type, and the like, and a corresponding operation method, and the like. For a vector instruction it must comprise an opcode and an operation field, wherein the operation field comprises at least the vector address to be operated on and the target address.

It should be understood that the instruction format of the vector instructions and the contained opcodes and operation fields may be set as desired by those skilled in the art, and the present disclosure is not limited thereto.

In this embodiment, the apparatus may include one or more control modules and one or more operation modules, and the number of the control modules and the number of the operation modules may be set according to actual needs, which is not limited in this disclosure. When the device comprises a control module, the control module can receive vector instructions and control one or more operation modules to perform vector operation. When the device comprises a plurality of control modules, the plurality of control modules can respectively receive the vector instruction and control one or more corresponding operation modules to perform vector operation.

The vector instruction processing device provided by the embodiment of the disclosure comprises a control module and an operation module, wherein the control module is used for analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction; the operation module is used for carrying out vector operation on the vector to be operated according to the vector operation type to obtain an operation result, and storing the operation result into the target address. The vector instruction processing device provided by the embodiment of the disclosure has a wide application range, and is high in vector instruction processing efficiency and processing speed, and high in processing efficiency and processing speed of vector operation.

Figure 2a illustrates a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2a, the operation module 12 may include a plurality of vector operators 120. The plurality of vector operators 120 are for performing vector operations corresponding to vector operation types.

In this implementation, the vector operator may include an adder, a divider, a multiplier, a comparator, and the like capable of performing arithmetic operations, logical operations, and the like on the vector. The type and number of vector operators may be set according to the requirements of the size of the data amount of the vector operation to be performed, the type of vector operation, the processing speed and efficiency of the vector operation, and the like, which is not limited by the present disclosure.

Figure 2b illustrates a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2b, the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122. The main operation sub-module 121 may include a plurality of vector operators (not shown in the drawings). The main operation sub-module 121 is configured to perform a vector operation by using a plurality of vector operators to obtain an operation result, and store the operation result in a target address.

In one possible implementation, as shown in fig. 2b, the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122, and the slave operation sub-modules 122 may include a plurality of vector operators (not shown in the figure). The slave operation submodule 122 is configured to perform corresponding vector operations in parallel by using a plurality of included vector operators to obtain operation results, store the operation results in corresponding sub-cache spaces, and send the operation results to the master operation submodule 121. The main operation sub-module 121 is further configured to receive an operation result and store the operation result in a target address.

In this implementation, the control module may determine to execute the currently received vector instruction through the master operation submodule or the plurality of slave operation submodules according to the vector operation type, the task amount of the operation, and the like. For example, when it is determined that the vectors to be operated need to be summed, the main operation submodule may be controlled to operate. When the vector to be operated needs to be multiplied, a plurality of slave operation submodule can be controlled to operate.

In a possible implementation manner, the control module 11 is further configured to analyze the obtained calculation instruction to obtain an operation domain and an operation code of the calculation instruction, and obtain data to be operated, which is required for executing the calculation instruction, according to the operation domain and the operation code. The operation module 12 is further configured to perform an operation on the data to be operated according to the calculation instruction to obtain a calculation result of the calculation instruction. The operation module may include a plurality of operators for performing operations corresponding to operation types of the calculation instructions.

In this implementation, the calculation instruction may be other instructions for performing arithmetic operations, logical operations, and the like on data such as scalars, vectors, matrices, tensors, and the like, and those skilled in the art may set the calculation instruction according to actual needs, which is not limited by the present disclosure.

In this implementation, the arithmetic unit may include an adder, a divider, a multiplier, a comparator, and the like, which are capable of performing arithmetic operations, logical operations, and the like on data. The type and number of the arithmetic units may be set according to the requirements of the size of the data amount of the arithmetic operation to be performed, the type of the arithmetic operation, the processing speed and efficiency of the arithmetic operation on the data, and the like, which is not limited by the present disclosure.

In a possible implementation manner, the control module 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the data to be operated and the plurality of operation instructions to the main operation sub-module 121.

The master operation sub-module 121 is configured to perform preamble processing on data to be operated, and transmit data and operation instructions with the plurality of slave operation sub-modules 122.

The slave operation submodule 122 is configured to execute an intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation submodule 121 to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master operation submodule 122.

The main operation sub-module 121 is further configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction, and store the calculation result in the corresponding address.

In this implementation, when the computation instruction is an operation performed on scalar or vector data, the apparatus may control the main operation sub-module to perform an operation corresponding to the computation instruction by using an operator therein. When the calculation instruction is to perform an operation on data having a dimension greater than or equal to 2, such as a matrix, a tensor, or the like, the device may control the slave operation submodule to perform an operation corresponding to the calculation instruction by using an operator therein.

It should be noted that, a person skilled in the art may set the connection manner between the master operation submodule and the plurality of slave operation submodules according to actual needs to implement the configuration setting of the operation module, for example, the configuration of the operation module may be an "H" configuration, an array configuration, a tree configuration, and the like, which is not limited in the present disclosure.

Figure 2c illustrates a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2c, the operation module 12 may further include one or more branch operation sub-modules 123, and the branch operation sub-module 123 is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. The main operation sub-module 121 is connected to one or more branch operation sub-modules 123. Therefore, the main operation sub-module, the branch operation sub-module and the slave operation sub-module in the operation module are connected by adopting an H-shaped structure, and data and/or operation instructions are forwarded by the branch operation sub-module, so that the resource occupation of the main operation sub-module is saved, and the instruction processing speed is further improved.

Figure 2d shows a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in FIG. 2d, a plurality of slave operation sub-modules 122 are distributed in an array.

Each slave operation submodule 122 is connected to another adjacent slave operation submodule 122, the master operation submodule 121 is connected to k slave operation submodules 122 of the plurality of slave operation submodules 122, and the k slave operation submodules 122 are: n slave operator sub-modules 122 of row 1, n slave operator sub-modules 122 of row m, and m slave operator sub-modules 122 of column 1.

As shown in fig. 2d, the k slave operator modules include only the n slave operator modules in the 1 st row, the n slave operator modules in the m th row, and the m slave operator modules in the 1 st column, that is, the k slave operator modules are slave operator modules directly connected to the master operator module among the plurality of slave operator modules. The k slave operation submodules are used for forwarding data and instructions between the master operation submodules and the plurality of slave operation submodules. Therefore, the plurality of slave operation sub-modules are distributed in an array, the speed of sending data and/or operation instructions to the slave operation sub-modules by the master operation sub-module can be increased, and the instruction processing speed is further increased.

Figure 2e illustrates a block diagram of a vector instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2e, the operation module may further include a tree sub-module 124. The tree submodule 124 includes a root port 401 and a plurality of branch ports 402. The root port 401 is connected to the master operation submodule 121, and the plurality of branch ports 402 are connected to the plurality of slave operation submodules 122, respectively. The tree sub-module 124 has a transceiving function, and is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. Therefore, the operation modules are connected in a tree-shaped structure under the action of the tree-shaped sub-modules, and the speed of sending data and/or operation instructions from the main operation sub-module to the auxiliary operation sub-module can be increased by utilizing the forwarding function of the tree-shaped sub-modules, so that the instruction processing speed is increased.

In one possible implementation, the tree submodule 124 may be an optional result of the apparatus, which may include at least one level of nodes. The nodes are line structures with forwarding functions, and the nodes do not have operation functions. The lowest level node is connected to the slave operation sub-module to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. In particular, if the tree submodule has zero level nodes, the apparatus does not require the tree submodule.

In one possible implementation, the tree submodule 124 may include a plurality of nodes of an n-ary tree structure, and the plurality of nodes of the n-ary tree structure may have a plurality of layers.

For example, fig. 2f shows a block diagram of a vector instruction processing device according to an embodiment of the present disclosure. As shown in FIG. 2f, the n-ary tree structure may be a binary tree structure with tree-type sub-modules including 2 levels of nodes 01. The lowest level node 01 is connected with the slave operation sub-module 122 to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122.

In this implementation, the n-ary tree structure may also be a ternary tree structure or the like, where n is a positive integer greater than or equal to 2. The number of n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure may be set by those skilled in the art as needed, and the disclosure is not limited thereto.

In one possible implementation, the operation domain may also include a vector operation type.

The control module 11 may be further configured to determine a vector operation type according to the operation domain.

In one possible implementation, the vector operation type may include at least one of: vector multiplication operation, vector and scalar multiplication operation, vector addition operation, vector summation operation, specified value storage operation meeting operation conditions, bitwise AND operation, bitwise OR operation, bitwise XOR operation, bitwise negation operation, bitwise maximum value operation and bitwise minimum value operation. The operation condition may include any one of the following: bitwise equal, bitwise unequal, bitwise less, bitwise greater than or equal to, bitwise greater than, bitwise less than or equal to. The specified value may be a numerical value such as 0, 1, etc., and the present disclosure does not limit this.

The operation satisfying the bit-wise equal storage of the specified value can be: judging whether corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated are equal, and storing a specified value when the corresponding bits of the first vector to be operated and the second vector to be operated are equal; and when the corresponding bits are not equal, storing the value of the first vector to be operated or the second vector to be operated at the corresponding bits, or storing 0 and other numerical values different from the specified value.

Satisfying the bitwise inequality store specified value operation may be: judging whether corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated are equal, and storing a specified value when the corresponding bits of the first vector to be operated and the second vector to be operated are not equal; and storing the value of the first vector to be operated or the second vector to be operated at the corresponding bit when the corresponding bits are equal, or storing 0 and other numerical values different from the specified value.

Satisfying the bitwise less than store specified value operation may be: judging the magnitude relation of corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated, and storing a specified value when the value of the first vector to be operated on the corresponding bit is smaller than that of the second vector to be operated; and when the value of the first to-be-operated vector on the corresponding bit is larger than or equal to the value of the second to-be-operated vector, storing the value of the first to-be-operated vector or the second to-be-operated vector on the corresponding bit, or storing a value such as 0 which is different from the specified value.

Satisfying the bitwise greater than or equal to store the specified value operation may be: judging the magnitude relation of corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated, and storing a specified value when the value of the first vector to be operated on the corresponding bit is greater than or equal to the value of the second vector to be operated; and when the value of the first to-be-operated vector on the corresponding bit is smaller than that of the second to-be-operated vector, storing the value of the first to-be-operated vector or the second to-be-operated vector on the corresponding bit, or storing a value such as 0 which is different from the specified value.

Satisfying the bitwise greater than store specified value operation may be: judging the magnitude relation of corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated, and storing a specified value when the value of the first vector to be operated on the corresponding bit is larger than that of the second vector to be operated; and when the value of the first vector to be operated on the corresponding bit is less than or equal to the value of the second vector to be operated, storing the value of the first vector to be operated or the second vector to be operated on the corresponding bit, or storing 0 and other values different from the specified value.

Satisfying the bitwise less than or equal to store the specified value operation may be: judging the size relationship of corresponding bits of a first vector to be operated and a second vector to be operated in the vectors to be operated, and storing a specified value when the value of the first vector to be operated on the corresponding bit is less than or equal to the value of the second vector to be operated; and when the value of the first to-be-operated vector on the corresponding bit is larger than that of the second to-be-operated vector, storing the value of the first to-be-operated vector or the second to-be-operated vector on the corresponding bit, or storing a value such as 0 which is different from the specified value.

In this implementation, different operation domain codes may be set for different vector operation types to distinguish different operation types. For example, the code of "vector multiply operation" may be set to "mult". The code of the "vector and scalar multiplication operation" may be set to "mult. The code of the "vector addition operation" may be set to "add". The code of the "vector sum operation" may be set to "sub". The code for "bitwise AND operation" may be set to "and". The code for "bitwise OR" may be set to "or". The code for the "bitwise exclusive-or operation" may be set to "xor". The code for the bitwise negation operation may be set to "not". The code for "maximum bitwise operation" may be set to "max". The code for "minimum by bit operation" may be set to "min". The code "store a specified value 1 operation if bitwise equality is satisfied" may be set to "eq". The code "store a specified value 1 operation if bitwise inequality is satisfied" may be set to "ne". The code "satisfy bitwise less than store specified value 1 operation" may be set to "lt". Code that satisfies bitwise greater than or equal to store a specified value 1 operation may be set to "ge". The code "satisfy bitwise greater than store specified value 1 operation" may be set to "gt". The code "satisfy bitwise less than or equal to store a specified value 1 operation" may be set to "le".

The operation types and the corresponding codes thereof can be set by those skilled in the art according to actual needs, and the disclosure does not limit this.

In one possible implementation, the operation field may further include an input quantity. The control module 11 is further configured to determine an input quantity according to the operation domain, and obtain a to-be-operated vector with the data quantity as the input quantity from the to-be-operated data address.

In this implementation, the input quantity may be a parameter characterizing the amount of data of the vector to be computed, e.g., vector length, width, etc.

In one possible implementation, a default input amount may be set. When the input quantity cannot be determined according to the operation domain, the default input quantity can be determined as the input quantity of the current vector instruction, and the to-be-operated vector with the data quantity as the default input quantity is obtained from the to-be-operated data address.

In one possible implementation, as shown in fig. 2 a-2 f, the apparatus may further include a storage module 13. The storage module 13 is used for storing the vector to be calculated.

In this implementation, the storage module may include one or more of a cache and a register, and the cache may include a temporary cache and may further include at least one NRAM (Neuron Random Access Memory). And the cache is used for storing the data to be operated and the vector to be operated. And the register is used for storing scalar data in the data to be operated.

In one possible implementation, the cache may include a neuron cache. The neuron buffer, i.e., the neuron random access memory, may be configured to store neuron data in data to be operated on, where the neuron data may include neuron vector data.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112, and a queue storage sub-module 113.

The instruction storage submodule 111 is used to store vector instructions.

The instruction processing sub-module 112 is configured to parse the vector instruction to obtain an opcode and an operand of the vector instruction.

The queue storage submodule 113 is configured to store an instruction queue, where the instruction queue includes multiple instructions to be executed that are sequentially arranged according to an execution order, and the instructions to be executed may include vector instructions.

In this implementation, the instructions to be executed may also include computation instructions related or unrelated to vector operations, which are not limited by this disclosure. The execution sequence of the multiple instructions to be executed can be arranged according to the receiving time, the priority level and the like of the instructions to be executed to obtain an instruction queue, so that the multiple instructions to be executed can be sequentially executed according to the instruction queue.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may further include a dependency processing sub-module 114. The dependency relationship processing submodule 114 is configured to, when it is determined that a first to-be-executed instruction in the multiple to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, cache the first to-be-executed instruction in the instruction storage submodule 111, and after the zeroth to-be-executed instruction is executed, extract the first to-be-executed instruction from the instruction storage submodule 111 and send the first to-be-executed instruction to the operation module 12. The method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area. On the contrary, there is no association relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, which may be that there is no overlapping area between the first storage address interval and the zeroth storage address interval.

By the method, according to the dependency relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, the subsequent first to-be-executed instruction is executed after the execution of the previous zeroth to-be-executed instruction is finished, and the accuracy of the operation result is ensured.

In one possible implementation, the instruction format of the vector instruction may be:

opcode dst src type size

wherein opcode is the operation code of the vector instruction, dst, src, type, size are the operation fields of the vector instruction. Wherein dst is the target address. src is an address of a vector to be operated, and when there are a plurality of vectors to be operated, src may include a plurality of addresses src0, src1, …, and src n, which is not limited by this disclosure. type is a vector operation type. size is the input amount. The type can be a code of a vector operation type, such as mult, mult.const, add, sub, eq, ne, lt, ge, gt, le, eq, and, or, xor, not, max, min.

When the number of vectors to be operated is multiple, the instruction format may include multiple data addresses to be operated, and the following example includes two vectors to be operated, and the instruction format of the vector instruction may be:

opcode dst src0src1type size

in one possible implementation, the instruction format of the vector instruction may be:

type dst src size

in one possible implementation, the instruction format of the vector instruction for the "vector multiply operation" may be set to: multdst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and multiplying the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "vector-by-scalar multiplication operation" may be set to: const dst src0src1 size. It represents: and acquiring a size-sized vector to be operated from the first data address src0, acquiring a size-sized scalar to be operated from the second data address src1, and multiplying the vector to be operated and the scalar to be operated to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "vector add operation" may be set to: add dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing addition operation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "vector sum operation" may be set to: sub dst src size. It represents: and acquiring a plurality of vectors to be operated with the size from the address src to be operated, and performing summation operation on the plurality of vectors to be operated to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a "bitwise and operation" vector instruction may be set to: and dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing bitwise AND operation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a "bitwise OR" vector instruction may be set to: or dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing bitwise OR operation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "bitwise xor operation" may be set to: xor dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing bitwise exclusive-or operation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "bitwise negation" operation may be set to: not dst src size. It represents: and acquiring the size of the vector to be operated from the address src to be operated, and performing bitwise negation operation on the vector to be operated to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "maximum bit-wise operation" may be set to: max dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing bit-wise maximum value calculation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format of the vector instruction for the "minimum-by-bit operation" may be set to: min dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, and performing bit-based minimum value calculation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for the vector instruction "store a specified value 1 operation if bitwise equality is satisfied" may be set to: eq dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector according to bits, and storing a specified value 1 when corresponding bits of the first to-be-operated vector and the second to-be-operated vector are equal to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a vector instruction that stores a specified value 1 operation if bitwise inequality is satisfied may be set to: ne dst src0src1 size. It represents: the method comprises the steps of obtaining a first to-be-operated vector with the size from a first to-be-operated address src0, obtaining a second to-be-operated vector with the size from a second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector according to bits, and storing a specified value 1 when corresponding bits of the first to-be-operated vector and the second to-be-operated vector are not equal to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a vector instruction that satisfies the store specified value 1 operation if bitwise less than is set to: lt dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector in a bitwise manner, and storing a specified value 1 when the value of the first to-be-operated vector on the corresponding bit is smaller than that of the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a vector instruction that satisfies the store specified value 1 operation if bitwise is greater than or equal to may be set to: ge dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector according to bits, and storing a specified value 1 when the value of the first to-be-operated vector on the corresponding bit is greater than or equal to the value of the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a vector instruction that satisfies the store specified value 1 operation if bitwise greater may be set to: gt dst src0src1 size. It represents: the method comprises the steps of obtaining a first to-be-operated vector with the size from a first to-be-operated address src0, obtaining a second to-be-operated vector with the size from a second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector according to bits, and storing a specified value 1 when the value of the first to-be-operated vector on the corresponding bit is larger than that of the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

In one possible implementation, the instruction format for a vector instruction that satisfies the store specified value 1 operation if bitwise is less than or equal to may be set to: le dst src0src1 size. It represents: and acquiring a first to-be-operated vector with the size from the first to-be-operated address src0, acquiring a second to-be-operated vector with the size from the second to-be-operated address src1, comparing the first to-be-operated vector with the second to-be-operated vector in a bitwise manner, and storing a specified value 1 when the value of the first to-be-operated vector on the corresponding bit is less than or equal to the value of the second to-be-operated vector to obtain an operation result. And stores the operation result into the target address dst.

It should be understood that the location of the opcode, opcode and operand field in the instruction format of the vector instruction may be set as desired by those skilled in the art, and is not limited by the present disclosure.

In one possible implementation manner, the apparatus may be disposed in one or more of a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and an embedded Neural Network Processor (NPU).

It should be noted that, although the vector instruction processing apparatus has been described above by taking the above-described embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application example

An application example according to the embodiments of the present disclosure is given below in conjunction with "vector operation using a vector instruction processing apparatus" as one exemplary application scenario to facilitate understanding of the flow of the vector instruction processing apparatus. It is understood by those skilled in the art that the following application examples are merely for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be construed as limiting the embodiments of the present disclosure

Fig. 3 is a schematic diagram illustrating an application scenario of a vector instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3, the vector instruction processing apparatus processes the vector instruction as follows:

the control module 11 analyzes the obtained vector instruction 1 (for example, the vector instruction 1 is opcode 500101102 add1024), and obtains an operation code and an operation domain of the vector instruction 1. The operation code of the vector instruction 1 is opcode, the target address is 500, the first to-be-operated vector address is 101, and the second to-be-operated data address is 102. The vector operation type is add (vector addition). The input amount is 1024. The control module 11 obtains a first vector to be operated with a data amount of input 1024 from the vector address to be operated 101, and obtains a second vector to be operated with a data amount of input 1024 from the vector address to be operated 102. The operation module 12 performs an addition operation on the first to-be-operated vector and the second to-be-operated vector to obtain an operation result 1, and stores the operation result 1 in the target address 500.

The vector instruction 1 may be opcode 500101102 add1024 or add 5001011021024, and the processing of vector instructions of different instruction formats is similar and will not be described again.

The working process of the above modules can refer to the above related description.

Thus, the vector instruction processing device can efficiently and quickly process the vector instruction, and the processing efficiency and the processing speed for vector operation are high.

The present disclosure provides a machine learning arithmetic device, which may include one or more of the above vector instruction processing devices, and is configured to acquire a vector to be operated and control information from other processing devices, and perform a specified machine learning operation. The machine learning arithmetic device can obtain vector instructions from other machine learning arithmetic devices or non-machine learning arithmetic devices and transmit execution results to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one vector instruction processing device is included, the vector instruction processing devices can be linked and transmit data through a specific structure, for example, the vector instruction processing devices are interconnected and transmit data through a PCIE bus, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DDR4 controllers therein, where 64bit is used for data transmission and 8bit is used for ECC check in the 72-bit DDR4 controller. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600 MB/s.

In one embodiment, each group 393 of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transmission between the machine learning chip 389 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to a machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operation states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a computer device, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 shows a flow diagram of a method of vector instruction processing according to an embodiment of the present disclosure. The method can be applied to computer equipment and the like comprising a memory and a processor, wherein the memory is used for storing data used in the process of executing the method; the processor is used for executing relevant processing and operation steps, such as the steps S51 and S52. As shown in fig. 6, the method is applied to the vector instruction processing apparatus described above, and includes step S51 and step S52.

In step S51, the control module is used to parse the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, and obtain a vector to be operated and a target address required for executing the vector instruction according to the operation code and the operation domain, and determine a vector operation type of the vector instruction. The operation code is used for indicating that the operation of the vector instruction on the data is vector operation, and the operation domain comprises a vector address to be operated and a target address.

In step S52, the operation module performs vector operation on the vector to be operated according to the vector operation type to obtain an operation result, and stores the operation result in the target address.

In a possible implementation manner, performing a vector operation on a vector to be operated according to a vector operation type to obtain an operation result may include: and executing vector operation corresponding to the vector operation type by using a plurality of vector operators in the operation module.

In one possible implementation, the operation module may include a master operation submodule and a plurality of slave operation submodules, and the master operation submodule may include the plurality of vector operators. Wherein, the step S52 may include: and executing vector operation corresponding to the vector operation type by using a plurality of vector operators in the main operation sub-module to obtain an operation result, and storing the operation result into a target address.

In one possible implementation, the calculation module comprises a master calculation submodule and a plurality of slave calculation submodules, the slave calculation submodules comprise a plurality of vector calculators,

the vector operation is carried out on the vector to be operated according to the vector operation type to obtain an operation result, and the operation result is stored in a target address, and the method comprises the following steps:

utilizing a plurality of vector operators contained in each slave operation submodule to execute in parallel to perform corresponding vector operation to obtain an operation result, storing the operation result into a corresponding sub-cache space, and sending the operation result to a main operation submodule;

and receiving the operation result by using the main operation sub-module, and storing the operation result into the target address.

In one possible implementation, the operation domain may also include a vector operation type. Determining the vector operation type of the vector instruction may include: when the vector operation type is included in the operation domain, the vector operation type is determined according to the operation domain.

In one possible implementation, the operation field may further include an input quantity. Obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, wherein the method further comprises the following steps: and determining the input quantity according to the operation domain, and acquiring a vector to be operated with the data quantity as the input quantity from the data address to be operated.

In one possible implementation, the opcode is also used to indicate the vector operation type. Determining the vector operation type of the vector instruction may include: and when the operation code is used for indicating the vector operation type, determining the vector operation type according to the operation code.

In one possible implementation, the vector operation type may include at least one of: vector multiplication operation, vector and scalar multiplication operation, vector addition operation, vector summation operation, specified value storage operation meeting operation conditions, bitwise AND operation, bitwise OR operation, bitwise XOR operation, bitwise negation operation, bitwise maximum value operation and bitwise minimum value operation. The operation condition may include any one of the following: bitwise equal, bitwise unequal, bitwise less, bitwise greater than or equal to, bitwise greater than, bitwise less than or equal to.

In one possible implementation, the method may further include: storing the vector to be computed by a storage module of the device, wherein the storage module comprises at least one of a register and a cache,

the cache is used for storing data to be operated and vectors to be operated, and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

the neuron buffer is used for storing neuron data in data to be operated, and the neuron data comprises neuron vector data.

In a possible implementation manner, parsing the obtained vector instruction to obtain an opcode and an operation domain of the vector instruction may include:

a stored vector instruction;

analyzing the vector instruction to obtain an operation code and an operation domain of the vector instruction;

the method includes storing an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are sequentially arranged according to an execution order, and the plurality of instructions to be executed may include vector instructions.

In one possible implementation, the method may further include: when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is in an association relation with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction. The associating relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction may include: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area.

It should be noted that, although the vector instruction processing method is described above by taking the above-mentioned embodiment as an example, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

The vector instruction processing method provided by the embodiment of the disclosure has the advantages of wide application range, high vector processing efficiency, high vector processing speed, high vector operation processing efficiency and high vector operation processing speed.

The present disclosure also provides a non-transitory computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the above-described vector instruction processing method.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowchart of fig. 6 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It should be understood that the above-described apparatus embodiments are merely exemplary, and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In addition, unless otherwise specified, each functional unit/module in the embodiments of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. Unless otherwise specified, the storage module may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1, a vector instruction processing device, the device comprising:

the control module is used for analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

the operation module is used for carrying out vector operation on the vector to be operated according to the vector operation type to obtain an operation result and storing the operation result into the target address,

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated on and the target address.

Clause a2, the apparatus of clause a1, the computing module comprising:

a plurality of vector operators for performing vector operations corresponding to the vector operation types.

Clause A3, the apparatus of clause a2, the arithmetic module comprising a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the master arithmetic sub-module comprising the plurality of vector operators,

and the main operation sub-module is used for executing the vector operation by utilizing the plurality of vector operators to obtain an operation result and storing the operation result into the target address.

Clause a4, the apparatus of clause a2, the arithmetic module comprising a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the slave arithmetic sub-modules comprising the plurality of vector operators,

the slave operation submodule is used for executing corresponding vector operation in parallel by utilizing a plurality of contained vector operators to obtain an operation result, storing the operation result into a corresponding sub-cache space and sending the operation result to the master operation submodule;

and the main operation sub-module is also used for receiving the operation result and storing the operation result into the target address.

Clause a5, the device of clause a1, the operation domain further comprising a vector operation type,

the control module is further configured to determine a vector operation type according to the operation domain when the operation domain includes the vector operation type.

Clause a6, the apparatus of clause a1, the operational field further comprising an input quantity,

the control module is further configured to determine the input quantity according to the operation domain, and obtain a vector to be operated, where the data quantity is the input quantity, from the data address to be operated.

Clause a7, the device of clause a1, the opcode also being for indicating the vector operation type,

the control module is further configured to determine the vector operation type according to the operation code when the operation code is used to indicate the vector operation type.

Clause A8, the device of clause a1, the type of vector operations comprising at least one of:

vector multiplication operation, vector and scalar multiplication operation, vector addition operation, vector summation operation, operation of storing specified values satisfying operation conditions, bitwise and operation, bitwise or operation, bitwise xor operation, bitwise negation operation, bitwise maximum operation, bitwise minimum operation,

wherein the operation condition includes any one of: bitwise equal, bitwise unequal, bitwise less, bitwise greater than or equal to, bitwise greater than, bitwise less than or equal to.

Clause a9, the apparatus of clause a1, further comprising:

a storage module for storing the vector to be calculated,

wherein the storage module comprises at least one of a register and a cache,

the cache is used for storing data to be operated and the vector to be operated, and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

the neuron cache is used for storing neuron data in the data to be operated, wherein the neuron data comprises neuron vector data.

Clause a10, the apparatus of clause a1, the control module comprising:

an instruction storage submodule for storing the vector instructions;

the instruction processing submodule is used for analyzing the vector instruction to obtain an operation code and an operation domain of the vector instruction;

and the queue storage submodule is used for storing an instruction queue, the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the vector instructions.

Clause a11, the apparatus of clause a10, the control module further comprising:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the fact that the first instruction to be executed in the plurality of instructions to be executed is associated with a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the operation module,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

Clause a12, a machine learning computing device, the device comprising:

one or more vector instruction processing apparatus as recited in any of clauses a 1-clause a11, configured to obtain a vector to be executed and control information from another processing apparatus, perform a specified machine learning operation, and transmit an execution result to the other processing apparatus via an I/O interface;

when the machine learning arithmetic device comprises a plurality of vector instruction processing devices, the vector instruction processing devices can be connected through a specific structure and transmit data;

the vector instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of vector instruction processing devices share the same control system or own respective control systems; the vector instruction processing devices share a memory or own memories; the interconnection mode of the vector instruction processing devices is any interconnection topology.

Clause a13, a combination processing device, comprising:

the machine learning computing device, universal interconnect interface, and other processing device of clause a 12;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

Clause a14, a machine learning chip, the machine learning chip comprising:

the machine learning computing device of clause a12 or the combined processing device of clause a 13.

Clause a15, an electronic device, comprising:

the machine learning chip of clause a 14.

Clause a16, a card, comprising: a memory device, an interface device and a control device and a machine learning chip as described in clause a 14;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

Clause a17, a vector instruction processing method, the method being applied to a vector instruction processing apparatus, the apparatus including a control module and an operation module, the method comprising:

analyzing the obtained vector instruction by using a control module to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

utilizing an operation module to carry out vector operation on the vector to be operated according to the vector operation type to obtain an operation result, storing the operation result into the target address,

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated on and the target address.

Clause a18, the method of clause a17, performing vector operation on the vector to be operated according to the vector operation type, comprising:

and utilizing a plurality of vector operators in the operation module to execute vector operation corresponding to the vector operation type.

Clause a19, the method of clause a18, the calculation module comprising a master calculation sub-module and a plurality of slave calculation sub-modules, the master calculation sub-module comprising the plurality of vector calculators,

the vector operation of the vector to be operated according to the vector operation type to obtain an operation result, and storing the operation result in the target address includes:

and executing vector operation corresponding to the vector operation type by utilizing the plurality of vector operators in the main operation sub-module to obtain an operation result, and storing the operation result into the target address.

Clause a20, the method of clause a18, the calculation module comprising a master calculation sub-module and a plurality of slave calculation sub-modules, the slave calculation sub-modules comprising the plurality of vector calculators,

the vector operation of the vector to be operated according to the vector operation type to obtain an operation result, and storing the operation result in the target address includes:

utilizing a plurality of vector operators contained in each slave operation submodule to execute in parallel to perform corresponding vector operation to obtain an operation result, storing the operation result into a corresponding sub-cache space, and sending the operation result to the master operation submodule;

and receiving the operation result by using the main operation submodule, and storing the operation result into the target address.

Clause a21, the method of clause a17, the operation domain further comprising a vector operation type,

wherein determining a vector operation type of a vector instruction comprises:

and when the operation domain comprises a vector operation type, determining the vector operation type according to the operation domain.

Clause a22, the method of clause a17, the operational field further comprising an input quantity,

wherein, obtaining the vector to be operated and the target address required by the vector instruction according to the operation code and the operation domain further comprises:

and determining the input quantity according to the operation domain, and acquiring a vector to be operated with the data quantity as the input quantity from the data address to be operated.

Clause a23, the method of clause a17, the opcode further being for indicating the vector operation type,

wherein determining a vector operation type of a vector instruction comprises:

and when the operation code is used for indicating the vector operation type, determining the vector operation type according to the operation code.

Clause a24, the method of clause a17, the type of vector operations comprising at least one of:

vector multiplication operation, vector and scalar multiplication operation, vector addition operation, vector summation operation, operation of storing specified values satisfying operation conditions, bitwise and operation, bitwise or operation, bitwise xor operation, bitwise negation operation, bitwise maximum operation, bitwise minimum operation,

wherein the operation condition includes any one of: bitwise equal, bitwise unequal, bitwise less, bitwise greater than or equal to, bitwise greater than, bitwise less than or equal to.

Clause a25, the method of clause a17, the method further comprising:

storing the vector to be computed with a storage module of the device,

wherein the storage module comprises at least one of a register and a cache,

the cache is used for storing data to be operated and the vector to be operated, and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

the neuron cache is used for storing neuron data in the data to be operated, wherein the neuron data comprises neuron vector data.

Clause a26, parsing the obtained vector instruction according to the method described in clause a17 to obtain the opcode and the operation domain of the vector instruction, including:

storing the vector instruction;

analyzing the vector instruction to obtain an operation code and an operation domain of the vector instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the vector instructions.

Clause a27, the method of clause a26, the method further comprising:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

Clause a28, a non-transitory computer readable storage medium having computer program instructions stored thereon that, when executed by a processor, implement the method of any of clauses a 17-a 27.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An apparatus for vector instruction processing, the apparatus comprising:

the control module is used for analyzing the obtained vector instruction to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

the operation module is used for carrying out vector operation on the vector to be operated according to the vector operation type to obtain an operation result and storing the operation result into the target address,

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated on and the target address.

2. The apparatus of claim 1, wherein the computing module comprises:

a plurality of vector operators for performing vector operations corresponding to the vector operation types.

3. The apparatus of claim 2, wherein the operation module comprises a master operation submodule and a plurality of slave operation submodule, the master operation submodule comprising the plurality of vector operators,

and the main operation sub-module is used for executing the vector operation by utilizing the plurality of vector operators to obtain an operation result and storing the operation result into the target address.

4. A machine learning arithmetic device, the device comprising:

one or more vector instruction processing devices as claimed in any one of claims 1 to 3, configured to obtain vectors to be operated and control information from other processing devices, perform specified machine learning operations, and transmit execution results to other processing devices via the I/O interface;

when the machine learning arithmetic device comprises a plurality of vector instruction processing devices, the vector instruction processing devices can be connected through a specific structure and transmit data;

the vector instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support operation of larger-scale machine learning; a plurality of vector instruction processing devices share the same control system or own respective control systems; the vector instruction processing devices share a memory or own memories; the interconnection mode of the vector instruction processing devices is any interconnection topology.

5. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 4;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

6. A machine learning chip, the machine learning chip comprising:

the machine learning arithmetic device according to claim 4 or the combined processing device according to claim 5.

7. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 6.

8. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface device and a control device and a machine learning chip according to claim 6;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

9. A vector instruction processing method is applied to a vector instruction processing device, the device comprises a control module and an operation module, and the method comprises the following steps:

analyzing the obtained vector instruction by using a control module to obtain an operation code and an operation domain of the vector instruction, obtaining a vector to be operated and a target address required by executing the vector instruction according to the operation code and the operation domain, and determining the vector operation type of the vector instruction;

utilizing an operation module to carry out vector operation on the vector to be operated according to the vector operation type to obtain an operation result, storing the operation result into the target address,

the operation code is used for indicating that the operation of the vector instruction on data is a vector operation, and the operation domain comprises a vector address to be operated on and the target address.

10. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of claim 9.

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