CN110096309B

CN110096309B - Operation method, operation device, computer equipment and storage medium

Info

Publication number: CN110096309B
Application number: CN201910548268.1A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-11-14
Filing date: 2019-06-24
Publication date: 2020-04-14
Anticipated expiration: 2039-06-24
Also published as: CN110096309A

Abstract

The present disclosure relates to an arithmetic method, an apparatus, a computer device, and a storage medium. Wherein the combined processing device comprises: a machine learning arithmetic device, a universal interconnection interface and other processing devices; the machine learning arithmetic device interacts with other processing devices to jointly complete the calculation operation designated by the user, wherein the combined processing device further comprises: and the storage device is respectively connected with the machine learning arithmetic device and the other processing devices and is used for storing the data of the machine learning arithmetic device and the other processing devices. The operation method, the operation device, the computer equipment and the storage medium provided by the embodiment of the disclosure have wide application range, high operation processing efficiency and high processing speed.

Description

Operation method, operation device, computer equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to an average pooling instruction processing method and apparatus, a computer device, and a storage medium.

Background

With the continuous development of science and technology, machine learning, especially neural network algorithms, are more and more widely used. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of neural network algorithms is higher and higher, the types and the number of involved data operations are increasing. In the related art, Average Pooling operation for data is inefficient and slow.

Disclosure of Invention

In view of the above, the present disclosure provides an average pooling instruction processing method, apparatus, computer device and storage medium to improve efficiency and speed of average pooling operation on data.

According to a first aspect of the present disclosure, there is provided an average pooled instruction processing apparatus comprising:

the control module is used for compiling the obtained average pooling instruction to obtain a compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and obtaining data to be operated, a pooling core and a target address which are required by executing the average pooling instruction according to the operation code and the operation domain;

the operation module is used for carrying out average pooling operation on the data to be operated according to the pooling core to obtain an operation result and storing the operation result into the target address,

the operation code is used for indicating that the operation performed on the data by the average pooling instruction is an average pooling operation, and the operation domain comprises a data address to be operated on, a pooling core address and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning arithmetic device, the device including:

one or more average pooling instruction processing devices of the first aspect, configured to obtain data to be computed and control information from other processing devices, execute a specified machine learning operation, and transmit an execution result to the other processing devices through an I/O interface;

when the machine learning operation device comprises a plurality of average pooling instruction processing devices, the average pooling instruction processing devices can be connected through a specific structure and transmit data;

the plurality of average pooling instruction processing devices are interconnected through a PCIE bus of a fast peripheral equipment interconnection bus and transmit data so as to support larger-scale machine learning operation; a plurality of average pooling instruction processing devices share the same control system or own respective control systems; the average pooling instruction processing devices share a memory or own memories; the interconnection mode of the average pooling instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing apparatus, the apparatus comprising:

the machine learning arithmetic device, the universal interconnect interface, and the other processing device according to the second aspect;

and the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip including the machine learning network operation device of the second aspect or the combination processing device of the third aspect.

According to a fifth aspect of the present disclosure, there is provided a machine learning chip package structure, which includes the machine learning chip of the fourth aspect.

According to a sixth aspect of the present disclosure, a board card is provided, which includes the machine learning chip packaging structure of the fifth aspect.

According to a seventh aspect of the present disclosure, there is provided an electronic device, which includes the machine learning chip of the fourth aspect or the board of the sixth aspect.

According to an eighth aspect of the present disclosure, there is provided an average pooled instruction processing method applied to an average pooled instruction processing apparatus, the method including:

compiling the obtained average pooling instruction to obtain a compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and obtaining data to be operated, a pooling core and a target address which are required by executing the average pooling instruction according to the operation code and the operation domain;

performing average pooling operation on the data to be operated according to the pooling core to obtain an operation result, storing the operation result into the target address,

According to a ninth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above average pooling instruction processing method.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

The device comprises a control module and an operation module, wherein the control module is used for compiling the obtained average pooling instruction to obtain a compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and acquiring data to be operated, a pooling core and a target address which are required by executing the average pooling instruction according to the operation code and the operation domain; the operation module is used for carrying out average pooling operation on the data to be operated according to pooling cores to obtain operation results and storing the operation results into the target address. The method, the device, the computer equipment and the storage medium for processing the average pooling instruction provided by the embodiment of the disclosure have wide application range, high processing efficiency and high processing speed for the average pooling instruction, and high processing efficiency and high processing speed for performing average pooling operation.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 2 a-2 f show block diagrams of an average pooled instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of an application scenario of an average pooled instruction processing apparatus according to an embodiment of the present disclosure.

Fig. 4a, 4b show block diagrams of a combined processing device according to an embodiment of the present disclosure.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure.

FIG. 6 illustrates a flow diagram of an average pooled instruction processing method according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "zero," "first," "second," and the like in the claims, the description, and the drawings of the present disclosure are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Due to the wide use of neural network algorithms, the computing man power of computer hardware is continuously improved, and the types and the number of data operations involved in practical application are continuously improved. Average pooling (Average-pooling)) is a method of taking the Average of all data in a local area. Because the programming languages are various in types, in order to realize the operation process of the average pooling operation under different language environments, in the related art, as no average pooling instruction which can be widely applied to various programming languages exists at the present stage, technicians need to customize a plurality of instructions corresponding to the programming language environments to realize the average pooling operation, and the efficiency of the average pooling operation is low and the speed is low. The present disclosure provides an average pooling instruction processing method, apparatus, computer device, and storage medium, which can implement average pooling operation with only one instruction, and can significantly improve efficiency and speed of performing average pooling operation.

Fig. 1 shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the apparatus includes a control module 11 and an operation module 12.

The control module 11 is configured to compile the obtained average pooling instruction to obtain a compiled average pooling instruction, analyze the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and obtain data to be operated, a pooling core, and a target address required for executing the average pooling instruction according to the operation code and the operation domain. The operation code is used for indicating that the operation of the average pooling instruction on the data is average pooling operation, and the operation domain comprises a data address to be operated, a pooling core address and a target address.

And the operation module 12 is configured to perform average pooling operation on the data to be operated according to the pooling core to obtain an operation result, and store the operation result in the target address.

In this embodiment, the average pooling instruction obtained by the control module is an uncompiled software instruction that cannot be directly executed by hardware, and the control module needs to compile the average pooling instruction (uncompiled) first. The compiled average pooling instruction can only be parsed after it is obtained. The compiled average pooling instructions are hardware instructions that can be directly executed by hardware. The control module can respectively obtain the data to be operated and the pooling core from the data address to be operated and the pooling core address. The control module may obtain instructions and data through a data input output unit, which may be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be a part of an instruction or a field (usually indicated by a code) specified in the computer program to perform an operation, and is an instruction sequence number used to inform a device executing the instruction which instruction needs to be executed specifically. The operation domain may be a source of all data required for executing the corresponding instruction, and all data required for executing the corresponding instruction includes parameters such as data to be operated on, a pooling core, and a corresponding operation method. For an average pooled instruction it must comprise an opcode and an operation field, wherein the operation field comprises at least the data address to be computed, the pooled core address and the target address.

It should be understood that the instruction format of the average pooled instruction and the included opcode and operation field may be set as desired by those skilled in the art, and the disclosure is not limited thereto.

In this embodiment, the apparatus may include one or more control modules and one or more operation modules, and the number of the control modules and the number of the operation modules may be set according to actual needs, which is not limited in this disclosure. When the device comprises a control module, the control module can receive the average pooling instruction and control one or more operation modules to perform the average pooling operation. When the device comprises a plurality of control modules, the plurality of control modules can respectively receive the average pooling instruction and control the corresponding one or more operation modules to perform average pooling operation.

The device for processing the average pooling instruction provided by the embodiment of the disclosure comprises a control module and an operation module, wherein the control module is used for compiling the obtained average pooling instruction to obtain the compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and acquiring data to be operated, a pooling core and a target address which are required by executing the average pooling instruction according to the operation code and the operation domain; the operation module is used for carrying out average pooling operation on the data to be operated according to pooling cores to obtain operation results and storing the operation results into the target address. The average pooling instruction processing device provided by the embodiment of the disclosure has a wide application range, high processing efficiency and high processing speed for average pooling instructions, and high processing efficiency and high processing speed for average pooling operation.

Fig. 2a shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2a, the operation module 12 may include a plurality of adders 120 and a plurality of dividers 120'. The plurality of adders 120 are configured to perform addition operations in the average pooling operation. The plurality of dividers 120' are used to perform division operations in the average pooling operation.

In this implementation, the operation module may also include an adder and a divider, or include an adder and a plurality of dividers, or include a plurality of adders and a divider. The number of adders and dividers may be set according to the size of the data amount of the average pooling operation to be performed, the processing speed, efficiency, and the like of the average pooling operation, which is not limited by the present disclosure.

Fig. 2b shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2b, the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122. The main operation sub-module 121 may include a plurality of adders and a plurality of dividers.

And the main operation sub-module 121 is configured to perform addition operation and division operation in the average pooling operation by using a plurality of adders and a plurality of dividers, respectively, to obtain an operation result, and store the operation result in the target address.

In a possible implementation manner, the control module 11 is further configured to analyze the obtained calculation instruction to obtain an operation domain and an operation code of the calculation instruction, and obtain data to be operated, which is required for executing the calculation instruction, according to the operation domain and the operation code. The operation module 12 is further configured to perform an operation on the data to be operated according to the calculation instruction to obtain a calculation result of the calculation instruction. The operation module may include a plurality of operators for performing operations corresponding to operation types of the calculation instructions.

In this implementation, the calculation instruction may be other instructions for performing arithmetic operations, logical operations, and the like on data such as scalars, vectors, matrices, tensors, and the like, and those skilled in the art may set the calculation instruction according to actual needs, which is not limited by the present disclosure.

In this implementation, the arithmetic unit may include an adder, a divider, a multiplier, a comparator, and the like, which are capable of performing arithmetic operations, logical operations, and the like on data. The type and number of the arithmetic units may be set according to the requirements of the size of the data amount of the arithmetic operation to be performed, the type of the arithmetic operation, the processing speed and efficiency of the arithmetic operation on the data, and the like, which is not limited by the present disclosure.

In a possible implementation manner, the control module 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the data to be operated and the plurality of operation instructions to the main operation sub-module 121.

The master operation sub-module 121 is configured to perform preamble processing on data to be operated, and transmit data and operation instructions with the plurality of slave operation sub-modules 122.

The slave operation submodule 122 is configured to execute an intermediate operation in parallel according to the data and the operation instruction transmitted from the master operation submodule 121 to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master operation submodule 122.

The main operation sub-module 121 is further configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction, and store the calculation result in the corresponding address.

In this implementation, when the computation instruction is an operation performed on scalar or vector data, the apparatus may control the main operation sub-module to perform an operation corresponding to the computation instruction by using an operator therein. When the calculation instruction is to perform an operation on data having a dimension greater than or equal to 2, such as a matrix, a tensor, or the like, the device may control the slave operation submodule to perform an operation corresponding to the calculation instruction by using an operator therein.

It should be noted that, a person skilled in the art may set the connection manner between the master operation submodule and the plurality of slave operation submodules according to actual needs to implement the configuration setting of the operation module, for example, the configuration of the operation module may be an "H" configuration, an array configuration, a tree configuration, and the like, which is not limited in the present disclosure.

Fig. 2c shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2c, the operation module 12 may further include one or more branch operation sub-modules 123, and the branch operation sub-module 123 is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. The main operation sub-module 121 is connected to one or more branch operation sub-modules 123. Therefore, the main operation sub-module, the branch operation sub-module and the slave operation sub-module in the operation module are connected by adopting an H-shaped structure, and data and/or operation instructions are forwarded by the branch operation sub-module, so that the resource occupation of the main operation sub-module is saved, and the instruction processing speed is further improved.

Fig. 2d shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in FIG. 2d, a plurality of slave operation sub-modules 122 are distributed in an array.

Each slave operation submodule 122 is connected to another adjacent slave operation submodule 122, the master operation submodule 121 is connected to k slave operation submodules 122 of the plurality of slave operation submodules 122, and the k slave operation submodules 122 are: n slave operator sub-modules 122 of row 1, n slave operator sub-modules 122 of row m, and m slave operator sub-modules 122 of column 1.

As shown in fig. 2d, the k slave operator modules include only the n slave operator modules in the 1 st row, the n slave operator modules in the m th row, and the m slave operator modules in the 1 st column, that is, the k slave operator modules are slave operator modules directly connected to the master operator module among the plurality of slave operator modules. The k slave operation submodules are used for forwarding data and instructions between the master operation submodules and the plurality of slave operation submodules. Therefore, the plurality of slave operation sub-modules are distributed in an array, the speed of sending data and/or operation instructions to the slave operation sub-modules by the master operation sub-module can be increased, and the instruction processing speed is further increased.

Fig. 2e shows a block diagram of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2e, the operation module may further include a tree sub-module 124. The tree submodule 124 includes a root port 401 and a plurality of branch ports 402. The root port 401 is connected to the master operation submodule 121, and the plurality of branch ports 402 are connected to the plurality of slave operation submodules 122, respectively. The tree sub-module 124 has a transceiving function, and is configured to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. Therefore, the operation modules are connected in a tree-shaped structure under the action of the tree-shaped sub-modules, and the speed of sending data and/or operation instructions from the main operation sub-module to the auxiliary operation sub-module can be increased by utilizing the forwarding function of the tree-shaped sub-modules, so that the instruction processing speed is increased.

In one possible implementation, the tree submodule 124 may be an optional result of the apparatus, which may include at least one level of nodes. The nodes are line structures with forwarding functions, and the nodes do not have operation functions. The lowest level node is connected to the slave operation sub-module to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122. In particular, if the tree submodule has zero level nodes, the apparatus does not require the tree submodule.

In one possible implementation, the tree submodule 124 may include a plurality of nodes of an n-ary tree structure, and the plurality of nodes of the n-ary tree structure may have a plurality of layers.

For example, fig. 2f shows a block diagram of an average pooled instruction processing device according to an embodiment of the present disclosure. As shown in FIG. 2f, the n-ary tree structure may be a binary tree structure with tree-type sub-modules including 2 levels of nodes 01. The lowest level node 01 is connected with the slave operation sub-module 122 to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122.

In this implementation, the n-ary tree structure may also be a ternary tree structure or the like, where n is a positive integer greater than or equal to 2. The number of n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure may be set by those skilled in the art as needed, and the disclosure is not limited thereto.

In one possible implementation, the operation field may further include an input height and an input width.

The control module is further used for acquiring the data to be operated corresponding to the input width and the input height from the data address to be operated.

In this implementation, the input height and the input width may define the data amount and size of the obtained data to be operated on. The input height and the input width included in the operation field may be specific numerical values, or may be storage addresses storing the input height and the input width. When a specific numerical value of the input height and the input width is directly included in the operation field, the specific numerical value is determined as the corresponding input height and input width. When the storage addresses of the input height and the input width are included in the operation field, the input height and the input width may be obtained from the storage addresses of the input height and the input width, respectively.

In one possible implementation manner, when the input height and/or the input width are not included in the operation domain, the data to be operated may be acquired according to a preset default input height and default input width.

By the mode, the data size and the size of the data to be operated can be limited, the accuracy of the operation result is ensured, and the device can execute the average pooling instruction.

In one possible implementation, the operation domain may further include a pooled core height and a pooled core width.

The control module 11 is further configured to obtain the pooled core from the pooled core address according to the height of the pooled core and the width of the pooled core.

In one possible implementation, the operation domain may further include a first stride. The operation module 12 may be further configured to move the pooling core in the x direction according to the first step.

In one possible implementation, the operation domain may further include a second stride. The operation module 12 may be further configured to move the pooling core in the y direction according to the second step.

In this implementation, the stride of the average pooling operation is the magnitude of each moving pooling core in performing the average pooling operation. The first step size may be a size of moving the pooled kernel in the x-direction and the second step size may be a size of moving the pooled kernel in the y-direction.

In the present disclosure, only the pooling core is taken as a two-dimensional example, and parameters such as the height, the width, the first stride, and the second stride of the pooling core required for performing the average pooling operation are described, and if the pooling core is multi-dimensional, the parameters of the pooling core include the size and the stride of each dimension thereof.

In a possible implementation manner, when the first stride and the second stride are not given in the operation domain of the average pooling instruction, the operation module may use the height and the width of the pooling core as the strides of the corresponding dimensions, respectively, to ensure that the average pooling operation is performed normally. For example, the operation module 12 may be further configured to move the pooling core on the data to be operated in a non-overlapping manner, and compare a plurality of data to be operated in the area corresponding to the pooling core to obtain an operation result.

In one possible implementation, when the pooling core height and the pooling core width are not included in the operation domain, a preset default pooling core height and a preset default pooling core width may be obtained, so that the control module and the operation module may execute the average pooling instruction.

In one possible implementation, the operation domain may also include a pooling core number. The operation module 12 is further configured to perform average pooling operation on the data to be operated through a plurality of pooling cores, where the number of pooling cores is the number of pooling cores.

In this implementation, the number of pooling cores corresponds to the data to be computed. For example, when the number of the pooling cores is 5, it may be determined that the data to be operated on may be divided into five parts, and 5 pooling cores are required to perform average pooling operation on the five parts of the data to be operated on respectively.

In this implementation, when the operation domain does not include the number of pooling cores, it may be determined that only one pooling core is needed for the data to be calculated to achieve the average pooling operation.

In a possible implementation manner, the operation module 12 is further configured to perform an average pooling operation on data to be operated on, which is an integer multiple of the size of the pooling core, when the size of the data to be operated on is a non-integer multiple of the size of the pooling core. The size of the data to be calculated is a non-integer multiple of the size of the pooling kernel, and may include at least one of: the input width of the data to be operated is non-integral multiple of the width of the pooling core, and the input height of the data to be operated is non-integral multiple of the height of the pooling core.

In this implementation, the average pooling operation may not be performed for portions of the remaining data that are non-integer multiples of the size of the pooling kernel in the data to be operated on.

In one possible implementation, as shown in fig. 2 a-2 f, the apparatus may further include a storage module 13. The storage module 13 is used for storing data to be operated and the pooling core.

In this implementation, the storage module may include one or more of a cache and a register, and the cache may include a temporary cache and may further include at least one NRAM (Neuron Random Access Memory). The cache can be used for storing data to be operated and the pooling core, and the register can be used for storing scalar data in the data to be operated.

In one possible implementation, the cache may include a neuron cache. The neuron buffer, i.e., the neuron random access memory, may be configured to store neuron data in data to be operated on, where the neuron data may include neuron vector data.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may include an instruction storage sub-module 111, an instruction processing sub-module 112, and a queue storage sub-module 113.

The instruction storage submodule 111 is used for storing the compiled average pooling instructions.

The instruction processing sub-module 112 is configured to parse the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction.

The queue storage sub-module 113 is configured to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed that are sequentially arranged according to an execution order, and the plurality of instructions to be executed may include a compiled average pooling instruction.

In this implementation manner, the execution order of the multiple instructions to be executed may be arranged according to the receiving time, the priority level, and the like of the instructions to be executed to obtain an instruction queue, so that the multiple instructions to be executed are sequentially executed according to the instruction queue.

In one possible implementation, as shown in fig. 2 a-2 f, the control module 11 may further include a dependency processing sub-module 114.

The dependency relationship processing submodule 114 is configured to, when it is determined that a first to-be-executed instruction in the multiple to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, cache the first to-be-executed instruction in the instruction storage submodule 111, and after the zeroth to-be-executed instruction is executed, extract the first to-be-executed instruction from the instruction storage submodule 111 and send the first to-be-executed instruction to the operation module 12.

The method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps: the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area. On the contrary, there is no association relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, which may be that there is no overlapping area between the first storage address interval and the zeroth storage address interval.

By the method, according to the dependency relationship between the first to-be-executed instruction and the zeroth to-be-executed instruction before the first to-be-executed instruction, the subsequent first to-be-executed instruction is executed after the execution of the previous zeroth to-be-executed instruction is finished, and the accuracy of the operation result is ensured.

In a possible implementation manner, the control module 11 may be further configured to generate an assembly file according to the average pooling instruction, and translate the assembly file into a binary file, where the binary file is a compiled average pooling instruction.

In one possible implementation, the instruction format of the average pooled instruction may be:

avgpool dst src0src1srcChannel srcHeigh srcWidth kernelHeightkernelWidth sx sy

wherein avgpool is the operation code of the average pooling instruction, dst, src0, src1, src channel, src height, src width, kernelHeight, kernelWidth, sx, sy are the operation domains of the average pooling instruction. Wherein dst is a target address, src0 is a data address to be calculated, src1 is a pooled core address, src channel is the number of pooled cores, src height is an input height, src width is an input width, kernelHeight is a pooled core height, kernelWidth is a pooled core width, sx is a first step of the pooled core moving in the x direction, and sy is a second step of the pooled core moving in the y direction.

It should be understood that the location of the operation code, operation code and operation field in the instruction format of the average pooled instruction may be set as desired by one skilled in the art, and the disclosure is not limited thereto.

In one possible implementation manner, the apparatus may be disposed in one or more of a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and an embedded Neural Network Processor (NPU).

It should be noted that, although the average pooling instruction processing apparatus is described above by taking the above-described embodiment as an example, those skilled in the art will appreciate that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

Application example

An application example according to an embodiment of the present disclosure is given below in conjunction with "performing an average pooling operation with an average pooling instruction processing apparatus" as one exemplary application scenario to facilitate understanding of the flow of the average pooling instruction processing apparatus. It is understood by those skilled in the art that the following application examples are merely for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be construed as limiting the embodiments of the present disclosure

Fig. 3 shows a schematic diagram of an application scenario of an average pooled instruction processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3, the average pooling instruction processing means processes the average pooling instruction as follows:

the control module 11 compiles the obtained average pooling instruction 1 to obtain a compiled average pooling instruction 1 (for example, the average pooling instruction 1 is avgpool 500100200564322221), and analyzes the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction 1. The operation code of the average pooling instruction 1 is avgpool, the target address is 500, the address of the data to be calculated is 100, the address of the pooling core is 200, the number of the pooling cores is 5, the input height is 64, the input width is 32, the height of the pooling core is 2, the width of the pooling core is 2, the first stride is 2, and the second stride is 1. The control module 11 obtains 64 × 32 data to be operated from the data address 100 to be operated, and obtains 2 × 2 pooled cores from the pooled core address 200.

The operation module 12 performs an average pooling operation on the data to be operated by using 5 pooling cores to obtain an operation result, and stores the operation result in the target address 500.

The working process of the above modules can refer to the above related description.

Thus, the average pooling instruction can be efficiently and quickly processed, and the efficiency and speed of performing the average pooling operation are also remarkably improved.

The present disclosure provides a machine learning arithmetic device, which may include one or more of the above average pooling instruction processing devices, and is configured to acquire data to be operated and control information from other processing devices, and perform a specified machine learning operation. The machine learning arithmetic device can obtain the average pooling instruction from other machine learning arithmetic devices or non-machine learning arithmetic devices, and transmit the execution result to peripheral equipment (also called other processing devices) through an I/O interface. Peripheral devices such as cameras, displays, mice, keyboards, network cards, wifi interfaces, servers. When more than one average pooling command processing device is included, the average pooling command processing devices can be linked and transmit data through a specific structure, for example, a PCIE bus is used for interconnection and data transmission, so as to support larger-scale operation of the neural network. At this time, the same control system may be shared, or there may be separate control systems; the memory may be shared or there may be separate memories for each accelerator. In addition, the interconnection mode can be any interconnection topology.

The machine learning arithmetic device has high compatibility and can be connected with various types of servers through PCIE interfaces.

Fig. 4a shows a block diagram of a combined processing device according to an embodiment of the present disclosure. As shown in fig. 4a, the combined processing device includes the machine learning arithmetic device, the universal interconnection interface, and other processing devices. The machine learning arithmetic device interacts with other processing devices to jointly complete the operation designated by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

And the universal interconnection interface is used for transmitting data and control instructions between the machine learning arithmetic device and other processing devices. The machine learning arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the machine learning arithmetic device; control instructions can be obtained from other processing devices and written into a control cache on a machine learning arithmetic device chip; the data in the storage module of the machine learning arithmetic device can also be read and transmitted to other processing devices.

Fig. 4b shows a block diagram of a combined processing device according to an embodiment of the present disclosure. In a possible implementation manner, as shown in fig. 4b, the combined processing device may further include a storage device, and the storage device is connected to the machine learning operation device and the other processing device respectively. The storage device is used for storing data stored in the machine learning arithmetic device and the other processing device, and is particularly suitable for data which is required to be calculated and cannot be stored in the internal storage of the machine learning arithmetic device or the other processing device.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above machine learning arithmetic device or combined processing device.

The present disclosure provides a machine learning chip package structure, which includes the above machine learning chip.

Fig. 5 shows a schematic structural diagram of a board card according to an embodiment of the present disclosure. As shown in fig. 5, the board includes the above-mentioned machine learning chip package structure or the above-mentioned machine learning chip. The board may include, in addition to the machine learning chip 389, other kits including, but not limited to: memory device 390, interface device 391 and control device 392.

The memory device 390 is coupled to a machine learning chip 389 (or a machine learning chip within a machine learning chip package structure) via a bus for storing data. Memory device 390 may include multiple sets of memory cells 393. Each group of memory cells 393 is coupled to a machine learning chip 389 via a bus. It is understood that each group 393 may be a DDR SDRAM (Double Data Rate SDRAM).

DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, memory device 390 may include 4 groups of memory cells 393. Each group of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include 4 72-bit DDR4 controllers therein, where 64bit is used for data transmission and 8bit is used for ECC check in the 72-bit DDR4 controller. It is appreciated that when DDR4-3200 particles are used in each group of memory cells 393, the theoretical bandwidth of data transfer may reach 25600 MB/s.

In one embodiment, each group 393 of memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling DDR is provided in the machine learning chip 389 for controlling data transfer and data storage of each memory unit 393.

Interface device 391 is electrically coupled to machine learning chip 389 (or a machine learning chip within a machine learning chip package). The interface device 391 is used to implement data transmission between the machine learning chip 389 and an external device (e.g., a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted to the machine learning chip 289 by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device 391 may also be another interface, and the disclosure does not limit the specific representation of the other interface, and the interface device can implement the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (e.g., server) by the interface device.

The control device 392 is electrically connected to a machine learning chip 389. The control device 392 is used to monitor the state of the machine learning chip 389. Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a single chip Microcomputer (MCU). For example, machine learning chip 389 may include multiple processing chips, multiple processing cores, or multiple processing circuits, which may carry multiple loads. Therefore, the machine learning chip 389 can be in different operation states such as a multi-load and a light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing circuits and/or a plurality of processing circuits in the machine learning chip.

The present disclosure provides an electronic device, which includes the above machine learning chip or board card.

The electronic device may include a data processing apparatus, a computer device, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

The vehicle may include an aircraft, a ship, and/or a vehicle. The household appliances may include televisions, air conditioners, microwave ovens, refrigerators, electric rice cookers, humidifiers, washing machines, electric lamps, gas cookers, and range hoods. The medical device may include a nuclear magnetic resonance apparatus, a B-mode ultrasound apparatus and/or an electrocardiograph.

FIG. 6 illustrates a flow diagram of an average pooled instruction processing method according to an embodiment of the present disclosure. The method can be applied to computer equipment and the like comprising a memory and a processor, wherein the memory is used for storing data used in the process of executing the method; the processor is used for executing relevant processing and operation steps, such as the steps S51 and S52. As shown in fig. 6, the method is applied to the above-described average pooling instruction processing apparatus, and includes step S51 and step S52.

In step S51, the control module is used to compile the obtained average pooling instruction to obtain a compiled average pooling instruction, analyze the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and obtain data to be operated, a pooling core and a target address required for executing the average pooling instruction according to the operation code and the operation domain. The operation code is used for indicating that the operation of the average pooling instruction on the data is average pooling operation, and the operation domain comprises a data address to be operated, a pooling core address and a target address.

In step S52, the operation module performs an average pooling operation on the data to be operated according to the pooling kernel to obtain an operation result, and stores the operation result in the target address.

In a possible implementation manner, performing an average pooling operation on data to be operated on according to the pooling core to obtain an operation result may include: the method further includes performing an addition operation in the average pooling operation with a plurality of adders in the operation module, and performing a division operation in the average pooling operation with a plurality of dividers in the operation module.

In one possible implementation, the operation module includes a master operation submodule and a plurality of slave operation submodules, and the master operation submodule includes a plurality of adders and a plurality of dividers. Wherein, the step S52 may include:

and respectively carrying out addition operation and division operation in the average pooling operation by utilizing a plurality of adders and a plurality of dividers in the main operation sub-module to obtain an operation result, and storing the operation result into a target address.

In one possible implementation, the operation field may further include an input height and an input width. The obtaining, according to the operation code and the operation domain, data to be operated, a pooling core, and a target address required for executing the average pooling instruction may include:

and acquiring the data to be operated corresponding to the input width and the input height from the data address to be operated.

In one possible implementation, the operation domain may further include a pooled core height and a pooled core width. The obtaining, according to the operation code and the operation domain, data to be operated, a pooling core, and a target address required for executing the average pooling instruction may include:

and acquiring the pooled core from the pooled core address according to the height of the pooled core and the width of the pooled core.

In one possible implementation, the operation domain may further include a first stride. The average pooling operation of the data to be operated according to the pooling core may include: the pooling core is moved in the x-direction in a first step.

In one possible implementation, the operation domain may further include a second stride. The average pooling operation of the data to be operated according to the pooling core may include: the pooled kernel is moved in the y-direction in a second step.

In a possible implementation manner, performing an average pooling operation on data to be operated on according to the pooling core to obtain an operation result may include:

and moving the pooling cores in a non-overlapping manner on the data to be operated, and comparing a plurality of data to be operated in the area corresponding to the pooling cores to obtain an operation result.

when the size of the data to be operated is not integral multiple of the size of the pooling core, performing average pooling operation on the data which is integral multiple of the size of the pooling core in the data to be operated,

the size of the data to be operated is a non-integral multiple of the size of the pooling kernel, and may include at least one of the following: the input width of the data to be operated is non-integral multiple of the width of the pooling core, and the input height of the data to be operated is non-integral multiple of the height of the pooling core.

In one possible implementation, the operation domain may also include a pooling core number. The average pooling operation is performed on the data to be operated according to the pooling core to obtain an operation result, and the average pooling operation may include:

and carrying out average pooling operation on the data to be operated through a plurality of pooling cores with the number being the number of the pooling cores.

In one possible implementation, the method may further include: and storing the data to be operated and the pooling core by using a storage module of the device. The storage module may include at least one of a register and a cache, where the cache is used to store data to be operated and a pooled core, and the cache may include at least one neuron cache NRAM; the register is used for storing scalar data in the data to be operated; the neuron buffer is used for storing neuron data in data to be operated on, and the neuron data can comprise neuron vector data.

In a possible implementation manner, parsing the obtained average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction may include:

storing the compiled average pooling instructions;

analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed can comprise compiled average pooling instructions.

In one possible implementation, the method may further include: when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions has an association relation with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, after the zeroth to-be-executed instruction is executed, executing the first to-be-executed instruction,

the method for determining the zero-th instruction to be executed before the first instruction to be executed has an incidence relation with the first instruction to be executed comprises the following steps:

the first storage address interval for storing the data required by the first to-be-executed instruction and the zeroth storage address interval for storing the data required by the zeroth to-be-executed instruction have an overlapped area.

In a possible implementation manner, compiling the obtained average pooling instruction to obtain a compiled average pooling instruction may include:

and generating an assembly file according to the average pooling instruction, and translating the assembly file into a binary file. Wherein the binary file is a compiled average pooling instruction.

It should be noted that, although the average pooling instruction processing method is described above by taking the above embodiment as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scene, as long as the technical scheme of the disclosure is met.

The average pooling instruction processing method provided by the embodiment of the disclosure has the advantages of wide application range, high processing efficiency and high processing speed for average pooling instructions, and high processing efficiency and high processing speed for average pooling operation.

The present disclosure also provides a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above average pooling instruction processing method.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowchart of fig. 6 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It should be understood that the above-described apparatus embodiments are merely exemplary, and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.

In addition, unless otherwise specified, each functional unit/module in the embodiments of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.

If the integrated unit/module is implemented in hardware, the hardware may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. Unless otherwise specified, the storage module may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.

The integrated units/modules, if implemented in the form of software program modules and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1, an average pooling instruction processing apparatus, the apparatus comprising:

Clause a2, the apparatus of clause a1, the computing module comprising:

a plurality of adders for performing addition operations in the average pooling operation;

a plurality of dividers for performing division operations in the average pooling operation.

Clause A3, the apparatus of clause a2, the operation module comprising a master operation sub-module and a plurality of slave operation sub-modules, the master operation sub-module comprising the plurality of adders and the plurality of dividers,

and the main operation sub-module is used for respectively performing addition operation and division operation in the average pooling operation by using the adders and the dividers to obtain operation results, and storing the operation results into the target address.

Clause a4, the apparatus of clause a1, the operation field further comprising an input height and an input width,

the control module is further configured to obtain data to be operated corresponding to the input width and the input height from the data address to be operated.

Clause a5, the apparatus of clause a1, the operational domain further comprising a pooled kernel height and a pooled kernel width,

the control module is further configured to obtain the pooled core from the pooled core address according to the pooled core height and the pooled core width.

Clause a6, the apparatus of clause a1, the operational domain further comprising a first stride,

the operation module is further configured to move the pooling kernel in an x direction according to the first step.

Clause a7, the apparatus of clause a1, the operational domain further comprising a second stride,

and the operation module is further configured to move the pooling core in the y direction according to the second step size.

Clause A8, the apparatus of clause a1,

the operation module is further configured to move the pooling core in a non-overlapping manner on the data to be operated, and compare a plurality of data to be operated in an area corresponding to the pooling core to obtain the operation result.

Clause a9, the apparatus of clause a1,

the operation module is further configured to perform average pooling operation on data that is an integer multiple of the size of the pooling core in the to-be-operated data when the size of the to-be-operated data is a non-integer multiple of the size of the pooling core,

wherein the size of the data to be operated is a non-integral multiple of the size of the pooling kernel, and the size includes at least one of the following items: the input width of the data to be operated is non-integral multiple of the width of the pooling core, and the input height of the data to be operated is non-integral multiple of the height of the pooling core.

Clause a10, the apparatus of clause a1, the operational domain further comprising a number of pooling cores,

the operation module is further configured to perform average pooling operation on the data to be operated through a plurality of pooling cores, the number of which is the number of the pooling cores.

Clause a11, the apparatus of clause a1, further comprising:

a storage module for storing the data to be operated and the pooling core,

wherein the storage module comprises at least one of a register and a cache,

the cache is used for storing the data to be operated and the pooling core, and comprises at least one neuron cache NRAM;

the register is used for storing scalar data in the data to be operated;

the neuron cache is used for storing neuron data in the data to be operated, wherein the neuron data comprises neuron vector data.

Clause a12, the apparatus of clause a1, the control module comprising:

the instruction storage submodule is used for storing the compiled average pooling instruction;

the instruction processing submodule is used for analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction;

and the queue storage submodule is used for storing an instruction queue, the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the compiled average pooling instructions.

Clause a13, the apparatus of clause a12, the control module further comprising:

the dependency relationship processing submodule is used for caching a first instruction to be executed in the instruction storage submodule when the fact that the first instruction to be executed in the plurality of instructions to be executed is associated with a zeroth instruction to be executed before the first instruction to be executed is determined, extracting the first instruction to be executed from the instruction storage submodule after the zeroth instruction to be executed is executed, and sending the first instruction to be executed to the operation module,

wherein the association relationship between the first to-be-executed instruction and a zeroth to-be-executed instruction before the first to-be-executed instruction comprises:

and a first storage address interval for storing the data required by the first instruction to be executed and a zeroth storage address interval for storing the data required by the zeroth instruction to be executed have an overlapped area.

Clause a14, the apparatus of clause a1,

the control module is also used for generating an assembly file according to the average pooling instruction and translating the assembly file into a binary file,

wherein the binary file is the compiled average pooling instruction.

Clause a15, a machine learning computing device, the device comprising:

one or more average pooling instruction processing devices as described in any of clauses a 1-clause a14, configured to obtain data and control information to be computed from other processing devices, perform a specified machine learning operation, and transmit the execution result to other processing devices through an I/O interface;

Clause a16, a combination processing device, comprising:

the machine learning computing device, universal interconnect interface, and other processing device of clause a 15;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

Clause a17, a machine learning chip, the machine learning chip comprising:

the machine learning computing device of clause a15 or the combined processing device of clause a 16.

Clause a18, an electronic device, comprising:

the machine learning chip of clause a 17.

Clause a19, a card, comprising: a memory device, an interface device and a control device and a machine learning chip as described in clause a 17;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

Clause a20, an average pooling instruction processing method applied to an average pooling instruction processing apparatus including a control module and an operation module, the method comprising:

compiling the obtained average pooling instruction by using a control module to obtain a compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, and obtaining data to be operated, a pooling core and a target address required by executing the average pooling instruction according to the operation code and the operation domain;

utilizing an operation module to perform average pooling operation on the data to be operated according to the pooling core to obtain an operation result, storing the operation result into the target address,

Clause a21, performing an average pooling operation on the data to be operated according to the pooling core according to the method of clause a20, and obtaining an operation result, including:

performing an addition operation in the average pooling operation with a plurality of adders in the operation module, and performing a division operation in the average pooling operation with a plurality of dividers in the operation module.

Clause a22, the method of clause a21, the arithmetic module comprising a master arithmetic sub-module and a plurality of slave arithmetic sub-modules, the master arithmetic sub-module comprising a plurality of adders and a plurality of dividers,

wherein, according to the pooling core, performing average pooling operation on the data to be operated to obtain an operation result, and storing the operation result in the target address, comprises:

and respectively carrying out addition operation and division operation in the average pooling operation by utilizing the adders and the dividers in the main operation sub-module to obtain an operation result, and storing the operation result into the target address.

Clause a23, the method of clause a20, the operation field further comprising an input height and an input width,

acquiring data to be operated, a pooling core and a target address required for executing the average pooling instruction according to the operation code and the operation domain, wherein the method comprises the following steps:

Clause a24, the method of clause a20, the operational domain further comprising a pooled kernel height and a pooled kernel width,

acquiring data to be operated, a pooling core and a target address required for executing an average pooling instruction according to the operation code and the operation domain, wherein the method comprises the following steps:

Clause a25, the method of clause a20, the operational domain further comprising a first stride,

wherein, according to the pooling core, performing average pooling operation on the data to be operated, comprises:

moving the pooling core in the x-direction according to the first step width.

Clause a26, the method of clause a20, the operational domain further comprising a second stride,

moving the pooling core in the y-direction according to the second swath.

Clause a27, performing an average pooling operation on the data to be operated according to the pooling core according to the method of clause a20, and obtaining an operation result, including:

and moving the pooling cores in a non-overlapping manner on the data to be operated, and comparing a plurality of data to be operated in the area corresponding to the pooling cores to obtain the operation result.

Clause a28, performing an average pooling operation on the data to be operated according to the pooling core according to the method of clause a20, and obtaining an operation result, including:

when the size of the data to be operated on is not integral multiple of the size of the pooling core, performing average pooling operation on the data which is integral multiple of the size of the pooling core in the data to be operated on,

Clause a29, the method of clause a20, the operational domain further comprising a number of pooling cores,

wherein, according to the pooling core, performing average pooling operation on the data to be operated to obtain an operation result, comprising:

Clause a30, the method of clause a20, the method further comprising:

storing the data to be operated and the pooling core by using a storage module of the device,

wherein the storage module comprises at least one of a register and a cache,

the register is used for storing scalar data in the data to be operated;

the neuron cache is used for storing neuron data in the data to be operated, and the neuron data comprises neuron vector data.

Clause a31, according to the method described in clause a20, parsing the obtained average pooling instruction to obtain the operation code and the operation domain of the average pooling instruction, includes:

storing the compiled average pooling instructions;

and storing an instruction queue, wherein the instruction queue comprises a plurality of instructions to be executed which are sequentially arranged according to an execution sequence, and the plurality of instructions to be executed comprise the compiled average pooling instruction.

Clause a32, the method of clause a31, the method further comprising:

when determining that the first to-be-executed instruction in the plurality of to-be-executed instructions is associated with a zeroth to-be-executed instruction before the first to-be-executed instruction, caching the first to-be-executed instruction, and after determining that the zeroth to-be-executed instruction is completely executed, controlling to execute the first to-be-executed instruction,

Clause a33, compiling the obtained average pooling instruction according to the method of clause a20 to obtain a compiled average pooling instruction, including:

generating an assembly file according to the average pooling instruction, and translating the assembly file into a binary file,

wherein the binary file is the compiled average pooling instruction.

Clause a34, a non-transitory computer readable storage medium having computer program instructions stored thereon that, when executed by a processor, implement the method of any of clauses a 20-a 33.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An average pooling instruction processing apparatus, characterized in that the apparatus comprises:

a control module, configured to compile the obtained average pooling instruction to obtain a compiled average pooling instruction, analyze the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, where the operation code is used to indicate that an operation performed on data by the average pooling instruction is an average pooling operation, and the operation domain includes a data address to be operated, a pooling core address, a target address, and

determining that the operation of the average pooling instruction on data is average pooling operation according to the operation code, acquiring data to be operated according to the address of the data to be operated in the operation domain, acquiring a pooling core according to the address of the pooling core in the operation domain, and determining a target address in the operation domain;

and the operation module is used for carrying out average pooling operation on the data to be operated according to the pooling core to obtain an operation result and storing the operation result into the target address.

2. The apparatus of claim 1, wherein the computing module comprises:

3. The apparatus of claim 2, wherein the operation module comprises a master operation submodule and a plurality of slave operation submodule, the master operation submodule comprising the plurality of adders and the plurality of dividers,

4. The apparatus of claim 1, wherein the operational field further comprises an input height and an input width,

5. The apparatus of claim 1, wherein the operational domain further comprises a pooled kernel height and a pooled kernel width,

6. The apparatus of claim 1, wherein the operational realm further comprises a first stride,

7. The apparatus of claim 1, wherein the operational realm further comprises a second stride,

8. The apparatus of claim 1,

9. The apparatus of claim 1,

10. The apparatus of claim 1, wherein the operational domain further comprises a pooling core number,

11. The apparatus of claim 1, further comprising:

a storage module for storing the data to be operated and the pooling core,

wherein the storage module comprises at least one of a register and a cache,

the register is used for storing scalar data in the data to be operated;

12. The apparatus of claim 1, wherein the control module comprises:

13. The apparatus of claim 12, wherein the control module further comprises:

14. The apparatus of claim 1,

wherein the binary file is the compiled average pooling instruction.

15. A machine learning arithmetic device, the device comprising:

one or more average pooling instruction processing devices according to any one of claims 1-14 for obtaining data and control information to be computed from other processing devices, performing specified machine learning operations, and transferring the results of the execution to other processing devices via an I/O interface;

16. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, universal interconnect interface, and other processing device of claim 15;

17. A machine learning chip, the machine learning chip comprising:

a machine learning computation apparatus according to claim 15 or a combined processing apparatus according to claim 16.

18. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 17.

19. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface apparatus and a control device and a machine learning chip according to claim 17;

the storage device is used for storing data;

20. An average pooling instruction processing method applied to an average pooling instruction processing apparatus including a control module and an operation module, the method comprising:

compiling the obtained average pooling instruction by using a control module to obtain a compiled average pooling instruction, analyzing the compiled average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction, wherein the operation code is used for indicating the operation of the average pooling instruction on data to be average pooling operation, and the operation domain comprises a data address to be operated, a pooling kernel address and a target address, and

determining that the operation of the average pooling instruction on data is average pooling operation according to the operation code by using a control module, acquiring data to be operated according to the address of the data to be operated in the operation domain, acquiring a pooling kernel according to the address of the pooling kernel in the operation domain, and determining a target address in the operation domain;

21. The method of claim 20, wherein performing an average pooling operation on the data to be operated on according to the pooling core to obtain an operation result comprises:

22. The method of claim 21, wherein the operation module comprises a master operation submodule and a plurality of slave operation submodule, the master operation submodule comprising a plurality of adders and a plurality of dividers,

23. The method of claim 20, wherein the operation field further comprises an input height and an input width,

the method for acquiring the data to be operated according to the data address to be operated in the operation domain comprises the following steps:

24. The method of claim 20, wherein the operational domain further comprises a pooled kernel height and a pooled kernel width,

25. The method of claim 20, wherein the operation domain further comprises a first stride,

moving the pooling core in the x-direction according to the first step width.

26. The method of claim 20, wherein the operation domain further comprises a second stride,

moving the pooling core in the y-direction according to the second swath.

27. The method of claim 20, wherein performing an average pooling operation on the data to be operated on according to the pooling core to obtain an operation result comprises:

28. The method of claim 20, wherein performing an average pooling operation on the data to be operated on according to the pooling core to obtain an operation result comprises:

29. The method of claim 20, wherein the operational domain further comprises a pooling core number,

30. The method of claim 20, further comprising:

wherein the storage module comprises at least one of a register and a cache,

the register is used for storing scalar data in the data to be operated;

31. The method of claim 20, wherein parsing the obtained average pooling instruction to obtain an operation code and an operation domain of the average pooling instruction comprises:

storing the compiled average pooling instructions;

32. The method of claim 31, further comprising:

33. The method of claim 20, wherein compiling the obtained average pooling instruction to obtain a compiled average pooling instruction comprises:

wherein the binary file is the compiled average pooling instruction.

34. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the method of any of claims 20 to 33.