CN114280941A - VDES communication method based on fractional order multi-time-lag memristor neural network - Google Patents
VDES communication method based on fractional order multi-time-lag memristor neural network Download PDFInfo
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Abstract
The invention belongs to the technical field of communication, and particularly relates to a VDES communication method based on a fractional order multi-time-lag memristor neural network. The method comprises the following steps: constructing a driving network based on a two-dimensional fractional order multi-time-lag memristive neural network; constructing a response network of a two-dimensional fractional order multi-time-lag memristor neural network; designing the synchronous controller to synchronize the drive network and the response network; selecting a signal transmission channel, and determining inherent noise n (t) in the channel; encrypting the plaintext signal to be sent at a sending end; transmitting the ciphertext signal s (t); the transmitted ciphertext signal is transmitted by a channel and then superposed with the inherent noise of the channel; and decrypting the received signal at the receiving end. The technical scheme can overcome the defects of low complexity and poor safety of the existing secret communication technology.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a VDES communication method based on a fractional order multi-time-lag memristor neural network.
Background
In recent years, with the increasing demand for marine communications, conventional AIS (Automatic Identification System) has been unable to meet the demand. When high-density and high-capacity communication is carried out, the data link of the AIS system is often overloaded, so that the problems of information congestion and the like occur, and the marine navigation safety is seriously influenced. To solve this problem, the concept of VDES (Data Exchange System) is proposed. It is used as the upgrading of AIS system, and has faster script and stronger data exchange capacity in VHF frequency band. However, while the multifunctional communication requirement is met, data security is concerned, and especially in the field of military maritime communication, the realization of data secret communication is very slow. At present, secure communication in AIS and VDES is not perfect. However, in the promising VDES system, the secure and confidential communication of information is more important. The VDES is required to meet the application requirements of offshore multi-service and multi-function, and also to meet the requirements of high security and high reliability of maritime communication.
Among the existing secure communication schemes, the chaotic secure communication scheme is popular. Chaos is considered as a third important revolution after relativity and quantum mechanics, and due to the fact that chaotic signals generated by a synchronous system have wide-band noise-like characteristics which are difficult to predict and the chaos characteristics have orderliness, a new thought is provided for aspects of secret communication, image processing, mode recognition and the like. In 1971, the existence of a relation element for describing charge and magnetic flux is theoretically conceived and predicted by professor zeisu begonia of berkeley division, california university according to the principle of completeness of combination of basic variables of a circuit, and the relation element is named as a memristor. In 2008, hewlett packard laboratory researchers observed the memristive behavior of nanoscale crosspoint devices in the cross-point memory array, which led people to make an all-round study on memristors. Since then, one applies memristors to the design of neural networks. Due to the non-volatility of the memristor, the neural network constructed by the memristor has more complex nonlinear dynamic behaviors such as chaotic behaviors compared with a general chaotic neural network. Compared with a chaotic path generated by a common neural network, the chaotic path is more difficult to trace and more complex; making it particularly advantageous in secure communications.
The existing secure communication schemes of the memristive neural network mainly focus on the range of integral orders. The integer order does not have more complicated characteristics and wider application range relatively; therefore, the security of the generated encrypted signal is low, the complexity of the constructed security system is low, and the wide application of the security system in the VDES security communication field is limited by the limitations.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a VDES communication method based on a fractional order multi-time-lag memristive neural network, which overcomes the problems of low complexity and insufficient safety of the existing secret communication technology.
The scheme for solving the technical problems is as follows:
a VDES communication method based on a fractional order multi-time-lag memristor neural network comprises the following steps:
s1: constructing a driving network based on a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the driving network is as follows:
in the above formula, xi(t) is the state variable driving the network, α is the order of the fractional order, c is the self-feedback coefficient of the network, fij(xj(t)) represents the activation function without dead time associated with the memristor in the drive network, gij(xj(t-τi) Represents an activation function with a time lag associated with the memristor in the drive network; said activation function fij(xj(t)) and gij(xj(t-τi) Satisfy f)i(xi(t))＝tanh(xi),gi(xi)＝sin(xi)i＝1,2；τiIs a multiple time lag, I, due to inconsistencies in neuronal information transfer and processingiTo drive external disturbances in the network, I is satisfiedi＝sin t i＝1,2；aijAnd bijConnecting weights related to memristors in the driving network;
s2: constructing a response network of a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the response network is:
in the above formula, yi(t) is a state variable of the response network, α is an order of the fractional order, c is a self-feedback coefficient of the network, fij(yj(t)) represents the activation function without dead time associated with the memristor in the response network, gij(yj(t-τi) Represents an activation function with a time lag associated with a memristor in a response network; said activation function fij(yj(t)) and gij(yj(t-τi) Satisfy f)i(yi(t))＝tanh(yi),gi(yi)＝sin(yi)i＝1,2；τiIs a multiple time lag caused by the inconsistency of neuron information transmission and processing, u (t) is a synchronous controller which needs to be designed to enable a driving system and a response system to achieve synchronization, IiIn response to external interference in the network, I is satisfiedi＝sin t i＝1,2；aijAnd bijConnection weights associated with memristors in the response network;
s3: a synchronization controller configured to synchronize said drive network and said response network:
s3.1: constructing an error signal defining a synchronization error as:
ei(t)＝yi(t)-xi(t) i＝1,2
in the above formula, xi(t) is a state variable of the drive network; y isi(t) is a state variable of the response network;
s3.2: based on the synchronization error, obtaining an adaptive controller as follows:
in the above formula, k (t) is a feedback function of the design controller;
taking the self-adaptive controller as a required synchronous controller;
s4: selecting a channel for signal transmission, determining noise n (t) inherent in the channel:
the channel is selected to be an AWGN channel, and n (t) is white Gaussian noise in the AWGN channel;
s5: encrypting a plaintext signal m (t) to be sent at a sending end:
s5.1: generating a chaotic signal zeta (t) by using a driving network as a chaotic signal generator of a signal sending end;
s5.2: carrying out encryption operation on the plaintext signal m (t) and the chaotic signal zeta (t) to obtain a ciphertext signal s (t); the encryption operation method is signal addition operation;
s6: transmitting said ciphertext signal s (t); after being transmitted through a channel, the sent ciphertext signal is superposed with inherent noise n (t) in the channel, namely, a receiving signal received by a receiving end is r (t) ═ s (t) + n (t);
s7: decrypting said received signal r (t) at the receiving end:
s7.1: the response network is used as a chaotic signal generator of a signal receiving end to generate a synchronous chaotic signal omega (t) which is synchronous with a chaotic signal zeta (t) of a transmitting end;
s7.2: carrying out decryption operation on a received signal r (t) and the synchronous chaotic signal omega (t) to obtain a decrypted signal m' (t), wherein the decryption operation is the inverse operation corresponding to the encryption operation of a sending end, namely subtraction operation; the algorithm terminates.
Compared with the prior art, the VDES communication method based on the fractional order multi-time-lag memristor neural network has the following beneficial effects:
the fractional order multi-time-lag memristive neural network is used as an encryption carrier in the VDES communication system, so that the difficulty of signal decoding is greatly increased, the problems of low complexity and insufficient confidentiality of the conventional chaotic neural network can be solved, and the technical effect enables the VDES communication system to be applied to a general communication network and can be better applied to the field of military communication.
Drawings
FIG. 1 is a signal flow block diagram of a communication process in a VDES communication method based on a fractional order multi-lag memristor neural network disclosed by the present invention;
FIG. 2 is a time response diagram of a plaintext signal in the VDES communication method based on the fractional order multi-lag memristor neural network disclosed by the present invention;
FIG. 3 is a time response diagram of an encrypted signal after being transmitted through a channel in the VDES communication method based on the fractional order multi-lag memristor neural network disclosed by the present invention;
FIG. 4 is a time response diagram of a decryption signal in the VDES communication method based on the fractional order multi-lag memristor neural network disclosed by the present invention
FIG. 5 is a curve variation diagram of an error measure function between a plaintext signal at a transmitting end and a decrypted signal at a receiving end in the VDES communication method based on the fractional order multi-lag memristor neural network disclosed by the present invention;
Detailed Description
The invention will be further explained with reference to the drawings.
Example 1
As shown in fig. 1, the VDES communication method based on the fractional order multi-lag memristive neural network disclosed by the present invention includes the following steps:
s1: constructing a driving network based on a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the driving network is as follows:
in the above formula, xi(t) is the state variable driving the network, α is the order of the fractional order, c is the self-feedback coefficient of the network, fij(xj(t)) represents the activation function without dead time associated with the memristor in the drive network, gij(xj(t-τi) Represents an activation function with a time lag associated with the memristor in the drive network; said activation function fij(xj(t)) and gij(xj(t-τi) Satisfy f)i(xi(t))＝tanh(xi),gi(xi)＝sin(xi)i＝1,2；τiIs a multiple time lag, I, due to inconsistencies in neuronal information transfer and processingiTo drive external disturbances in the network, I is satisfiedi＝sin t i＝1,2；aijAnd bijConnecting weights related to memristors in the driving network;
s2: constructing a response network of a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the response network is:
in the above formula, yi(t) is a state variable of the response network, α is an order of the fractional order, c is a self-feedback coefficient of the network, fij(yj(t)) represents the activation function without dead time associated with the memristor in the response network, gij(yj(t-τi) Represents an activation function with a time lag associated with a memristor in a response network; said activation function fij(yj(t)) and gij(yj(t-τi) Satisfy f)i(yi(t))＝tanh(yi),gi(yi)＝sin(yi)i＝1,2；τiIs a multiple lag time due to the inconsistency of neuron information transfer and processing, u: (t) is a synchronous controller designed to synchronize the drive system and the response system, I)iIn response to external interference in the network, I is satisfiedi＝sin t i＝1,2；aijAnd bijConnection weights associated with memristors in the response network;
s3: a synchronization controller configured to synchronize said drive network and said response network:
s3.1: constructing an error signal defining a synchronization error as:
ei(t)＝yi(t)-xi(t) i＝1,2
in the above formula, xi(t) is a state variable of the drive network; y isi(t) is a state variable of the response network;
s3.2: based on the synchronization error, obtaining an adaptive controller as follows:
in the above formula, k (t) is a feedback function of the design controller;
taking the self-adaptive controller as a required synchronous controller;
s4: selecting a channel for signal transmission, determining noise n (t) inherent in the channel:
the channel is selected to be an AWGN channel, and n (t) is white Gaussian noise in the AWGN channel;
s5: encrypting a plaintext signal m (t) to be sent at a sending end:
s5.1: generating a chaotic signal zeta (t) by using a driving network as a chaotic signal generator of a signal sending end;
s5.2: carrying out encryption operation on the plaintext signal m (t) and the chaotic signal zeta (t) to obtain a ciphertext signal s (t); the encryption operation method is signal addition operation;
s6: transmitting said ciphertext signal s (t); after being transmitted through a channel, the sent ciphertext signal is superposed with inherent noise n (t) in the channel, namely, a receiving signal received by a receiving end is r (t) ═ s (t) + n (t);
s7: decrypting said received signal r (t) at the receiving end:
s7.1: the response network is used as a chaotic signal generator of a signal receiving end to generate a synchronous chaotic signal omega (t) which is synchronous with a chaotic signal zeta (t) of a transmitting end;
s7.2: carrying out decryption operation on a received signal r (t) and the synchronous chaotic signal omega (t) to obtain a decrypted signal m' (t), wherein the decryption operation is the inverse operation corresponding to the encryption operation of a sending end, namely subtraction operation; the algorithm terminates.
Example 2 (simulation verification)
In the embodiment, a simulation test is carried out by using a PC (personal computer) with a CPU (central processing unit) of i5-9400f and an operating memory of 8G as a simulated hardware environment and using Matlab2016a as a simulated software tool, and the purpose of the test is to verify the safety performance of the VDES secret communication method provided in the embodiment 1; in the test process, the order α of the fractional order is 0.98, the self-feedback coefficient c of the network is 1, and the initial values of the driving network and the response system are respectively selected from x (0) ═ 0.1, -0.3, and y (0) ═ 0.3, 1.2.
The response curve of the plaintext signal with respect to time in this embodiment is shown in fig. 2.
Plaintext signals are encrypted at a transmitting end through a driving network taking a fractional order multi-time-lag memristive neural network as a model, and then transmitted into a VDES channel, and obtained ciphertext signals transmitted in the channel are shown in figure 3.
Meanwhile, in the present embodiment, the error measure function is defined as:
η(t)＝m(t)′-m(t)，
in the above formula, η (t) is an error measure function, and m (t)' is a decryption signal obtained by the decryption operation at the receiving end; m (t) is a plaintext signal.
And drawing an error curve between the plaintext signal decrypted by the receiving end and the plaintext signal of the transmitting end according to the value of the error measure function, wherein the curve is shown in fig. 4, the abscissa is time t, and the ordinate is η (t).
By comparing the signals of fig. 2 and 3, in conjunction with the curves of fig. 5, it can be found that: the signal obtained by the signal through the transmitting end is in a chaotic state, and the signal in channel transmission is also in a chaotic state, so that a good confidentiality effect is achieved; as can be seen from fig. 2 and fig. 4, the plaintext signal recovered by the receiving end can achieve a synchronization effect with the initial plaintext signal to be sent, so that the signal is effectively recovered.
It should be noted that: the value of the error measure function is not always zero in the actual process because the noise is still present after the encrypted signal is transmitted through the VDES channel and decrypted.
Claims (1)
1. A VDES communication method based on a fractional order multi-time-lag memristor neural network comprises the following steps:
s1: constructing a driving network based on a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the driving network is as follows:
in the above formula, xi(t) is the state variable driving the network, α is the order of the fractional order, c is the self-feedback coefficient of the network, fij(xj(t)) represents the activation function without dead time associated with the memristor in the drive network, gij(xj(t-τi) Represents an activation function with a time lag associated with the memristor in the drive network; said activation function fij(xj(t)) and gij(xj(t-τi) Satisfy f)i(xi(t))＝tanh(xi),gi(xi)＝sin(xi)i＝1,2；τiIs a multiple time lag, I, due to inconsistencies in neuronal information transfer and processingiTo drive external disturbances in the network, I is satisfiedi＝sint i＝1,2；aijAnd bijConnecting weights related to memristors in the driving network;
s2: constructing a response network of a two-dimensional fractional order multi-time-lag memristor neural network:
the expression of the response network is:
in the above formula, yi(t) is a state variable of the response network, α is an order of the fractional order, c is a self-feedback coefficient of the network, fij(yj(t)) represents the activation function without dead time associated with the memristor in the response network, gij(yj(t-τi) Represents an activation function with a time lag associated with a memristor in a response network; said activation function fij(yj(t)) and gij(yj(t-τi) Satisfy f)i(yi(t))＝tanh(yi),gi(yi)＝sin(yi)i＝1,2；τiIs a multiple time lag caused by the inconsistency of neuron information transmission and processing, u (t) is a synchronous controller which needs to be designed to enable a driving system and a response system to achieve synchronization, IiIn response to external interference in the network, I is satisfiedi＝sint i＝1,2；aijAnd bijConnection weights associated with memristors in the response network;
s3: a synchronization controller configured to synchronize said drive network and said response network:
s3.1: constructing an error signal defining a synchronization error as:
ei(t)＝yi(t)-xi(t)i＝1,2
in the above formula, xi(t) is a state variable of the drive network; y isi(t) is a state variable of the response network;
s3.2: based on the synchronization error, obtaining an adaptive controller as follows:
in the above formula, k (t) is a feedback function of the design controller;
taking the self-adaptive controller as a required synchronous controller;
s4: selecting a channel for signal transmission, determining noise n (t) inherent in the channel:
the channel is selected to be an AWGN channel, and n (t) is white Gaussian noise in the AWGN channel;
s5: encrypting a plaintext signal m (t) to be sent at a sending end:
s5.1: generating a chaotic signal zeta (t) by using a driving network as a chaotic signal generator of a signal sending end;
s5.2: carrying out encryption operation on the plaintext signal m (t) and the chaotic signal zeta (t) to obtain a ciphertext signal s (t); the encryption operation method is signal addition operation;
s6: transmitting said ciphertext signal s (t); after being transmitted through a channel, the sent ciphertext signal is superposed with inherent noise n (t) in the channel, namely, a receiving signal received by a receiving end is r (t) ═ s (t) + n (t);
s7: decrypting said received signal r (t) at the receiving end:
s7.1: the response network is used as a chaotic signal generator of a signal receiving end to generate a synchronous chaotic signal omega (t) which is synchronous with a chaotic signal zeta (t) of a transmitting end;
s7.2: carrying out decryption operation on a received signal r (t) and the synchronous chaotic signal omega (t) to obtain a decrypted signal m' (t), wherein the decryption operation is the inverse operation corresponding to the encryption operation of a sending end, namely subtraction operation; the algorithm terminates.
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| CN116962588A (en) * | 2023-07-03 | 2023-10-27 | 盐城工学院 | Image encryption method and system based on uncertain neural network of proportion time lag parameter |
| CN116800508B (en) * | 2023-07-03 | 2024-01-09 | 盐城工学院 | Complex value memristor neural network secret communication method with reaction diffusion term |
| CN116962588B (en) * | 2023-07-03 | 2024-01-30 | 盐城工学院 | Image encryption method and system based on uncertain neural network of proportion time lag parameter |
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