CN114268080B - M-LVDS drive circuit capable of preventing bus leakage - Google Patents
M-LVDS drive circuit capable of preventing bus leakage Download PDFInfo
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Abstract
The invention discloses an M-LVDS driving circuit for preventing bus leakage, which belongs to the field of integrated circuit I/O ports and comprises a secondary power supply, a main driving circuit connected with the secondary power supply, a switching tube and a floating liner circuit; the secondary power supply comprises two stages of power supplies which are used for supplying power to the main driving circuit respectively so as to accurately control the switching tube and reduce the noise influence of the switching tube on the power supply; the floating lining circuit is connected with the switching tube, so that the lining bias effect of the switching tube is reduced, bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switching tube is improved. According to the invention, the input control signal in the traditional M-LVDS drive circuit is processed through the secondary power supply, so that the interference of the switch signal on the power supply can be isolated. The built-in current backflow preventing structure replaces the substrate structure of the PMOS switching tube in the traditional M-LVDS circuit with an NMOS pair of a diode connection method, reduces the lining bias effect of the PMOS switching tube, avoids the potential communication between port signals and a power supply during cold backup, and prevents bus leakage.
Description
Technical Field
The invention relates to the technical field of integrated circuit I/O ports, in particular to an M-LVDS driving circuit capable of preventing bus leakage.
Background
Along with the development of signal transmission technologies such as LVDS (Low-Voltage Differential Signaling, low voltage differential signaling), M-LVDS (multi-point LVDS), LV-PECL (Low Voltage PosiTIve Emitter-coupled Logic), etc. in the technical field of integrated circuit I/O ports, the application of M-LVDS transceivers is becoming more and more widespread, in which a driving circuit is directly connected to various standard types of digital buses, and the I/O ports transmit and receive data to and from the buses.
In an M-LVDS transceiver, as shown in fig. 1, two pairs of PMOS switching transistors are usually turned on alternately, when one pair of the switching transistors is turned off, a high level of a driving signal input to a gate terminal of the switching transistors is VCC, and during a high-speed data transmission process, frequent inversion of the level on the switching transistors will cause noise interference to a power supply VCC.
In the earliest M-LVDS driver circuit, the substrate of the PMOS switching tube receives the highest potential VCC, and the circuit does not have a cold backup function, because when the power supply is powered down, the input voltage on the data bus is led to the power supply VCC through the drain-substrate parasitic diode of the PMOS, current is leaked from the bus to the VCC, and the power supply cannot be powered down normally. After improvement, as shown in fig. 1, the gate terminal of P0 and P0 is VCC, so as to ensure that P0 is in an off state during normal operation, the source terminal and the drain terminal of P0 are VCC, and the N-well substrate is the common substrate Vsub terminal of the switch tube, so that the parasitic diode of the source-drain-substrate of P0 is utilized to bias the N-well Vsub terminal, thereby effectively avoiding the potential connection of the port voltage to the power supply VCC through the parasitic effect of the PMOS switch tube. For this method, the voltage drop between the power supply VCC and the bias voltage Vsub will not exceed the turn-on voltage of the diode (typically VCC-0.3V), but in the M-LVDS driver, the common mode voltage of the bus port is typically VCC/2, and in this application scenario, the substrate voltage of the PMOS switching transistor will be higher, which will bring about a certain lining bias effect, so that the turn-on voltage of the PMOS switching transistor is increased, and the passing current capability is reduced in the same size.
Disclosure of Invention
The invention aims to provide an M-LVDS driving circuit for preventing bus leakage, so as to prevent bus current backflow and the interference of isolating switch signals on a power supply during cold backup and reduce the lining bias effect of a PMOS switching tube.
In order to solve the technical problems, the invention provides an M-LVDS driving circuit for preventing bus leakage, which comprises a secondary power supply, a main driving circuit connected with the secondary power supply, a switching tube and a floating liner circuit;
the secondary power supply comprises two stages of power supplies which are used for supplying power to the main driving circuit respectively so as to accurately control the switching tube and reduce the noise influence of the switching tube on the power supply;
the floating lining circuit is connected with the switching tube, so that the lining bias effect of the switching tube is reduced, bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switching tube is improved.
Optionally, the main driving circuit includes two first drivers and two second drivers;
the input ends of the two first drivers are connected with the signal CTRL, one first driver outputs a switch control signal D to the gate end of the PMOS switch tube MP1, and the other first driver outputs a switch control signalTo the gate end of the PMOS switch tube MP 2;
the input ends of the two second drivers are connected with signalsOne second driver outputs a switch control signal D to the gate end of the PMOS switch tube MP3, and the other second driver outputs a switch control signal +.>To the gate end of the PMOS switch tube MP4;
the PMOS switching tubes MP1 and MP3, MP2 and MP4 are respectively arranged on the control signals D and MP4Is alternately conducted under the drive of the PMOS switching tubes MP1 and MP2, and the load current flows in from the source ends of the PMOS switching tubes MP1 and MP2 and passes through an external load R L Then flows out from the drain ends of the PMOS switching tubes MP3 and MP4;
the substrates of the PMOS switching tubes MP 1-MP 4 are all connected with the output voltage Vsub of the floating liner circuit.
Optionally, the drain terminal of the PMOS switch tube MP1 and the source terminal of MP4 lead out the output port OUTA, the drain terminal of the PMOS switch tube MP2 and the source terminal of MP3 lead out the output port OUTB, and the external load R L Across the output ports OUTA and OUTB.
Optionally, the floating liner circuit comprises NMOS transistors MN1 and MN2, and resistors R1 and R2; the drain end of the NMOS tube MN1 is connected with a power supply VCC, the gate end is connected with the power supply VCC through a resistor R1, the source end is connected with the drain end of the NMOS tube MN2, the source end of the NMOS tube MN2 is grounded, and the gate end is grounded through the resistor R2;
the substrates of the NMOS tubes MN1 and MN2 are grounded, and the output voltage Vsub of the floating lining circuit is output from the source end of the NMOS tube MN1 and the drain end of the NMOS tube MN 2.
Optionally, the first driver includes PMOS transistors P1 to P6 and NMOS transistors N1 to N4;
the gate of the NMOS tube N1 is connected with a signal CTRL, the drain of the NMOS tube N1 is connected with the drain of the PMOS tube P1, and the source and the substrate are grounded; the gate of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are grounded; the gate of the NMOS tube N3 is connected with the signal EN, the drain of the NMOS tube N3 is connected with the drain of the PMOS tube P3, the source of the NMOS tube N3 is connected with the source of the PMOS tube P3, and the substrate is grounded; the gate of the NMOS tube N4 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P3 and the source end of the NMOS tube N3, the source is connected with the source end of the PMOS tube P6, and the substrate is grounded;
the gate end of the PMOS tube P1 is connected with the signal CTRL, the drain end is connected with the gate end of the NMOS tube N2 and the gate end of the PMOS tube P2 at the same time, and the source end and the substrate are connected with the level VDD1; the source end and the substrate of the PMOS tube P2 are connected with the level VDD1; gate termination signal of PMOS tube P3The drain end is connected with the drain end of the NMOS tube N2 and the drain end of the PMOS tube P2 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P4 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N3 and the source end of the PMOS tube P3 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P5 is connected with the output port OUTA/B, the drain end is connected with the source end of the NMOS tube N4 and the source end of the PMOS tube P6 at the same time, the source end is connected with the drain end of the PMOS tube P4, and the substrate is connected with the output voltage Vsub; the gate of the PMOS tube P6 is connected with a power supply VCC, the drain end outputs an output port OUTA/B, and the substrate is connected with an output voltage Vsub; the gate end of the PMOS tube P5 is connected with the drain end of the PMOS tube P6.
Optionally, the second driver comprises PMOS tubes P7-P12 and NMOS tubes N5-N8;
gate termination signal of NMOS transistor N5The drain end is connected with the drain end of the PMOS tube P7, and the source end and the substrate are connected withA ground; the gate of the NMOS tube N6 is connected with the gate end of the PMOS tube P8, the drain end of the NMOS tube N6 is connected with the drain end of the PMOS tube P8, and the source end and the substrate are grounded; the gate of the NMOS tube N7 is connected with the signal EN, the drain of the NMOS tube N7 is connected with the drain of the PMOS tube P9, the source of the NMOS tube N7 is connected with the source of the PMOS tube P9, and the substrate is grounded; the gate of the NMOS tube N8 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P9 and the source end of the NMOS tube N7, the source is connected with the source end of the PMOS tube P12, and the substrate is grounded;
gate termination signal of PMOS tube P7The drain end is connected with the gate end of the NMOS tube N6 and the gate end of the PMOS tube P8 at the same time, and the source end and the substrate are both connected with the level VDD1; the source end and the substrate of the PMOS tube P8 are connected with the level VDD2; gate termination signal of PMOS tube P9The drain end is connected with the drain end of the NMOS tube N6 and the drain end of the PMOS tube P8 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P10 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N7 and the source end of the PMOS tube P9 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P11 is connected with the output port OUTB/A, the drain end is connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12 at the same time, the source end is connected with the drain end of the PMOS tube P10, and the substrate is connected with the output voltage Vsub; the gate of the PMOS tube P12 is connected with a power supply VCC, the drain end outputs an output port OUTB/A, and the substrate is connected with an output voltage Vsub; the gate end of the PMOS tube P11 is connected with the drain end of the PMOS tube P12.
Optionally, the secondary power supply comprises an amplifier AMP, a capacitor C1, a resistor R3, PMOS tubes P13-P15 and an NMOS tube N9;
the gate end of the PMOS tube P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with the power VCC, and the drain end is connected with the first end of the resistor R3; the gate end and the drain end of the PMOS tube P14 are both connected with the negative input end of the amplifier AMP, and the substrate and the source end are both connected with the first end of the resistor R3; the gate end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are grounded;
the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP inputs an internal reference Vref1/Vref2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15.
The M-LVDS driving circuit capable of preventing bus leakage comprises a secondary power supply, a main driving circuit connected with the secondary power supply, a switching tube and a floating lining circuit; the secondary power supply comprises two stages of power supplies which are used for supplying power to the main driving circuit respectively so as to accurately control the switching tube and reduce the noise influence of the switching tube on the power supply; the floating lining circuit is connected with the switching tube, so that the lining bias effect of the switching tube is reduced, bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switching tube is improved. According to the invention, the input control signal in the traditional M-LVDS drive circuit is processed through the secondary power supply, so that the interference of the switch signal on the power supply can be isolated. The built-in current backflow preventing structure replaces the substrate structure of the PMOS switching tube in the traditional M-LVDS circuit with an NMOS pair of a diode connection method, reduces the lining bias effect of the PMOS switching tube, avoids the potential communication between port signals and a power supply during cold backup, and prevents bus leakage.
Drawings
FIG. 1 is a diagram of a conventional M-LVDS transceiver driver circuit;
FIG. 2 is a schematic diagram of an M-LVDS driving circuit for preventing bus leakage;
FIG. 3 is a diagram of a main driving circuit in an M-LVDS driving circuit for preventing bus leakage according to the present invention;
fig. 4 is a block diagram of a secondary power supply in the M-LVDS driving circuit for preventing bus leakage according to the present invention.
Detailed Description
The invention will now be described in further detail with reference to the drawings and examples. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides an M-LVDS driving circuit capable of preventing bus leakage, which is shown in figure 2 and comprises a floating lining circuit, a switching tube, a secondary power supply and a main driving circuit connected with the floating lining circuit. The secondary power supply comprises two stages of power supplies VDD1/VDD2 which are respectively used for supplying power to the main driving circuit, so that a switching tube can be accurately controlled, and noise of a switching signal on the power supply can be isolated; the floating lining circuit can reduce the lining bias effect of the switch tube and improve the working efficiency of the PMOS switch tube.
As shown in FIG. 2, the main driving circuit comprises two first drivers Driver1 and two second drivers Driver2, and LVTTL input signals with swing of 0-VCCThe two first drivers and the two second drivers are respectively input from the driver and are supplied by a secondary power supply, and the switch control signals with the swing of 0-VDD 1/VDD2 are output +.>The high level of the gate ends of the PMOS upper switching transistors MP1 and MP2 is VDD1, and the high level of the gate ends of the PMOS lower switching transistors MP3 and MP4 is VDD2. Because the source end voltage of the upper switching tube is necessarily larger than that of the lower switching tube, in order to maximally utilize the turn-off voltages of the upper switching tube and the lower switching tube, the voltage swing of the control signal of the PMOS switching tube can be reduced, and the secondary power supply meets the following conditions: VDD2<VDD1<VCC, the secondary power supply is used for isolating noise generated on the switch tube to the power supply.
As shown in FIG. 2, the PMOS switching tubes MP1 and MP3, MP2 and MP4 are connected with a control signal D,Is alternately conducted under the drive of the PMOS upper switch tubes MP1 and MP2, and the load current can flow in from the source ends of the PMOS upper switch tubes MP1 and MP2 and pass through an external load R L And then flows out from the drain ends of the PMOS lower switch tubes MP3 and MP 4. The output port OUTA is led out from the drain end of MP1 and the source end of MP4, the output port OUTB is led out from the drain end of MP2 and the source end of MP3, and the external load R L Then it is connected across the M-LVDS output ports OUTA and OUTB.
As shown in fig. 2, the floating liner circuit comprises NMOS transistors MN1 and MN2, and resistors R1 and R2; the drain end of the NMOS tube MN1 is connected with a power supply VCC, the gate end is connected with the power supply VCC through a resistor R1, the source end is connected with the drain end of the NMOS tube MN2, the source end of the NMOS tube MN2 is grounded, and the gate end is grounded through the resistor R2; the substrates of the NMOS tubes MN1 and MN2 are grounded, and the output voltage Vsub of the floating lining circuit is output from the source end of the NMOS tube MN1 and the drain end of the NMOS tube MN 2.
As shown in fig. 3, the first driver includes PMOS transistors P1 to P6 and NMOS transistors N1 to N4; the gate of the NMOS tube N1 is connected with a signal CTRL, the drain of the NMOS tube N1 is connected with the drain of the PMOS tube P1, and the source and the substrate are grounded; the gate of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are grounded; the gate of the NMOS tube N3 is connected with the signal EN, the drain of the NMOS tube N3 is connected with the drain of the PMOS tube P3, the source of the NMOS tube N3 is connected with the source of the PMOS tube P3, and the substrate is grounded; the gate of the NMOS tube N4 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P3 and the source end of the NMOS tube N3, the source is connected with the source end of the PMOS tube P6, and the substrate is grounded; the gate end of the PMOS tube P1 is connected with the signal CTRL, the drain end is connected with the gate end of the NMOS tube N2 and the gate end of the PMOS tube P2 at the same time, and the source end and the substrate are connected with the level VDD1; the source end and the substrate of the PMOS tube P2 are connected with the level VDD1; gate termination signal of PMOS tube P3The drain end is connected with the drain end of the NMOS tube N2 and the drain end of the PMOS tube P2 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P4 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N3 and the source end of the PMOS tube P3 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P5 is connected with the output port OUTA, the drain end is connected with the source end of the NMOS tube N4 and the source end of the PMOS tube P6 at the same time, the source end is connected with the drain end of the PMOS tube P4, and the substrate is connected with the output voltage Vsub; the gate of the PMOS transistor P6 is connected to the power supply VCC, the drain is connected to the output port OUTA (the drain is connected to the output port OUTB of the PMOS transistor P6 if the gate of the PMOS transistor P5 is connected to the output port OUTB), and the substrate is connected to the output voltage Vsub.
The second driver comprises PMOS (P7-P12) tubes and NMOS (N5-N8) tubes; gate termination signal of NMOS transistor N5The drain end is connected with the drain end of the PMOS tube P7, and the source end and the substrate are grounded; NMOS tubeThe gate of the N6 is connected with the gate end of the PMOS tube P8, the drain end of the PMOS tube P8 is connected with the drain end, and the source end and the substrate are grounded; the gate of the NMOS tube N7 is connected with the signal EN, the drain of the NMOS tube N7 is connected with the drain of the PMOS tube P9, the source of the NMOS tube N7 is connected with the source of the PMOS tube P9, and the substrate is grounded; the gate of the NMOS tube N8 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P9 and the source end of the NMOS tube N7, the source is connected with the source end of the PMOS tube P12, and the substrate is grounded; gate termination signal of PMOS tube P7>The drain end is connected with the gate end of the NMOS tube N6 and the gate end of the PMOS tube P8 at the same time, and the source end and the substrate are both connected with the level VDD1; the source end and the substrate of the PMOS tube P8 are connected with the level VDD2; gate termination signal of PMOS tube P9>The drain end is connected with the drain end of the NMOS tube N6 and the drain end of the PMOS tube P8 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P10 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N7 and the source end of the PMOS tube P9 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P11 is connected with the output port OUTB, the drain end is connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12 at the same time, the source end is connected with the drain end of the PMOS tube P10, and the substrate is connected with the output voltage Vsub; the gate of the PMOS transistor P12 is connected to the power source VCC, the drain is connected to the output port OUTB (if the gate of the PMOS transistor P11 is connected to the output port OUTA, the drain of the PMOS transistor P12 is connected to the output port OUTA), and the substrate is connected to the output voltage Vsub.
In fig. 3, if the gate end of the PMOS transistor P5 and the drain end of the PMOS transistor P6 are connected to the OUTA in common, the gate end of the PMOS transistor P11 and the drain end of the PMOS transistor P12 are connected to the OUTB in common; if the gate end of the PMOS transistor P5 and the drain end of the PMOS transistor P6 are connected to the OUTB in common, the gate end of the PMOS transistor P11 and the drain end of the PMOS transistor P12 are connected to the OUTA in common.
The LVTTL input signal CTRL is input to two-stage inverters in the first Driver1, which are respectively composed of P1, N1 and P2, N2, and are supplied with power from the secondary power supply VDD 1. Then, control signals pass through a transmission gate consisting of P3 and N3, the output of the transmission gate is connected to the drain ends of P4 and N4 and the source end of P5, the source ends of N4 and P6 are connected, the gate ends of the transmission gate are connected with VCC, an output port OUTA is led out from the gate end of P5 and the drain end of P6, and control signals with swing ranges from 0 to VDD1 are led out from the source ends of N4 and P6 and the drain end of P5, so that the switching tubes MP1 and MP2 on the PMOS are controlled to be turned on or off. The NMOS transistor N4 keeps a normally open state when operating normally, and when the power supply is turned off, the leakage path from the bus port OUTA to the power supply VCC can be effectively turned off, so that current backflow can be prevented.
As shown in fig. 3, the LVTTL input signalThe two-stage inverters are respectively composed of P7, N5, P8 and N6, wherein P7 is powered by a secondary power supply VDD1, P8 is powered by a secondary power supply VDD2, then control signals pass through a transmission gate composed of P9 and N7, the output of the transmission gate is connected to the drain ends of P10 and N8 and the source end of P11, the gate ends of N8 and P12 are connected with VCC, an output port OUTB is led out from the gate end of P11 and the drain end of P12, and control signals with swing ranges of 0-VDD 2 are led out from the source ends of N8 and P12 and the drain end of P11, so that the PMOS lower switching tubes MP3 and MP4 are controlled to be turned on or off. The NMOS transistor N8 keeps a normally open state when operating normally, and can effectively turn off a leakage path between the bus port OUTB and the power VCC when the power is turned off, so as to prevent current from flowing backward.
As shown in fig. 4, the secondary power supply includes an amplifier AMP, a capacitor C1, a resistor R3, PMOS transistors P13 to P15, and an NMOS transistor N9; the gate end of the PMOS tube P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with the power VCC, and the drain end is connected with the first end of the resistor R3; the gate end and the drain end of the PMOS tube P14 are both connected with the negative input end of the amplifier AMP, and the substrate and the source end are both connected with the first end of the resistor R3; the gate end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are grounded; the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP inputs an internal reference Vref1/Vref2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15. The secondary power supply adopts an internal light load LDO structure, an internal reference Vref1/Vref2 is input to the positive input end of the amplifier, the negative input end of the amplifier is connected to the drain end of a current source tube N9, the output end of the amplifier is connected to the gate end of a linear output PMOS tube P13, a diode-connected PMOS tube P14 is used as a load, the source end of the diode-connected PMOS tube P14 and the drain end of the output PMOS tube P13 are led out of a secondary power supply VDD1/VDD2, a capacitor C1 is connected with a resistor R3 in series and is bridged on two sides of the output of the amplifier and VDD1/VDD2, loop phase margin can be compensated, and the output end of the secondary power supply is connected with a load capacitor P15 of the PMOS connection.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. An M-LVDS driving circuit for preventing bus leakage is characterized by comprising a secondary power supply, a main driving circuit connected with the secondary power supply, a switching tube and a floating lining circuit;
the secondary power supply comprises two stages of power supplies which are used for supplying power to the main driving circuit respectively so as to accurately control the switching tube and reduce the noise influence of the switching tube on the power supply;
the floating lining circuit is connected with the switching tube, so that the lining bias effect of the switching tube is reduced, bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switching tube is improved;
the switching tubes comprise a PMOS switching tube MP1, a PMOS switching tube MP2, a PMOS switching tube MP3 and a PMOS switching tube MP4;
the main driving circuit comprises two first drivers and two second drivers;
the input ends of the two first drivers are connected with the signal CTRL, one first driver outputs a switch control signal D to the gate end of the PMOS switch tube MP1, and the other first driver outputs a switch control signalTo the gate end of the PMOS switch tube MP 2;
the input ends of the two second drivers are connected with signalsOne second driver outputs a switch control signal D to the gate end of the PMOS switch tube MP3, and the other second driver outputs a switch control signal +.>To the gate end of the PMOS switch tube MP4;
the PMOS switching tubes MP1 and MP3, MP2 and MP4 are respectively arranged on the control signals D and MP4Is alternately conducted under the drive of the PMOS switching tubes MP1 and MP2, and the load current flows in from the source ends of the PMOS switching tubes MP1 and MP2 and passes through an external load R L Then flows out from the drain ends of the PMOS switching tubes MP3 and MP4;
the substrates of the PMOS switching tubes MP 1-MP 4 are all connected with the output voltage Vsub of the floating liner circuit.
2. The bus leakage prevention M-LVDS driving circuit according to claim 1, wherein the drain of the PMOS switching transistor MP1 and the source of MP4 lead out an output port OUTA, the drain of the PMOS switching transistor MP2 and the source of MP3 lead out an output port OUTB, the external load R L Across the output ports OUTA and OUTB.
3. The bus leakage prevention M-LVDS driving circuit of claim 2, wherein the floating liner circuit comprises NMOS transistors MN1 and MN2, resistors R1 and R2; the drain end of the NMOS tube MN1 is connected with a power supply VCC, the gate end is connected with the power supply VCC through a resistor R1, the source end is connected with the drain end of the NMOS tube MN2, the source end of the NMOS tube MN2 is grounded, and the gate end is grounded through the resistor R2;
the substrates of the NMOS tubes MN1 and MN2 are grounded, and the output voltage Vsub of the floating lining circuit is output from the source end of the NMOS tube MN1 and the drain end of the NMOS tube MN 2.
4. The bus leakage prevention M-LVDS driving circuit of claim 3, wherein the first driver comprises PMOS transistors P1-P6 and NMOS transistors N1-N4;
the gate of the NMOS tube N1 is connected with a signal CTRL, the drain of the NMOS tube N1 is connected with the drain of the PMOS tube P1, and the source and the substrate are grounded; the gate of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are grounded; the gate of the NMOS tube N3 is connected with the signal EN, the drain of the NMOS tube N3 is connected with the drain of the PMOS tube P3, the source of the NMOS tube N3 is connected with the source of the PMOS tube P3, and the substrate is grounded; the gate of the NMOS tube N4 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P3 and the source end of the NMOS tube N3, the source is connected with the source end of the PMOS tube P6, and the substrate is grounded;
the gate end of the PMOS tube P1 is connected with the signal CTRL, the drain end is connected with the gate end of the NMOS tube N2 and the gate end of the PMOS tube P2 at the same time, and the source end and the substrate are connected with the level VDD1; the source end and the substrate of the PMOS tube P2 are connected with the level VDD1; gate termination signal of PMOS tube P3The drain end is connected with the drain end of the NMOS tube N2 and the drain end of the PMOS tube P2 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P4 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N3 and the source end of the PMOS tube P3 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P5 is connected with the output port OUTA/B, the drain end is connected with the source end of the NMOS tube N4 and the source end of the PMOS tube P6 at the same time, the source end is connected with the drain end of the PMOS tube P4, and the substrate is connected with the output voltage Vsub; the gate of the PMOS tube P6 is connected with a power supply VCC, the drain end outputs an output port OUTA/B, and the substrate is connected with an output voltage Vsub; the gate end of the PMOS tube P5 is connected with the drain end of the PMOS tube P6.
5. The bus leakage prevention M-LVDS driving circuit of claim 4, wherein the second driver comprises PMOS transistors P7-P12 and NMOS transistors N5-N8;
gate termination signal of NMOS transistor N5The drain end is connected with the drain end of the PMOS tube P7, and the source end and the substrate are grounded; the gate of the NMOS tube N6 is connected with the gate end of the PMOS tube P8, the drain end of the PMOS tube P8 is connected with the drain end, and the source end and the substrate are bothGrounding; the gate of the NMOS tube N7 is connected with the signal EN, the drain of the NMOS tube N7 is connected with the drain of the PMOS tube P9, the source of the NMOS tube N7 is connected with the source of the PMOS tube P9, and the substrate is grounded; the gate of the NMOS tube N8 is connected with a power supply VCC, the drain is connected with the source end of the PMOS tube P9 and the source end of the NMOS tube N7, the source is connected with the source end of the PMOS tube P12, and the substrate is grounded;
gate termination signal of PMOS tube P7The drain end is connected with the gate end of the NMOS tube N6 and the gate end of the PMOS tube P8 at the same time, and the source end and the substrate are both connected with the level VDD1; the source end and the substrate of the PMOS tube P8 are connected with the level VDD2; gate termination signal of PMOS tube P9>The drain end is connected with the drain end of the NMOS tube N6 and the drain end of the PMOS tube P8 at the same time, and the substrate is connected with the output voltage Vsub; the gate end of the PMOS tube P10 is connected with a signal EN, the drain end is connected with the source end of the NMOS tube N7 and the source end of the PMOS tube P9 at the same time, and the source end and the substrate are connected with a power supply VCC; the gate end of the PMOS tube P11 is connected with the output port OUTB/A, the drain end is connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12 at the same time, the source end is connected with the drain end of the PMOS tube P10, and the substrate is connected with the output voltage Vsub; the gate of the PMOS tube P12 is connected with a power supply VCC, the drain end outputs an output port OUTB/A, and the substrate is connected with an output voltage Vsub; the gate end of the PMOS tube P11 is connected with the drain end of the PMOS tube P12.
6. The bus leakage prevention M-LVDS driving circuit of claim 5, wherein the secondary power supply comprises an amplifier AMP, a capacitor C1, a resistor R3, PMOS transistors P13-P15, and an NMOS transistor N9;
the gate end of the PMOS tube P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with the power VCC, and the drain end is connected with the first end of the resistor R3; the gate end and the drain end of the PMOS tube P14 are both connected with the negative input end of the amplifier AMP, and the substrate and the source end are both connected with the first end of the resistor R3; the gate end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are grounded;
the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP inputs an internal reference Vref1/Vref2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15.
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| WO2015170845A1 (en) * | 2014-05-08 | 2015-11-12 | (주) 픽셀플러스 | Low-voltage differential signalling transmitter |
| CN105207661A (en) * | 2015-09-18 | 2015-12-30 | 中国科学院微电子研究所 | Multi-point low voltage differential signal transmitter |
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| US7843235B2 (en) * | 2006-12-05 | 2010-11-30 | Integrated Device Technology, Inc. | Output slew rate control in low voltage differential signal (LVDS) driver |
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