CN114268080A - M-LVDS drive circuit for preventing bus electric leakage - Google Patents
M-LVDS drive circuit for preventing bus electric leakage Download PDFInfo
- Publication number
- CN114268080A CN114268080A CN202111552556.8A CN202111552556A CN114268080A CN 114268080 A CN114268080 A CN 114268080A CN 202111552556 A CN202111552556 A CN 202111552556A CN 114268080 A CN114268080 A CN 114268080A
- Authority
- CN
- China
- Prior art keywords
- pmos
- tube
- drain
- source
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 230000000694 effects Effects 0.000 claims abstract description 9
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 claims description 9
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000002265 prevention Effects 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000011664 signaling Effects 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Abstract
The invention discloses an M-LVDS drive circuit for preventing bus electric leakage, belonging to the field of integrated circuit I/O ports, comprising a secondary power supply, a main drive circuit connected with the secondary power supply, a switching tube and a floating liner circuit; the secondary power supply comprises two stages of power supplies which respectively supply power to the main driving circuit so as to accurately control the switch tube and reduce the noise influence of the switch tube on the power supply; the floating liner circuit is connected with the switch tube, so that the liner bias effect of the switch tube is reduced, the bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switch tube is improved. The input control signal in the traditional M-LVDS drive circuit is processed by the secondary power supply, so that the interference of the switch signal to the power supply can be isolated. A built-in anti-current backflow structure replaces the substrate structure of a PMOS (P-channel metal oxide semiconductor) switching tube in the traditional M-LVDS (differential voltage differential signaling) circuit with a diode-connected NMOS (N-channel metal oxide semiconductor) pair, so that the substrate bias effect of the PMOS switching tube is reduced, the potential connection between a port signal and a power supply during cold backup is avoided, and the bus is prevented from electric leakage.
Description
Technical Field
The invention relates to the technical field of integrated circuit I/O ports, in particular to an M-LVDS drive circuit for preventing bus leakage.
Background
With the development of signal transmission technologies such as LVDS (Low-Voltage Differential Signaling), M-LVDS (multi-drop LVDS), LV-PECL (Low-Voltage PosiTIve Emitter-coupled Logic) and the like in the technical field of I/O ports of integrated circuits, M-LVDS transceivers are also more and more widely applied, wherein a driving circuit is directly connected to digital buses of various standard types, and the I/O ports transmit and receive data to and from the buses.
In an M-LVDS transceiver, a typical driving circuit structure is generally as shown in fig. 1, two pairs of PMOS switching tubes are alternately turned on, when one pair of the switching tubes is turned off, a high level of a driving signal input to a gate terminal is VCC, and during high-speed data transmission, frequent inversion of the level on the switching tubes will bring noise interference to a power supply VCC.
In the earliest M-LVDS driver circuit, the substrate of the PMOS switch tube would be connected to the highest potential VCC, and such a circuit does not have a cold backup function, because when the power supply is powered down, the input voltage on the data bus would be sneak through the PMOS drain-substrate parasitic diode to the power supply VCC, and current would leak from the bus to the VCC, which also results in the power supply failing to normally power down. Later, through improvement, as shown in fig. 1, the gate terminal of P0 and the gate terminal of P0 are VCC, so that it is ensured that the P0 is in an off state during normal operation, the source terminal and the drain terminal of P0 are VCC, and the N-well substrate thereof is the common substrate Vsub terminal of the switch tube, so that the source-drain-substrate parasitic diode of P0 is used to bias the N-well Vsub terminal, thereby effectively avoiding the potential connection of the port voltage to the power supply VCC through the parasitic effect of the PMOS switch tube. In the method, the voltage drop between the power source VCC and the bias voltage Vsub will not exceed the turn-on voltage (normally VCC-0.3V) of the diode, while in the M-LVDS driver, the common-mode value of the voltage of the bus port is normally about VCC/2, and in this application scenario, the substrate voltage of the PMOS switching tube will be higher, which will bring about a certain substrate bias effect, so that the turn-on voltage of the PMOS switching tube is increased, and the current passing capability is reduced under the same size.
Disclosure of Invention
The invention aims to provide an M-LVDS drive circuit for preventing bus leakage so as to prevent bus current from flowing backwards and isolate interference of switch signals to a power supply during cold backup and reduce the substrate bias effect of a PMOS (P-channel metal oxide semiconductor) switch tube.
In order to solve the technical problem, the invention provides an M-LVDS drive circuit for preventing bus leakage, which comprises a secondary power supply, a main drive circuit connected with the secondary power supply, a switching tube and a floating liner circuit, wherein the switching tube is connected with the main drive circuit;
the secondary power supply comprises two stages of power supplies which respectively supply power to the main driving circuit so as to accurately control the switch tube and reduce the noise influence of the switch tube on the power supply;
the floating liner circuit is connected with the switch tube, so that the liner bias effect of the switch tube is reduced, the bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switch tube is improved.
Optionally, the main driving circuit includes two first drivers and two second drivers;
the input ends of the two first drivers are connected with a signal CTRL, one first driver outputs a switch control signal D to the grid end of a PMOS switch tube MP1, and the other first driver outputs a switch control signal
To the gate terminal of the PMOS switch MP 2;
the input ends of the two second drivers are connected with signals
One of the second drivers outputs a switch control signal D to the gate of the PMOS switch tube MP3, and the other second driver outputs a switch control signal
To the gate terminal of the PMOS switch MP 4;
the PMOS switching tubes MP1 and MP3, MP2 and MP4 are respectively controlled by control signals D and MP3
Is driven to be alternately conducted, the load current flows from the source ends of the PMOS switching tubes MP1 and MP2 and passes through the external load RLThen flows out from the drain ends of the PMOS switching tubes MP3 and MP 4;
the substrates of the PMOS switching tubes MP 1-MP 4 are all connected with the output voltage Vsub of the floating circuit.
Optionally, the drain terminal of the PMOS switch tube MP1 and the source terminal of MP4 lead out the output port OUTA, the drain terminal of the PMOS switch tube MP2 and the source terminal of MP3 lead out the output port OUTB, and the external load RLAcross the output ports OUTA and OUTB.
Optionally, the floating circuit includes NMOS transistors MN1 and MN2, and resistors R1 and R2; the drain terminal of the NMOS tube MN1 is connected with a power supply VCC, the gate terminal is connected with the power supply VCC through a resistor R1, the source terminal is connected with the drain terminal of the NMOS tube MN2, the source terminal of the NMOS tube MN2 is grounded, and the gate terminal is grounded through a resistor R2;
the substrates of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, and the output voltage Vsub of the floating circuit is connected from the source terminal of the NMOS transistor MN1 and the drain terminal of the NMOS transistor MN 2.
Optionally, the first driver includes PMOS transistors P1-P6 and NMOS transistors N1-N4;
the grid end of the NMOS tube N1 is connected with a signal CTRL, the drain end of the NMOS tube N1 is connected with the drain end of the PMOS tube P1, and the source end and the substrate are both grounded; the gate end of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N3 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P3, the source end is connected with the source end of a PMOS transistor P3, and the substrate is grounded; the grid end of the NMOS tube N4 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P3 and the source end of an NMOS tube N3, the source end is connected with the source end of a PMOS tube P6, and the substrate is grounded;
the grid end of the PMOS tube P1 is connected with a signal CTRL, the drain end of the PMOS tube P1 is simultaneously connected with the grid end of the NMOS tube N2 and the grid end of the PMOS tube P2, and the source end and the substrate are both connected with a level VDD 1; the source end and the substrate of the PMOS tube P2 are connected with a level VDD 1; grid terminal signal of PMOS pipe P3
With drain terminals connected simultaneously to NMOS transistor N2The drain terminal of the PMOS tube P2 and the drain terminal of the PMOS tube P2, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS tube P4 is connected with a signal EN, the drain end of the PMOS tube P4 is simultaneously connected with the source end of an NMOS tube N3 and the source end of a PMOS tube P3, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS tube P5 is connected with an output port OUTA/B, the drain end of the PMOS tube P5 is simultaneously connected with the source end of an NMOS tube N4 and the source end of a PMOS tube P6, the source end of the PMOS tube P4 is connected with the drain end of the PMOS tube, and the substrate is connected with an output voltage Vsub; the grid end of the PMOS pipe P6 is connected with a power supply VCC, the drain end is connected with an output port OUTA/B, and the substrate is connected with an output voltage Vsub; the grid end of the PMOS pipe P5 is connected with the drain end of the PMOS pipe P6.
Optionally, the second driver includes PMOS transistors P7-P12 and NMOS transistors N5-N8;
grid terminal signal of NMOS transistor N5
The drain end is connected with the drain end of the PMOS pipe P7, and the source end and the substrate are both grounded; the gate end of the NMOS tube N6 is connected with the gate end of the PMOS tube P8, the drain end of the NMOS tube N6 is connected with the drain end of the PMOS tube P8, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N7 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P9, the source end is connected with the source end of a PMOS transistor P9, and the substrate is grounded; the grid end of the NMOS tube N8 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P9 and the source end of an NMOS tube N7, the source end is connected with the source end of a PMOS tube P12, and the substrate is grounded;
grid terminal signal of PMOS pipe P7
The drain terminal is simultaneously connected with the gate terminal of the NMOS transistor N6 and the gate terminal of the PMOS transistor P8, and the source terminal and the substrate are both connected with the level VDD 1; the source end and the substrate of the PMOS tube P8 are connected with a level VDD 2; grid terminal signal of PMOS pipe P9
The drain end is simultaneously connected with the drain end of the NMOS transistor N6 and the drain end of the PMOS transistor P8, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS tube P10 is connected with a signal EN, the drain end of the PMOS tube P10 is simultaneously connected with the source end of an NMOS tube N7 and the source end of a PMOS tube P9, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS tube P11 is connected with the output port OUTB/A, the drain end is simultaneously connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12, the source end is connected with the drain end of the PMOS tube P10, and the substrate is connected with the output powerA voltage Vsub; the grid end of the PMOS pipe P12 is connected with a power supply VCC, the drain end is connected with an output port OUTB/A, and the substrate is connected with an output voltage Vsub; the grid end of the PMOS pipe P11 is connected with the drain end of the PMOS pipe P12.
Optionally, the secondary power supply includes an amplifier AMP, a capacitor C1, a resistor R3, PMOS transistors P13 to P15, and an NMOS transistor N9;
the grid end of the PMOS pipe P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with a power supply VCC, and the drain end is connected with the first end of a resistor R3; the grid end and the drain end of the PMOS pipe P14 are both connected with the negative input end of the amplifier AMP, and the substrate end and the source end are both connected with the first end of the resistor R3; the grid end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are all grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are both grounded;
the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP is input with internal reference Vref1/Vref 2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15.
The M-LVDS drive circuit for preventing bus leakage comprises a secondary power supply, a main drive circuit connected with the secondary power supply, a switching tube and a floating liner circuit; the secondary power supply comprises two stages of power supplies which respectively supply power to the main driving circuit so as to accurately control the switch tube and reduce the noise influence of the switch tube on the power supply; the floating liner circuit is connected with the switch tube, so that the liner bias effect of the switch tube is reduced, the bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switch tube is improved. The input control signal in the traditional M-LVDS drive circuit is processed by the secondary power supply, so that the interference of the switch signal to the power supply can be isolated. A built-in anti-current backflow structure replaces the substrate structure of a PMOS (P-channel metal oxide semiconductor) switching tube in the traditional M-LVDS (differential voltage differential signaling) circuit with a diode-connected NMOS (N-channel metal oxide semiconductor) pair, so that the substrate bias effect of the PMOS switching tube is reduced, the potential connection between a port signal and a power supply during cold backup is avoided, and the bus is prevented from electric leakage.
Drawings
FIG. 1 is a diagram of a conventional M-LVDS transceiver driving circuit;
FIG. 2 is a schematic diagram of a bus leakage prevention M-LVDS driving circuit according to the present invention;
FIG. 3 is a main driving circuit diagram of the M-LVDS driving circuit for preventing bus leakage according to the present invention;
fig. 4 is a structural diagram of a secondary power supply in the bus leakage prevention M-LVDS driving circuit provided in the present invention.
Detailed Description
The invention will be described in more detail with reference to the following description of the preferred embodiments and the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides an M-LVDS drive circuit for preventing bus leakage, which has a structure shown in FIG. 2 and comprises a floating liner circuit, a switching tube, a secondary power supply and a main drive circuit connected with the secondary power supply. The secondary power supply comprises a two-stage power supply VDD1/VDD2 which respectively supplies power to the main driving circuit, can accurately control the switching tube and can isolate noise of the switching signal to the power supply; the floating liner circuit can reduce the liner bias effect of the switch tube and improve the working efficiency of the PMOS switch tube.
As shown in FIG. 2, the main driving circuit includes two first drivers 1 and two second drivers 2, and LVTTL input signal with swing of 0-VCC
The switch control signals are respectively input from two first drivers and two second drivers of the driver, are supplied by a secondary power supply and have output swing ranges of 0-VDD 1/VDD2
The high level of the gate terminals of the PMOS upper switching tubes MP1 and MP2 is VDD1, and the high level of the gate terminals of the PMOS lower switching tubes MP3 and MP4 is VDD 2. Because the source end voltage of the upper switch tube is certainly greater than that of the lower switch tube, the turn-off voltage of the upper switch tube and the lower switch tube is utilized to the maximum extent, and therefore the control of the PMOS switch tube can be reducedThe voltage swing of the control signal, the secondary power supply satisfies: VDD2<VDD1<VCC, the secondary power supply can also isolate the noise generated on the switch tube to the power supply.
As shown in FIG. 2, PMOS switching tubes MP1 and MP3, MP2 and MP4 are under the control signal D,
Can flow in from the source ends of the PMOS upper switch tubes MP1 and MP2 and pass through the external load RLAnd then flows out from the drain ends of the PMOS lower switching tubes MP3 and MP 4. The output port OUTA is led out from the drain terminal of MP1 and the source terminal of MP4, the output port OUTB is led out from the drain terminal of MP2 and the source terminal of MP3, and the external load RLThen across the M-LVDS output ports OUTA and OUTB.
As shown in fig. 2, the floating circuit includes NMOS transistors MN1 and MN2, resistors R1 and R2; the drain terminal of the NMOS tube MN1 is connected with a power supply VCC, the gate terminal is connected with the power supply VCC through a resistor R1, the source terminal is connected with the drain terminal of the NMOS tube MN2, the source terminal of the NMOS tube MN2 is grounded, and the gate terminal is grounded through a resistor R2; the substrates of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, and the output voltage Vsub of the floating circuit is connected from the source terminal of the NMOS transistor MN1 and the drain terminal of the NMOS transistor MN 2.
As shown in fig. 3, the first driver includes PMOS transistors P1-P6 and NMOS transistors N1-N4; the grid end of the NMOS tube N1 is connected with a signal CTRL, the drain end of the NMOS tube N1 is connected with the drain end of the PMOS tube P1, and the source end and the substrate are both grounded; the gate end of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N3 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P3, the source end is connected with the source end of a PMOS transistor P3, and the substrate is grounded; the grid end of the NMOS tube N4 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P3 and the source end of an NMOS tube N3, the source end is connected with the source end of a PMOS tube P6, and the substrate is grounded; the grid end of the PMOS tube P1 is connected with a signal CTRL, the drain end of the PMOS tube P1 is simultaneously connected with the grid end of the NMOS tube N2 and the grid end of the PMOS tube P2, and the source end and the substrate are both connected with a level VDD 1; the source end and the substrate of the PMOS tube P2 are connected with a level VDD 1; grid terminal signal of PMOS pipe P3
Drain terminal simultaneous connectionThe drain terminal of the NMOS transistor N2 and the drain terminal of the PMOS transistor P2, and the substrate is connected with an output voltage Vsub; the grid end of the PMOS tube P4 is connected with a signal EN, the drain end of the PMOS tube P4 is simultaneously connected with the source end of an NMOS tube N3 and the source end of a PMOS tube P3, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS tube P5 is connected with an output port OUTA, the drain end of the PMOS tube P5 is simultaneously connected with the source end of an NMOS tube N4 and the source end of a PMOS tube P6, the source end of the PMOS tube P4 is connected with the drain end of the PMOS tube, and the substrate is connected with an output voltage Vsub; the gate of the PMOS transistor P6 is connected to the power source VCC, the drain output port OUTA (if the gate of the PMOS transistor P5 is connected to the output port OUTB, the drain output port OUTB of the PMOS transistor P6), and the substrate is connected to the output voltage Vsub.
The second driver comprises PMOS tubes P7-P12 and NMOS tubes N5-N8; grid terminal signal of NMOS transistor N5
The drain end is connected with the drain end of the PMOS pipe P7, and the source end and the substrate are both grounded; the gate end of the NMOS tube N6 is connected with the gate end of the PMOS tube P8, the drain end of the NMOS tube N6 is connected with the drain end of the PMOS tube P8, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N7 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P9, the source end is connected with the source end of a PMOS transistor P9, and the substrate is grounded; the grid end of the NMOS tube N8 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P9 and the source end of an NMOS tube N7, the source end is connected with the source end of a PMOS tube P12, and the substrate is grounded; grid terminal signal of PMOS pipe P7
The drain terminal is simultaneously connected with the gate terminal of the NMOS transistor N6 and the gate terminal of the PMOS transistor P8, and the source terminal and the substrate are both connected with the level VDD 1; the source end and the substrate of the PMOS tube P8 are connected with a level VDD 2; grid terminal signal of PMOS pipe P9
The drain end is simultaneously connected with the drain end of the NMOS transistor N6 and the drain end of the PMOS transistor P8, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS tube P10 is connected with a signal EN, the drain end of the PMOS tube P10 is simultaneously connected with the source end of an NMOS tube N7 and the source end of a PMOS tube P9, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS tube P11 is connected with the output port OUTB, the drain end of the PMOS tube P11 is simultaneously connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12, the source end of the PMOS tube P10 is connected with the drain end of the PMOS tube, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS pipe P12 is connected with a power supply VCC, and the drain end outputsThe port OUTB (if the gate of the PMOS transistor P11 is connected to the output port OUTA, the drain of the PMOS transistor P12 is connected to the output port OUTA) and the substrate is connected to the output voltage Vsub.
In fig. 3, if the gate terminal of the PMOS transistor P5 and the drain terminal of the PMOS transistor P6 are commonly connected to OUTA, the gate terminal of the PMOS transistor P11 and the drain terminal of the PMOS transistor P12 are commonly connected to OUTB; if the gate terminal of the PMOS transistor P5 and the drain terminal of the PMOS transistor P6 are connected to OUTB, the gate terminal of the PMOS transistor P11 and the drain terminal of the PMOS transistor P12 are connected to OUTA.
The LVTTL input signal CTRL is input to two-stage inverters in the first Driver1, which are respectively composed of P1, N1, P2, and N2, and are powered by the secondary power supply VDD 1. Then the control signal passes through a transmission gate composed of P3 and N3, the output of the transmission gate is connected to the drain terminals of P4 and N4 and the source terminal of P5, the source terminals of N4 and P6 are connected, the gate terminals are all connected with VCC, an output port OUTA is led out from the gate terminal of P5 and the drain terminal of P6, a control signal with the swing amplitude of 0-VDD 1 is led out from the source terminals of N4 and P6 and the drain terminal of P5, and the opening or closing of switch tubes MP1 and MP2 on the PMOS is controlled. Wherein, NMOS pipe N4 normal during operation keeps normally open state, and when the power supply lost power, can effectively turn off the electric leakage route between bus port OUTA to the power VCC, can prevent that the electric current from flowing backward.
As shown in fig. 3, LVTTL input signal
The two-stage inverter is input into the second Driver2 and respectively comprises P7, N5, P8 and N6, P7 is powered by a secondary power supply VDD1, P8 is powered by a secondary power supply VDD2, then a control signal passes through a transmission gate consisting of P9 and N7, the output of the transmission gate is connected to the drain terminals of P10 and N8 and the source terminal of P11, the source terminals of N8 and P12 are connected, the gate terminals of the N8 and P12 are all connected with VCC, an output port OUTB is led out from the gate terminal of P11 and the drain terminal of P12, a control signal with the swing of 0-VDD 2 is led out from the source terminals of N8 and P12 and the drain terminal of P11, and the on or off of PMOS lower switch tubes MP3 and MP4 is controlled. Wherein, NMOS pipe N8 keeps normally open state when normal during operation, and when the power supply loses electricity, can effectively turn off the electric leakage route between bus port OUTB to power VCC, can prevent the electricityAnd (4) flowing backwards.
As shown in fig. 4, the secondary power supply includes an amplifier AMP, a capacitor C1, a resistor R3, PMOS transistors P13 to P15, and an NMOS transistor N9; the grid end of the PMOS pipe P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with a power supply VCC, and the drain end is connected with the first end of a resistor R3; the grid end and the drain end of the PMOS pipe P14 are both connected with the negative input end of the amplifier AMP, and the substrate end and the source end are both connected with the first end of the resistor R3; the grid end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are all grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are both grounded; the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP is input with internal reference Vref1/Vref 2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15. The secondary power supply adopts an internal light load LDO structure, an internal reference Vref1/Vref2 is input to the positive input end of an amplifier, the negative input end of the amplifier is connected to the drain end of a current source tube N9, the output end of the amplifier is connected to the gate end of a linear output PMOS tube P13, a diode-connected PMOS tube P14 is used as a load, the source end of the diode-connected PMOS tube P14 and the drain end of an output PMOS tube P13 lead out a secondary power supply VDD1/VDD2, a capacitor C1 is connected with a resistor R3 in series and bridged at two sides of the output of the amplifier and VDD1/VDD2, the phase margin of a loop can be compensated, and the output end of the secondary power supply is connected with a load capacitor P15 of the PMOS connection method.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. The M-LVDS drive circuit for preventing bus leakage is characterized by comprising a secondary power supply, a main drive circuit connected with the secondary power supply, a switching tube and a floating liner circuit;
the secondary power supply comprises two stages of power supplies which respectively supply power to the main driving circuit so as to accurately control the switch tube and reduce the noise influence of the switch tube on the power supply;
the floating liner circuit is connected with the switch tube, so that the liner bias effect of the switch tube is reduced, the bus current is effectively prevented from flowing backwards to the power supply when the power supply is powered off, and the working efficiency of the switch tube is improved.
2. The bus leakage prevention M-LVDS driver circuit according to claim 1, wherein the master driver circuit includes two first drivers and two second drivers;
the input ends of the two first drivers are connected with a signal CTRL, one first driver outputs a switch control signal D to the grid end of a PMOS switch tube MP1, and the other first driver outputs a switch control signal
To the gate terminal of the PMOS switch MP 2;
the input ends of the two second drivers are connected with signals
One of the second drivers outputs a switch control signal D to the gate of the PMOS switch tube MP3, and the other second driver outputs a switch control signal
To the gate terminal of the PMOS switch MP 4;
the PMOS switching tubes MP1 and MP3, MP2 and MP4 are respectively controlled by control signals D and MP3
Is driven to be alternately conducted, the load current flows from the source ends of the PMOS switching tubes MP1 and MP2 and passes through the external load RLThen flows out from the drain ends of the PMOS switching tubes MP3 and MP 4;
the substrates of the PMOS switching tubes MP 1-MP 4 are all connected with the output voltage Vsub of the floating circuit.
3. The bus leakage prevention M-LVDS driver circuit as claimed in claim 2, wherein the drain terminal of the PMOS switch MP1 and the source terminal of MP4 lead out the output port OUTA, the PMOS switch MP1 and the source terminal of the PMOS switch MP4 are connected to the output port OUTAThe drain terminal of the switching tube MP2 and the source terminal of the MP3 lead out the output port OUTB, and the external load RLAcross the output ports OUTA and OUTB.
4. The bus leakage prevention M-LVDS drive circuit according to claim 3, wherein the floating-liner circuit includes NMOS transistors MN1 and MN2, resistors R1 and R2; the drain terminal of the NMOS tube MN1 is connected with a power supply VCC, the gate terminal is connected with the power supply VCC through a resistor R1, the source terminal is connected with the drain terminal of the NMOS tube MN2, the source terminal of the NMOS tube MN2 is grounded, and the gate terminal is grounded through a resistor R2;
the substrates of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded, and the output voltage Vsub of the floating circuit is connected from the source terminal of the NMOS transistor MN1 and the drain terminal of the NMOS transistor MN 2.
5. The bus leakage prevention M-LVDS drive circuit of claim 4, wherein the first driver comprises PMOS transistors P1-P6 and NMOS transistors N1-N4;
the grid end of the NMOS tube N1 is connected with a signal CTRL, the drain end of the NMOS tube N1 is connected with the drain end of the PMOS tube P1, and the source end and the substrate are both grounded; the gate end of the NMOS tube N2 is connected with the gate end of the PMOS tube P2, the drain end of the NMOS tube N2 is connected with the drain end of the PMOS tube P2, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N3 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P3, the source end is connected with the source end of a PMOS transistor P3, and the substrate is grounded; the grid end of the NMOS tube N4 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P3 and the source end of an NMOS tube N3, the source end is connected with the source end of a PMOS tube P6, and the substrate is grounded;
the grid end of the PMOS tube P1 is connected with a signal CTRL, the drain end of the PMOS tube P1 is simultaneously connected with the grid end of the NMOS tube N2 and the grid end of the PMOS tube P2, and the source end and the substrate are both connected with a level VDD 1; the source end and the substrate of the PMOS tube P2 are connected with a level VDD 1; grid terminal signal of PMOS pipe P3
The drain end is simultaneously connected with the drain end of the NMOS transistor N2 and the drain end of the PMOS transistor P2, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS tube P4 is connected with a signal EN, the drain end of the PMOS tube P4 is simultaneously connected with the source end of an NMOS tube N3 and the source end of a PMOS tube P3, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS pipe P5 is connected with the output port OUTA/B, and the drain end is simultaneously connectedThe source end of the NMOS transistor N4 and the source end of the PMOS transistor P6 are connected, the source end is connected with the drain end of the PMOS transistor P4, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS pipe P6 is connected with a power supply VCC, the drain end is connected with an output port OUTA/B, and the substrate is connected with an output voltage Vsub; the grid end of the PMOS pipe P5 is connected with the drain end of the PMOS pipe P6.
6. The bus leakage prevention M-LVDS driver circuit according to claim 5, wherein the second driver includes PMOS transistors P7-P12 and NMOS transistors N5-N8;
grid terminal signal of NMOS transistor N5
The drain end is connected with the drain end of the PMOS pipe P7, and the source end and the substrate are both grounded; the gate end of the NMOS tube N6 is connected with the gate end of the PMOS tube P8, the drain end of the NMOS tube N6 is connected with the drain end of the PMOS tube P8, and the source end and the substrate are both grounded; the gate end of the NMOS transistor N7 is connected with a signal EN, the drain end is connected with the drain end of a PMOS transistor P9, the source end is connected with the source end of a PMOS transistor P9, and the substrate is grounded; the grid end of the NMOS tube N8 is connected with a power supply VCC, the drain end is connected with the source end of a PMOS tube P9 and the source end of an NMOS tube N7, the source end is connected with the source end of a PMOS tube P12, and the substrate is grounded;
grid terminal signal of PMOS pipe P7
The drain terminal is simultaneously connected with the gate terminal of the NMOS transistor N6 and the gate terminal of the PMOS transistor P8, and the source terminal and the substrate are both connected with the level VDD 1; the source end and the substrate of the PMOS tube P8 are connected with a level VDD 2; grid terminal signal of PMOS pipe P9
The drain end is simultaneously connected with the drain end of the NMOS transistor N6 and the drain end of the PMOS transistor P8, and the substrate is connected with the output voltage Vsub; the grid end of the PMOS tube P10 is connected with a signal EN, the drain end of the PMOS tube P10 is simultaneously connected with the source end of an NMOS tube N7 and the source end of a PMOS tube P9, and the source end and the substrate are both connected with a power supply VCC; the grid end of the PMOS tube P11 is connected with the output port OUTB/A, the drain end of the PMOS tube P11 is simultaneously connected with the source end of the NMOS tube N8 and the source end of the PMOS tube P12, the source end of the PMOS tube P10 is connected with the drain end of the PMOS tube, and the substrate is connected with the output voltage Vsub; the grid of the PMOS tube P12 is connected with the power supply VCC, the drain terminal is connected with the output port OUTB/A, and the substrate is connected with the outputA voltage Vsub; the grid end of the PMOS pipe P11 is connected with the drain end of the PMOS pipe P12.
7. The bus leakage prevention M-LVDS drive circuit according to claim 6, wherein the secondary power supply comprises an amplifier AMP, a capacitor C1, a resistor R3, PMOS transistors P13-P15 and an NMOS transistor N9;
the grid end of the PMOS pipe P13 is connected with the output end of the amplifier AMP, the substrate and the source end are both connected with a power supply VCC, and the drain end is connected with the first end of a resistor R3; the grid end and the drain end of the PMOS pipe P14 are both connected with the negative input end of the amplifier AMP, and the substrate end and the source end are both connected with the first end of the resistor R3; the grid end of the PMOS tube P15 is connected with the first end of the resistor R3, and the substrate, the drain end and the source end are all grounded; the drain end of the NMOS tube N9 is connected with the negative input end of the amplifier AMP, the gate end is connected with Vbias1/Vbias2, and the source end and the substrate are both grounded;
the second end of the resistor R3 is connected with the output end of the amplifier AMP through a capacitor C1, and the positive input end of the amplifier AMP is input with internal reference Vref1/Vref 2; the power supply VDD1/VDD2 is led out from the gate end of the PMOS tube P15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111552556.8A CN114268080B (en) | 2021-12-17 | 2021-12-17 | M-LVDS drive circuit capable of preventing bus leakage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111552556.8A CN114268080B (en) | 2021-12-17 | 2021-12-17 | M-LVDS drive circuit capable of preventing bus leakage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114268080A true CN114268080A (en) | 2022-04-01 |
| CN114268080B CN114268080B (en) | 2024-03-26 |
Family
ID=80827733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111552556.8A Active CN114268080B (en) | 2021-12-17 | 2021-12-17 | M-LVDS drive circuit capable of preventing bus leakage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114268080B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155254A (en) * | 2023-04-18 | 2023-05-23 | 成都芯翼科技有限公司 | M-LVDS drive circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080129349A1 (en) * | 2006-12-05 | 2008-06-05 | Integrated Device Technology, Inc. | Output Slew Rate Control In Low Voltage Differential Signal (LVDS) Driver |
| WO2015170845A1 (en) * | 2014-05-08 | 2015-11-12 | (주) 픽셀플러스 | Low-voltage differential signalling transmitter |
| CN105207661A (en) * | 2015-09-18 | 2015-12-30 | 中国科学院微电子研究所 | Multi-point low voltage differential signal transmitter |
| CN106656148A (en) * | 2016-12-20 | 2017-05-10 | 峰岹科技（深圳）有限公司 | Two-way IO circuit for preventing current from flowing backwards |
| CN107968552A (en) * | 2017-12-29 | 2018-04-27 | 电子科技大学 | A kind of floating gate voltage drive circuit for Switching Power Supply |
| CN110868204A (en) * | 2019-11-04 | 2020-03-06 | 深圳市国微电子有限公司 | Anti-backflow circuit, bidirectional level converter and integrated circuit |
-
2021
- 2021-12-17 CN CN202111552556.8A patent/CN114268080B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080129349A1 (en) * | 2006-12-05 | 2008-06-05 | Integrated Device Technology, Inc. | Output Slew Rate Control In Low Voltage Differential Signal (LVDS) Driver |
| WO2015170845A1 (en) * | 2014-05-08 | 2015-11-12 | (주) 픽셀플러스 | Low-voltage differential signalling transmitter |
| CN106416077A (en) * | 2014-05-08 | 2017-02-15 | 派视尔株式会社 | Low-voltage differential signalling transmitter |
| CN105207661A (en) * | 2015-09-18 | 2015-12-30 | 中国科学院微电子研究所 | Multi-point low voltage differential signal transmitter |
| CN106656148A (en) * | 2016-12-20 | 2017-05-10 | 峰岹科技（深圳）有限公司 | Two-way IO circuit for preventing current from flowing backwards |
| CN107968552A (en) * | 2017-12-29 | 2018-04-27 | 电子科技大学 | A kind of floating gate voltage drive circuit for Switching Power Supply |
| CN110868204A (en) * | 2019-11-04 | 2020-03-06 | 深圳市国微电子有限公司 | Anti-backflow circuit, bidirectional level converter and integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155254A (en) * | 2023-04-18 | 2023-05-23 | 成都芯翼科技有限公司 | M-LVDS drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114268080B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5872464A (en) | Input buffer with stabilized trip points | |
| US20040178828A1 (en) | Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption | |
| US7511555B2 (en) | Level conversion circuit and input-output device using same | |
| US7525367B2 (en) | Method for implementing level shifter circuits for integrated circuits | |
| US6127841A (en) | CMOS buffer having stable threshold voltage | |
| US7786760B2 (en) | I/O buffer circuit | |
| US20050270079A1 (en) | Input buffer structure with single gate oxide | |
| US7432762B2 (en) | Circuit having enhanced input signal range | |
| US7800426B2 (en) | Two voltage input level shifter with switches for core power off application | |
| JPH0964718A (en) | Output buffer circuit | |
| KR100363381B1 (en) | Two-supply protection circuit | |
| JP3657243B2 (en) | Level shifter, semiconductor integrated circuit, and information processing system | |
| US5880617A (en) | Level conversion circuit and semiconductor integrated circuit | |
| CN110098830B (en) | Substrate switching circuit and level conversion circuit of transistor | |
| CN114268080B (en) | M-LVDS drive circuit capable of preventing bus leakage | |
| US7358790B2 (en) | High performance level shift circuit with low input voltage | |
| US20070279091A1 (en) | Digital Voltage Level Shifter | |
| EP3955252A1 (en) | High speed circuit with driver circuit | |
| US8736311B2 (en) | Semiconductor integrated circuit | |
| US20090167369A1 (en) | Lvds output driver | |
| US6426658B1 (en) | Buffers with reduced voltage input/output signals | |
| JP4753663B2 (en) | Output circuit | |
| US7532071B2 (en) | Operational amplifier circuit | |
| KR100713907B1 (en) | Circuit for driving lines of a semiconductor | |
| US6388475B1 (en) | Voltage tolerant high drive pull-up driver for an I/O buffer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |