CN114265561A - Data reading control method, chip and medium - Google Patents
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Abstract
The invention provides a data reading control method, which comprises the following steps: when the chip is powered on, the control module enters a working state from an idle state, and the control module reads a head file from a memory; the head file stores readable and writable data; the control module reads the head addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file and respectively stores the head addresses and the block lengths into a head address register and a block length register, wherein M is a positive integer; and the control module reads the data of the M target storage blocks from the memory according to the head addresses of the M target storage blocks and the block lengths of the M target storage blocks. The method provides for flexible access to data in the memory without relying on a micro-control unit.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a data reading control method, a chip, and a medium.
Background
In today's System On Chip (SOC) design, Memory is an indispensable part, especially some Memory cells that can be read and written many times, such as Flash Memory. In practical application, data in the flash memory can be repeatedly programmed and changed according to practical situations, flexible access to the data in the memory is difficult to realize under the condition that a Micro Control Unit (MCU) is not used for controlling read and write addresses, and it is obviously not practical if the data in the memory is completely read at one time. Therefore, a data reading control method, a chip and a medium are needed to improve the above problems.
Disclosure of Invention
The invention aims to provide a data reading control method, a chip and a medium, which are used for flexibly accessing data in a memory without depending on a micro control unit.
In a first aspect, the present invention provides a data reading method applied to a chip including a control module, the method including: when the chip is powered on, the control module enters a working state from an idle state, and the control module reads a head file from a memory; the head file stores readable and writable data; the control module reads the head addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file and respectively stores the head addresses and the block lengths into a head address register and a block length register, wherein M is a positive integer; and the control module reads the data of the M target storage blocks from the memory according to the head addresses of the M target storage blocks and the block lengths of the M target storage blocks.
The data reading method provided by the invention has the beneficial effects that: the first address of the target storage block and the block length of the target storage block in the head file are read from the memory, and the first address and the block length of the target storage block are respectively stored in the first address register and the block length register, so that the first address position of the target data block and the block length to be read are conveniently and definitely read, and the data in the memory can be flexibly accessed without depending on a micro control unit.
Optionally, reading the head addresses of the M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file, including: the control module reads a synchronous code and an information code in the target storage block, wherein the synchronous code in the target storage block is used for guiding the control module to jump to a state of reading the target storage block; when the control module identifies that the information code in the target storage block is legal, reading the head addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file; and when the control module identifies that the information code in the target storage block is illegal, the control module jumps to a state of reading the next target storage block. The beneficial effects are that: the control module is guided to jump to the state of reading the header file through the synchronous codes, so that the data in the header file can be conveniently searched, and the addressing time can be saved; when the control module identifies that the information code in the target storage block is illegal, the control module jumps to the state of reading the next target storage block to avoid reading wrong data, which is beneficial to improving the stability of the reading method.
Optionally, reading the head addresses of the M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file, including: the control module reads the M target storage blocks one by one; and the address counter records the reading length of the target storage block from the first address by the control module, and when the reading length reaches the block length, the control module stops reading. The beneficial effects are that: when the reading length reaches the block length, the control module stops reading to ensure that proper data can be read, and work delay caused by the fact that the reading method is always in the reading process is avoided.
Optionally, the method further includes: the control module judges whether all the first addresses in the first address register are read; when the first addresses in the first address register are not all read, the control module jumps to a working state; and when all the first addresses in the first address register are read, the control module jumps to the idle state. The beneficial effects are that: the control module jumps to a working state, so that the control module can read a next target storage block conveniently; the control module jumps to the idle state, facilitating the control module to wait for a start instruction.
Optionally, when all the first addresses in the first address register are not read, the control module jumps to a working state, and further includes: and when the first addresses in the first address register are not all read, the control module empties the address counter and jumps to a working state. The beneficial effects are that: by clearing the address counter, space for the address counter can be freed up for reading the next target memory block.
Optionally, when all the first addresses in the first address register are read, jumping to the idle state further includes: and when all the initial addresses in the initial address register are read, the control module empties the initial address register, the address counter and the block length register and jumps to the idle state. The beneficial effects are that: the control module empties the first address register, the address counter and the block length register to return the control module to the initial state, so that the influence of residual data on subsequent reading work is avoided.
Optionally, the synchronization code and the information code occupy at least four bytes; the information code includes a model number of the chip, a version number of the chip, or a program version number. The beneficial effects are that: the different chips are distinguished through the types of the chips, the version numbers of the chips or the program version numbers, and the reading process is limited within a reasonable authority range.
Optionally, a header file length code and a block header address set code are stored in the header file; the header file length code is used for configuring the length of the header file; the block head address set code is used for configuring head addresses of a plurality of target storage blocks; the header file length code and the block head address set code are both readable and writable data. The beneficial effects are that: the header file length code and the block head address set code are both readable and writable data, so that the header file content can be flexibly adjusted, and flexible reading can be realized by selecting the required target data block head address and block length.
In a second aspect, the invention provides a chip characterized by a method for performing any one of the possible designs of the first aspect, the chip comprising a control module; the control module comprises an address counter, a first address register, a block length register and a state machine.
In a third aspect, the present invention provides a readable storage medium, in which a program is stored, wherein the program, when executed, implements any one of the possible design methods of the first aspect.
Drawings
FIG. 1 is a schematic flow chart of a data reading method according to the present invention;
FIG. 2 is a schematic diagram illustrating a storage method of a memory according to the present invention;
FIG. 3 is a state machine transition diagram of a control module according to the present invention;
fig. 4 is a schematic diagram of a chip structure according to the present invention.
Reference numbers in the figures:
400. a chip; 410. a control module; 411. a state machine; 412. a first address register; 413. an address counter; 414. a block length register.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
Fig. 1 is a schematic flow chart of a data reading method according to the present invention.
To solve the problems in the prior art, as shown in fig. 1, the present invention provides a data reading method applied to a chip including a control module, the method including:
s101, after the chip is powered on, the control module enters a working state from an idle state, and the control module reads a head file from a memory; the head file stores readable and writable data;
it is noted that in some embodiments, the control module 410 is placed in an idle state via a reset command. When the control module 410 receives the start instruction, it jumps to the working state. In the working state, the block lengths of the M target storage blocks are read from the header file, and then the first addresses of the M target storage blocks are respectively read.
Fig. 2 is a schematic diagram of a storage method of a memory according to the present invention.
In some embodiments, as shown in fig. 2, the storage space of the memory includes a header file and a plurality of target storage blocks, and addresses between the header file and the plurality of target storage blocks may be continuous or discontinuous. The addresses between the target memory blocks may be contiguous or non-contiguous.
In some embodiments, a header file length code and a block header address set code are stored in the header file; the header file length code is used for configuring the length of the header file; the block head address set code is used for configuring head addresses of a plurality of target storage blocks; the header file length code and the block head address set code are both readable and writable data.
In some specific embodiments, as shown in table one, the M target memory blocks are Block1-Block M, respectively. Illustratively, the memory has a storage space of 4 MB. In the storage space of the memory, the header file, Block1, Block2 are arranged in sequence up to Block m with the head address of the header file as a reference. It should be noted that the present embodiment uses 16-ary to represent offset addresses and data. Illustratively, the sync code of the header file stored here is a 16-bit 16-system number 0xA9560000, with 0xA9 as the starting position of the header file, and the data stored subsequently are 0x56, 0x00 and 0x00, respectively. And the chip model number and the chip version number are 16-bit 16-system numbers, are represented as 0xXXXX and can be any data from 0x0000 to 0 xffff.
In other embodiments, the storage space of the memory may be any size. The header file and the M target storage blocks may be arranged continuously or discontinuously. Data may be represented in 8 or other binary form. The synchronous code, the chip model and the chip version number of the header file can be any data represented by any system, and the digits can be full or not full, so that the header file can be flexibly set according to actual projects.
In some embodiments, the synchronization code and the information code each occupy at least four bytes; the information code includes a model number of the chip 400, a version number of the chip 400, or a program version number.
In some specific embodiments, four bytes after the beginning of the first address of the header file are synchronization codes. And two bytes after the synchronous code are used for storing the model of the chip. And the two bytes after the chip model are used for storing the version number of the chip. It is noted that the chip model or chip version number may be used to encrypt the header file. And two bytes after the version number of the chip are used for configuring the total length of data. The header file Length code Head Length comprises the total Length of the Head addresses configuring the Block1-Block M. The bytes after the header Length code Head Length are used for configuring the first address of Block1-Block M. The first address of each target storage block occupies two byte spaces, and the least significant bit of the first address of the target storage block is in front of the most significant bit of the first address of the target storage block.
In some embodiments, the memory structures of Block1-Block M are identical. Taking Block1 as an example, four bytes after the start of the first address of Block1 are synchronization codes. And two bytes after the synchronous code are used for storing the model of the chip. And the two bytes after the chip model are used for storing the version number of the chip. It is worth noting that the chip model or chip version number may be used to encrypt the Block 1. The two bytes after the chip version number are used for the configuration Block length of Block 1. The bytes after the configuration Block length of Block1 are the configuration data of Block 1.
In other embodiments, the occupied spaces of the synchronization code, the chip model, the chip version number, and the first address of the target memory block may be set to any number of bytes according to the requirement of the project. The storage sequence of the synchronous codes, the chip models and the chip version numbers can be set to be any sequence according to project requirements. The first address of the target memory block may be set with the most significant bit preceding and the least significant bit following.
In some embodiments, reading the first addresses of the M target memory blocks in the memory and the block lengths of the M target memory blocks from the header file includes: the control module 410 reads the M target memory blocks one by one; the address counter 413 records the read length of the target storage block from the first address, and when the read length reaches the block length, the control module 410 stops reading.
In other embodiments, the control module 410 may also control whether to stop reading by determining whether the information code is illegal, for example, when the information code is illegal, the control module 410 stops reading.
In still another embodiment, the control module 410 may further control whether to stop reading by determining whether the read length reaches the block length and determining whether the information code is illegal.
S102, the control module 410 reads the first addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file, and respectively stores the first addresses and the block lengths into a first address register 412 and a block length register 414, wherein M is a positive integer;
fig. 3 is a transition diagram of a state machine 411 of a control module 410 according to the present invention.
As shown in fig. 3, in some embodiments, reading the first addresses of the M target memory blocks in the memory and the block lengths of the M target memory blocks from the header file includes: the control module 410 reads a synchronization code and an information code in the target storage block, wherein the synchronization code in the target storage block is used for guiding the control module 410 to jump to a state of reading the target storage block; when the control module 410 recognizes that the information code in the target storage block is legal, reading the first addresses of the M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file; when the control module 410 recognizes that the information code in the target storage block is illegal, the control module 410 jumps to a state of reading a next target storage block.
In some embodiments, the control module 410 is first in IDLE state IDLE by a reset instruction rst _ n, then enters an active state by a start command start, and then enters a sequence detection state SEQ _ DEC to retrieve data of a target memory block in the memory. When the sync code of Block1 is detected, it jumps to the state of read Block 1. The control module 410 reads the information code and judges whether the information code of Block1 is illegal. When the information code of Block1 is legal, the data of Block1 is read continuously. When the information code of Block1 is illegal, the method enters a read completion state DONE and stops reading. The control module 410 jumps to a state where the next target memory block is read. Continuously judging whether the read length exceeds the Block1 Block length in the state of reading the Block1, and continuously reading the Block1 data when the read length does not exceed the Block1 Block length; when the read length exceeds the Block length of Block1, the read completion state DONE is entered and the read is stopped.
In other embodiments, the control module 410 may stop reading or re-read from the first target memory block when there is no next target memory block or when the memory is read in its entirety.
S103, the control module 410 reads data of the M target storage blocks from the memory according to the head addresses of the M target storage blocks and the block lengths of the M target storage blocks.
In some embodiments, the method further comprises: the control module 410 determines whether all the first addresses in the first address register 412 are read; when all the first addresses in the first address register 412 are not read, the control module 410 jumps to the working state; when all of the first addresses in the first address register 412 are read, the control module 410 transitions to the idle state.
It is noted that in other embodiments, the control module 410 may also jump to the idle state when all addresses in the memory are read.
In some embodiments, when all of the first addresses in the first address register 412 are not read, the control module 410 jumps to the working state, further comprising: when all the first addresses in the first address register 412 are not read, the control module 410 clears the address counter 413, and the control module 410 jumps to the working state.
In some embodiments, when all the first addresses in the first address register 412 are not read, the control module 410 jumps to the suspend state HOLD, clears the address counter 413, and jumps to the active state.
In other embodiments, when all the first addresses in the first address register 412 are read, the control module 410 clears the first address register 412, the address counter 413, and the block length register 414, and transitions to the idle state.
In some embodiments, when all the first addresses in the first address register 412 are read, the control module 410 clears the address counter 413, the first address register 412, and the block length register 414, and then the control module 410 jumps to the IDLE state IDLE. By clearing the address counter 413, the first address register 412 and the block length register 414, new data is registered for subsequent reads.
Fig. 4 is a schematic structural diagram of a chip 400 according to the present invention.
As shown in fig. 4, the present invention further provides a chip 400 for performing the method according to any one of the above method embodiments, where the chip 400 includes a control module 410; the control module 410 includes an address counter 413, a first address register 412, a block length register 414, and a state machine 411.
In some embodiments, the control module 410 includes an address counter 413, a head address register 412, a block length register 414, and a state machine 411. The address counter 413 is used to calculate the read address length in real time. The first address register 412 is used to store the first address of the target memory block. The block length register 414 is used to store the block length of the target memory block. The state machine 411 is used for the jump state.
In other embodiments, the address counter 413, the first address register 412, and the block length register 414 may be in the form of a register set or a general purpose register. The state machine 411 may be provided separately from the address counter 413, the first address register 412, and the block length register 414, or the address counter 413, the first address register 412, and the block length register 414 may be built in the state machine 411.
The invention also provides a readable storage medium, in which a program is stored, wherein the program, when executed, implements the method according to any of the method embodiments described above.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A data reading method is applied to a chip comprising a control module, and is characterized by comprising the following steps:
when the chip is powered on, the control module enters a working state from an idle state, and the control module reads a head file from a memory; the head file stores readable and writable data;
the control module reads the head addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file and respectively stores the head addresses and the block lengths into a head address register and a block length register, wherein M is a positive integer;
and the control module reads the data of the M target storage blocks from the memory according to the head addresses of the M target storage blocks and the block lengths of the M target storage blocks.
2. The method of claim 1, wherein reading the first addresses of the M target memory blocks in the memory and the block lengths of the M target memory blocks from the header file comprises:
the control module reads a synchronous code and an information code in the target storage block, wherein the synchronous code in the target storage block is used for guiding the control module to jump to a state of reading the target storage block;
when the control module identifies that the information code in the target storage block is legal, reading the head addresses of M target storage blocks in the memory and the block lengths of the M target storage blocks from the header file;
and when the control module identifies that the information code in the target storage block is illegal, the control module jumps to a state of reading the next target storage block.
3. The method of claim 1 or 2, wherein reading the first addresses of the M target memory blocks in the memory and the block lengths of the M target memory blocks from the header file comprises:
the control module reads the M target storage blocks one by one;
and the address counter records the reading length of the target storage block from the first address by the control module, and when the reading length reaches the block length, the control module stops reading.
4. The method of claim 3, further comprising: the control module judges whether all the first addresses in the first address register are read;
when the first addresses in the first address register are not all read, the control module jumps to the working state;
and when all the first addresses in the first address register are read, the control module jumps to the idle state.
5. The method of claim 4, wherein the control module transitions to the active state when not all of the first addresses in the first address register are read, further comprising:
and when the first addresses in the first address register are not all read, the control module empties the address counter and jumps to the working state.
6. The method of claim 4, wherein jumping to the idle state when all of the first addresses in the first address register are read, further comprises:
and when all the initial addresses in the initial address register are read, the control module empties the initial address register, the address counter and the block length register and jumps to the idle state.
7. The method of claim 2,
the synchronous code and the information code occupy at least four bytes;
the information code includes a model number of the chip, a version number of the chip, or a program version number.
8. The method according to claim 1 or 2,
the header file is stored with a header file length code and a block head address set code;
the header file length code is used for configuring the length of the header file;
the block head address set code is used for configuring head addresses of a plurality of target storage blocks; the header file length code and the block head address set code are both readable and writable data.
9. A chip for performing the method of any one of claims 1-8, the chip comprising a control module; the control module comprises an address counter, a first address register, a block length register and a state machine.
10. A readable storage medium having a program stored therein, wherein the program, when executed, implements the method of any of claims 1 to 8.
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