CN114256283A - CMOS image sensor and method of manufacturing the same - Google Patents

CMOS image sensor and method of manufacturing the same Download PDF

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Publication number
CN114256283A
CN114256283A CN202111657644.4A CN202111657644A CN114256283A CN 114256283 A CN114256283 A CN 114256283A CN 202111657644 A CN202111657644 A CN 202111657644A CN 114256283 A CN114256283 A CN 114256283A
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type
region
epitaxial layer
photodiode
image sensor
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孙德明
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Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
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Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Abstract

The present invention provides a CMOS image sensor and a method of manufacturing the same, the CMOS image sensor including: a substrate having a P-type epitaxial layer; a photodiode formed in the P-type epitaxial layer; the photodiode comprises a first P-type contact region formed in a P-type epitaxial layer, a first P-type doped region formed in the P-type epitaxial layer below the first P-type contact region, and a first metal pad formed above the first P-type contact region, wherein an electron potential well is formed between the first metal pad and the photodiode through the first P-type doped region and the P-type epitaxial layer. In the invention, the first P-type doped region is used as an electron barrier between the first P-type contact region and the photodiode to prevent the first metal pad from emitting electrons to the photodiode through the first P-type contact region to form dark current, and the P-type epitaxial layer between the first P-type contact region and the first P-type doped region is used as an electron potential well to accommodate the electrons, thereby reducing the dark current of the CMOS image sensor.

Description

CMOS image sensor and method of manufacturing the same
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a CMOS image sensor and a method for manufacturing the same.
Background
The CMOS Image Sensor (CIS) has many advantages over the original CCD due to its compatibility with the existing standard CMOS manufacturing process. The CMOS image sensor can integrate digital-analog operation, a control circuit and a pixel unit, simplifies hardware design, simultaneously reduces power consumption of a system, can process image information in real time, and has higher speed than a CCD image sensor.
However, compared with the CCD image sensor, the CMOS image sensor always has a problem of large Dark Current (DC), and the Dark Current causes problems of large noise, low sensitivity, and the like of the CMOS image sensor, thereby seriously affecting the imaging quality. As shown in the schematic structural diagram of the pixel unit of the conventional CMOS image sensor provided in fig. 1, since the first P-type contact region 22 '(e.g., the body end of the NMOS transistor) of the transistor (e.g., the NMOS transistor) of the transistor region 20' is not in perfect ohmic contact with the first metal pad 23 ', the first metal pad 23' emits minority carriers (electrons) to the substrate 10 'through the first P-type contact region 22', and the minority carriers further diffuse to the N region of the adjacent photodiode 40 ', so as to form the dark current of the photodiode 40'. In addition, the second P-type contact region 32 ' provided in the isolation region 30 ' provided around the photodiode 40 ' also has similar problems.
Disclosure of Invention
The invention aims to provide a CMOS image sensor and a manufacturing method thereof, which are used for reducing dark current of a pixel unit of the CMOS image sensor.
To solve the above technical problem, the present invention provides a CMOS image sensor, including: a substrate having a P-type epitaxial layer; a photodiode formed in the P-type epitaxial layer; the photodiode comprises a first P-type contact region formed in the P-type epitaxial layer, a first P-type doped region formed in the P-type epitaxial layer below the first P-type contact region, and a first metal pad formed above the first P-type contact region, wherein the first P-type contact region is positioned on one side of the photodiode, and an electron potential well is formed between the first metal pad and the photodiode through the first P-type doped region and the P-type epitaxial layer.
Optionally, the CMOS image sensor further includes a second P-type contact region formed in the P-type epitaxial layer, a second P-type doped region formed in the P-type epitaxial layer below the second P-type contact region, and a second metal pad formed above the second P-type contact region, the second P-type contact region is located at the other side of the photodiode, and an electron potential well is formed between the second metal pad and the photodiode through the second P-type doped region and the P-type epitaxial layer.
Optionally, the CMOS image sensor further includes a shallow trench isolation structure and a P-type isolation layer, the shallow trench isolation structure surrounds the photodiode, the P-type isolation layer is disposed below the shallow trench isolation structure, and the second P-type doped region is located in a P-type epitaxial layer on the outer side of the shallow trench isolation structure surrounding the photodiode.
Optionally, the doping concentration of the first P-type doped region and the second P-type doped region is 6 × 1017/cm3～5×1018/cm3。
Optionally, the CMOS image sensor further includes a P-type well region formed in the P-type epitaxial layer, an N-type heavily doped region formed in the P-type well region, and a third metal pad above the N-type heavily doped region, where the N-type heavily doped region is used as a source terminal of a reset transistor of the CMOS image sensor or a drain terminal of a transfer transistor of the CMOS image sensor.
Optionally, the CMOS image sensor further includes a reset transistor, and the first P-type contact region is located in the P-type epitaxial layer on one side of the drain terminal of the reset transistor.
Optionally, a distance between the first P-type contact region and the drain of the reset transistor is less than or equal to 0.5 μm.
Optionally, the CMOS image sensor is a back-illuminated CMOS image sensor.
Based on another aspect of the present invention, the present invention also provides a method for manufacturing a CMOS image sensor, including: providing a substrate, wherein the substrate is provided with a P-type epitaxial layer; forming a photodiode, a first P-type contact region and a first P-type doped region in the P-type epitaxial layer, forming a first metal pad above the first P-type contact region, wherein the first P-type contact region is positioned at one side of the photodiode, and forming an electron potential well between the first metal pad and the photodiode through the first P-type doped region and the P-type epitaxial layer.
Optionally, a second P-type contact region and a second P-type doped region are formed in the P-type epitaxial layer, the second P-type contact region is located above the second P-type doped region, and a second metal pad is formed above the second P-type contact region; the first P-type contact region and the second P-type contact region are formed simultaneously, the first P-type doped region and the second P-type doped region are formed simultaneously, and an electron potential well is formed between the second metal pad and the photodiode through the second P-type doped region and the P-type epitaxial layer.
In summary, the CMOS image sensor and the manufacturing method provided by the invention have the following beneficial effects: the first P-type doped region is formed in the P-type epitaxial layer below the first P-type contact region and serves as a potential barrier between the first P-type contact region and the photodiode, so that electrons emitted from the first metal pad are prevented from flowing to the photodiode, an electron potential well is formed between the first metal pad and the photodiode by the first P-type doped region and the P-type epitaxial layer, and the electrons emitted from the first metal pad are stored by the electron potential well, so that the dark current of a pixel unit of the CMOS image sensor is reduced, and the imaging quality is improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
fig. 1 is a schematic diagram of a conventional CMOS image sensor;
fig. 2 is a schematic diagram of a CMOS image sensor provided in an embodiment of the present application;
fig. 3 is an equivalent circuit diagram of a CMOS image sensor provided in an embodiment of the present application;
fig. 4 is a schematic top view of a CMOS image sensor provided in an embodiment of the present application;
fig. 5 is a flowchart of a method for manufacturing a CMOS image sensor according to an embodiment of the present disclosure;
fig. 6a to 6g are schematic structural diagrams corresponding to respective steps of the method for manufacturing a CMOS image sensor according to this embodiment.
In fig. 1:
10' -a substrate; 20' -a transistor region; 11' -shallow trench isolation; 22' -a first P-type contact region; 23' -a first metal pad; 30' -an isolation region; 32' -a second P-type contact region; 33' -second metal pads; 40' -photodiode.
In fig. 2 to 6 g:
10-a substrate; an 11-P type epitaxial layer; 12-shallow trench isolation structures; 13-N type lightly doped region; 14-P type clamping layer; AA-photodiode region; BB-isolation area; a CC-transistor region;
21-a first P-type contact region; 22-a first P-type doped region; 23-a first metal pad;
31-a second P-type contact region; 32-a second P-type doped region; 33-a second metal pad;
41-N type heavily doped region; a 42-P type well region; 43-a third metal pad;
a 51-P type injection layer; a 52-P type spacer layer; 53-gate structure;
61-back dielectric layer; 61 a-a first dielectric layer; 61 b-a second dielectric layer; 62-front dielectric layer;
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 2 is a schematic diagram of a CMOS image sensor provided in an embodiment of the present application.
As shown in fig. 2, the CMOS image sensor provided in the embodiment of the present application includes a substrate having a P-type epitaxial layer 11; a photodiode formed in the P-type epitaxial layer 11; the photodiode structure comprises a first P-type contact region 21 formed in a P-type epitaxial layer, a first P-type doped region 22 formed in the P-type epitaxial layer 11 below the first P-type contact region 21, and a first metal pad 23 formed above the first P-type contact region 21, wherein the first P-type contact region 21 is positioned on one side of the photodiode, and an electron potential well is formed between the first metal pad 23 and the photodiode through the first P-type doped region 22 and the P-type epitaxial layer 11.
The substrate may be, for example, a P-type substrate, the P-type epitaxial layer 11 is located on the front surface of the P-type substrate 10, and the pixel unit of the CMOS image sensor is formed in the P-type epitaxial layer 11 and on the front surface of the P-type epitaxial layer 11.
Referring to fig. 2, as a preferred embodiment, the CMOS image sensor may be a back-illuminated CMOS image sensor, which utilizes light incident from the back side to improve the dark current reduction, i.e., the substrate on the back side of the P-type epitaxial layer 11 is removed and covered with the back dielectric layer 61, and the back dielectric layer 61 is used as a light incident window of the CMOS image sensor. The back dielectric layer 61 comprises a first dielectric layer 61a covering the P-type epitaxial layer 11 and a second dielectric layer 61b covering the first dielectric layer 61 a. The first dielectric layer 61a may be made of silicon oxide, and the second dielectric layer 61b may be made of a high-k dielectric, so that holes are accumulated at the interface between the first dielectric layer 61a and the P-type epitaxial layer 11 by using negative charges carried by the high-k dielectric, and the interface state level is filled with the holes, thereby reducing the dark current at the interface. Preferably, the second dielectric layer 61b may be, for example, hafnium oxide, and the first dielectric layer 61a may be a silicon oxide layer formed by a low temperature process (LTO), for example, a PECVD process, to further reduce the dark current introduced at the above interface.
With reference to fig. 2, a pixel unit (also referred to as a pixel) of the CMOS image sensor includes a photodiode area AA, a transistor area CC and an isolation area BB, the isolation area BB surrounds the photodiode area AA for isolation and shielding, the transistor area CC is located on the other side of the isolation area BB (across the isolation area BB) relative to the photodiode area AA and is electrically connected to the photodiode area AA for driving and reading a photo signal.
The photodiode area AA includes at least one photodiode, and the photodiode uses the N-type lightly doped region 13 as an N region and uses the P-type epitaxial layer 11 surrounding the N-type lightly doped region 13 as a P region. Preferably, the photodiode may further include a P-type clamp layer 14 partially covering the front surface of the N-type lightly doped region 13, and the doping concentration of the P-type clamp layer 14 is greater than that of the N-type lightly doped region 13, so as to fill the interface level on the surface of the N-type lightly doped region 4113 with holes, thereby reducing the dark current. In one embodiment, the doping concentration of the P-type clamp layer 14 is, for example, greater than or equal to 1 × 1018/cm3。
The transistor region CC may be, for example, a 4T structure (4 transistors) including a transfer transistor TG, a floating node FD, a reset transistor RS, a source follower transistor SF, and a selection transistor SEL. Specifically, taking the transistor regions CC all made of NMOS transistors as an example, the connection relationship may be as shown in fig. 3, where the source terminal of the transfer transistor TG is connected to the N terminal (N-type lightly doped region 13) of the photodiode, the drain terminal of the transfer transistor TG is connected to the floating node FD, the source terminal of the reset transistor RS and the gate of the source follower transistor SF are connected to the floating node FD, the drain terminal of the reset transistor RS and the drain terminal of the source follower transistor SF are connected to VDD, the drain terminal of the select transistor SEL is connected to the source terminal of the source follower transistor SF, and the source terminal of the select transistor SEL is used as the output terminal of the transistor region CC and the output terminal of the pixel unit. Of course, in practice, the number and types of transistors in the transistor area CC are not limited thereto, but the transistor area CC may also include more or less transistors, such as 3T structure or 5T structure, and other elements for decoupling noise reduction, such as capacitors or resistors. The 3T structure includes 3 transistors, such as a reset transistor RS, a source follower transistor SF, and a select transistor SEL; the 5T structure includes 5 transistors, which may be, for example, 2 transfer transistors TG, a reset transistor RS, a source follower transistor SF, and a select transistor SEL. The present embodiment is not limited to the specific structure of the transistor region CC, and those skilled in the art can apply the principle of the present embodiment to the specific transistor region CC (driving circuit of the pixel unit).
With reference to fig. 2, the transistor region CC at least includes a first P-type contact region 21 for grounding the P-type epitaxial layer 11 of the transistor region CC to achieve electrical isolation of the transistor and prevent the floating node FD (floating drain) from output drift. The first P-type contact region 21 is located on the surface of the P-type epitaxial layer 11, the front surface of the P-type epitaxial layer 11 is covered with a front surface dielectric layer 62, a contact hole exposing the first P-type contact region 21 is formed in the front surface dielectric layer 62, a first metal pad 23 is formed in the contact hole, and the first P-type contact region 21 is electrically led out by using ohmic contact formed by the first P-type contact region 21 and the first metal pad 23.
Specifically, a first P-type doped region 22 is further formed in the P-type epitaxial layer 11 below the first P-type contact region 21, an electron potential well is formed between the first metal pad 23 and the photodiode through the first P-type doped region 22 and the P-type epitaxial layer 11, electrons emitted from the first metal pad 23 are stored by the electron potential well, and the electrons emitted from the first metal pad 23 are prevented from diffusing to the photodiode region AA to form a dark current, which affects the imaging quality. It is understood that in practice, the contact between the first metal pad 23 and the first P-type contact region 21 is difficult to form a perfect ohmic contact, so that the first metal pad 23 emits electrons to the first P-type contact region 21, so that the electrons diffuse to the photodiode area AA to form a dark current, which affects the imaging quality.
Further, the doping concentration of the first P-type doped region 22 is greater than that of the P-type epitaxial layer11 and the barrier height of the first P-type doped region 22 is above 0.15 ev in order to effectively prevent electrons emitted from the first metal pad 23 from crossing the barrier. In a preferred embodiment, the doping concentration of the first P-type doped region 22 is 6 × 1017/cm3Less than 5 x 1018/cm3The thickness of the doping concentration of the first P-type doped region 22 is greater than 0.3 μm, and the distance between the first P-type doped region 22 and the first P-type contact region 21 is greater than 0.1 μm, so that an electron well formed by the P-type epitaxial layer 11 between the first P-type doped region 22 and the first P-type contact 21 stores electrons. Moreover, the first P-type doped region 22 may also extend to the shallow trench isolation structure 12 on both sides of the transistor region CC along the width direction (laterally) as much as possible to improve the blocking effect of the second P-type doped region 3222. The shallow trench isolation structure 12 is used to define each region of the pixel unit, and taking the depth of the shallow trench isolation structure 12 as 0.3 micrometer as an example, the thickness of the second P-type contact region 3121 may be, for example, 0.1 micrometer, the thickness of the first P-type doped region 22 may be, for example, 0.3 micrometer, and the first P-type doped region 22 may be located at the bottom of the shallow trench isolation structure 12.
Furthermore, the first P-type doped region 22, i.e. the first P-type contact region 21 or the first metal pad 23, is disposed near the drain (VDD) of the reset transistor RS, for example, the first P-type contact 21 is located in the P-type epitaxial layer 11 on one side of the drain of the reset transistor RS, so as to draw away the electrons stored in the electron well when the reset transistor RS is reset. Preferably, the first P-type doped region 22 and the reset transistor RS are located in the same active region, and the distance between the first metal pad 23 and the metal pad at the drain terminal of the reset transistor RS is less than or equal to 0.5 μm, so as to improve the effect of extracting electrons from the electron well when the reset transistor RS is reset.
With reference to fig. 2, the isolation region BB surrounds the photodiode region AA to isolate and shield the photodiode region AA, and of course, the isolation region BB is provided with an opening at the junction of the transistor region CC and the photodiode region AA (the transfer transistor TG) for electrical connection, and due to the opening, only the isolation region BB on the right side of the photodiode region AA is shown in fig. 2. The isolation region BB may, for example, include the shallow trench isolation structure 12 and the P-type isolation layer 52 located under the shallow trench isolation structure 12, wherein the shape of the shallow trench isolation structure 12 surrounding the photodiode area AA may be set according to specific requirements. In practice, if the photodiode areas AA of at least two pixel units are adjacently disposed, the isolation area BB may surround the periphery of the at least two pixel units, and the photodiode areas AA between the at least two pixel units are isolated by the P-type isolation layer 52.
The second P-type contact region 31 is arranged in the P-type epitaxial layer 11 outside the shallow trench isolation structure 12 surrounding the photodiode region AA, and the second P-type contact region 31 is used for grounding the P-type epitaxial layer 11 of the photodiode region AA and keeping a zero potential. In practice, the second P-type contact region 31 may also be formed on the surface of the P-type epitaxial layer 11 (active region) surrounded by the shallow trench isolation structure 12, and the second metal pad 33 is formed in the front dielectric layer 62, and the second P-type contact region 31 is electrically led out by using the ohmic contact formed between the second P-type contact region 31 and the second metal pad 33.
In particular, the P-type epitaxial layer 11 under the second P-type contact region 31 is provided with a second P-type doped region 32, and an electron potential well is formed between the second metal pad 33 and the photodiode through the second P-type doped region 32 and the P-type epitaxial layer 11, so that electrons emitted from the second metal pad 33 are prevented from diffusing to the photodiode area AA to form a dark current, which affects the imaging quality. Specifically, the second P-type doped region 32 may be formed simultaneously with the first P-type doped region 22, and the specific configuration thereof may refer to the first P-type doped region 22, which is not described herein again. Preferably, the isolation region BB is further provided with a P-type isolation layer, which surrounds the shallow trench isolation structure and the photodiode region AA from below to further improve the isolation effect. Wherein, the periphery of the shallow trench isolation structure 12 is further provided with a P-type injection layer 51, the P-type injection layer 51 surrounds the shallow trench isolation structure 12 along the outer wall of the shallow trench isolation structure 12, so that the interface state energy level between the shallow trench isolation structure 12 and silicon is filled by the cavity as much as possible, thereby reducing (suppressing)System) dark current. Preferably, the doping concentration of the P-type implantation layer 51 may be greater than 2 × 1017/cm3. The P-type isolation layer 52 is located under the shallow trench isolation structure 12 and contacts the P-type injection layer 51 to isolate from the side of the photodiode area AA. It should be understood that the depth of the shallow trench isolation structure 12 is shallower than the depth of the photodiode region AA, and the P-type isolation layer 52 can be used to compensate the above depth difference, so as to achieve a better isolation effect for the photodiode region AA.
With reference to fig. 2, the transistor region CC further includes an N-type heavily doped region 41, and the N-type heavily doped region 41 is used as a drain terminal of the pass transistor or a source terminal of the reset transistor, i.e. as a floating node (floating drain) for storing collected photo-generated electrons. The heavily doped N-type region 41 is located on the surface of the P-type epitaxial layer 11, a third metal pad 43 is formed in the front dielectric layer 62, and the drain terminal of the transfer transistor or the source terminal of the reset transistor is led out by using the ohmic contact formed between the heavily doped N-type region 41 and the third metal pad 43. A P-type well region 42 surrounding the heavily doped N-type region 41 is formed under the heavily doped N-type region 41, and the doping concentration of the P-type well region 42 is greater than that of the P-type epitaxial layer 11. It should be noted that the P-well 42 may not extend to the lower side of the first P-type contact region 21 and the second P-type contact region 31, so as to prevent lowering the barrier height of the first P-type doped region 22 or the second P-type doped region 32, thereby increasing the probability of electron escape from the electron well.
In a preferred embodiment, as shown in FIG. 4, a cross-sectional view as shown in FIG. 2 can be obtained using section line XX. The two pixel units are adjacently and symmetrically arranged, the photodiode areas AA of the two pixel units share a part of the isolation area BB, and the second metal pad 33 is arranged outside the isolation area BB of the shared part and is located at one end relatively far away from the transfer transistor TG, so as to simultaneously provide isolation grounding for the P ends of the photodiodes of the two pixel units, and reduce the probability of electrons diffusing to the transfer transistor TG by utilizing the distance far away from the transfer transistor TG, thereby reducing the dark current. The two transistor regions CC of the two pixel units are symmetrically disposed at two sides of the two photodiode regions AA and are disposed adjacent to the isolation region BB to increase the pixel density. The first metal pad 23 is located near the drain (VDD) of the reset transistor RS in the transistor region CC, so that electrons stored in the electron potential well under the first metal pad 23 are extracted when the reset transistor RS is reset, thereby reducing the dark current. Furthermore, the first metal pad 23 may also be located in a region near the middle of the transistor region CC to facilitate grounding of the transistor region CC. Of course, several other transistors, such as a source follower transistor SF and a select transistor SEL, may be provided in the transistor area CC, which are not all shown in fig. 4.
Fig. 5 is a flowchart of a method for manufacturing a CMOS image sensor according to an embodiment of the present application.
As shown in fig. 5, a method for manufacturing a CMOS image sensor according to an embodiment of the present application includes:
s01: providing a substrate 10, wherein the substrate 10 is provided with a P-type epitaxial layer 11;
s02: a photodiode, a first P-type contact region 21 and a first P-type doped region 22 are formed in the P-type epitaxial layer 11, a first metal pad 23 is formed above the first P-type contact region 21, the first P-type contact region 21 is located at one side of the photodiode, and an electron potential well is formed between the first metal pad 23 and the photodiode through the P-type heavily doped region 22 and the P-type epitaxial layer 11.
Fig. 6a to 6g are schematic structural diagrams corresponding to respective steps of the method for manufacturing a CMOS image sensor according to this embodiment. Next, a method of manufacturing the CMOS image sensor will be described in detail with reference to fig. 6a to 6 g.
First, referring to fig. 6a, a substrate 10 is provided, the substrate 10 has a P-type epitaxial layer 11, a shallow trench isolation structure 12 is formed in the P-type epitaxial layer 11, and a photodiode area AA, an isolation area BB and a transistor area CC are defined by the shallow trench isolation structure 12. The substrate 10 may be a P-type substrate.
Next, referring to fig. 6b, an N-type lightly doped region 13 is formed in the photodiode region AA as an N region of the photodiode, and a P-type clamping layer 14 is formed on the N-type lightly doped region 4113, and the P-type clamping layer and the P-type epitaxial layer are used as a P region of the photodiode, wherein the P-type clamping layer 14 covers the surface of the N-type lightly doped region 13 as much as possible.
Next, referring to fig. 6c, a P-type isolation layer 52 and a P-type implantation layer 51 are sequentially formed in the isolation region BB. The P-type implant layer 51 surrounds the shallow trench isolation structure 12 along the outer wall of the shallow trench isolation structure 12, and the P-type isolation layer 52 is located under the shallow trench isolation structure 12 and contacts the P-type implant layer 51.
Next, referring to fig. 6d, a P-well 42 is formed in the transistor region CC, and an N-type heavily doped region 41 is formed in the P-well 42, wherein the N-type heavily doped region 41 is used as a drain terminal of the transfer transistor or a source terminal (floating drain terminal) of the reset transistor.
Next, referring to fig. 6e, a first P-type doped region 22 and a first P-type contact region 21 are sequentially formed in the transistor region CC, and a second P-type contact region 31 is formed in the isolation region BB. Preferably, the second-type heavily doped region 32 is also formed in the isolation region BB simultaneously.
Next, referring to fig. 6f, an annealing process and a metallization process are performed. Specifically, the metallization process includes forming a first metal pad 23, a second metal pad 33, and a third metal pad 43 on the front surface of the P-type epitaxial layer 11.
Next, referring to fig. 6g, a back-side thinning process is performed on the substrate 10, and a back-side dielectric layer 61 is formed on the back side of the P-type epitaxial layer 11. The back dielectric layer 61 includes a first dielectric layer 61a and a second dielectric layer 61 b.
Certainly, the manufacturing method of the CMOS image sensor in this embodiment further includes other corresponding process steps, such as formation of a gate structure of a transistor and formation of a front dielectric layer, but the formation of the above steps is performed by a method commonly used in the art, and is not described herein again.
In summary, the CMOS image sensor and the manufacturing method provided by the invention have the following beneficial effects: the first P-type doped region is formed in the P-type epitaxial layer below the first P-type contact region and serves as a potential barrier between the first P-type contact region and the photodiode, so that electrons emitted from the first metal pad are prevented from flowing to the photodiode, an electron potential well is formed between the first metal pad and the photodiode by the first P-type doped region and the P-type epitaxial layer, and the electrons emitted from the first metal pad are stored by the electron potential well, so that the dark current of a pixel unit of the CMOS image sensor is reduced, and the imaging quality is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A CMOS image sensor, comprising:
a substrate having a P-type epitaxial layer;
a photodiode formed in the P-type epitaxial layer;
the photodiode comprises a first P-type contact region formed in the P-type epitaxial layer, a first P-type doped region formed in the P-type epitaxial layer below the first P-type contact region, and a first metal pad formed above the first P-type contact region, wherein the first P-type contact region is positioned on one side of the photodiode, and an electron potential well is formed between the first metal pad and the photodiode through the first P-type doped region and the P-type epitaxial layer.
2. The CMOS image sensor of claim 1, further comprising a second P-type contact region formed in the P-type epitaxial layer, a second P-type doped region formed in the P-type epitaxial layer below the second P-type contact region, and a second metal pad formed above the second P-type contact region, the second P-type contact region being on the other side of the photodiode, an electron well being formed between the second metal pad and the photodiode through the second P-type doped region and the P-type epitaxial layer.
3. The CMOS image sensor of claim 2, further comprising a shallow trench isolation structure surrounding the photodiode and a P-type isolation layer disposed below the shallow trench isolation structure, wherein the second P-type doped region is located in a P-type epitaxial layer outside the shallow trench isolation structure surrounding the photodiode.
4. The CMOS image sensor of claim 3, wherein the doping concentration of the first and second P-type doped regions is 6 x 1017/cm3～5×1018/cm3。
5. The CMOS image sensor of claim 1, further comprising a P-type well region formed in the P-type epitaxial layer, a heavily N-doped region formed in the P-type well region, and a third metal pad over the heavily N-doped region, the heavily N-doped region serving as a source terminal of a reset transistor of the CMOS image sensor or a drain terminal of a transfer transistor of the CMOS image sensor.
6. The CMOS image sensor of claim 1, further comprising a reset transistor, wherein the first P-type contact region is located in a P-type epitaxial layer on a side of a drain of the reset transistor.
7. The CMOS image sensor of claim 6, wherein the first P-type contact region is less than or equal to 0.5 microns from a drain terminal of the reset transistor.
8. The CMOS image sensor of any one of claims 1 to 7, wherein said CMOS image sensor is a backside illuminated CMOS image sensor.
9. A method of fabricating a CMOS image sensor, comprising:
providing a substrate, wherein the substrate is provided with a P-type epitaxial layer;
forming a photodiode, a first P-type contact region and a first P-type doped region in the P-type epitaxial layer, forming a first metal pad above the first P-type contact region, wherein the first P-type contact region is positioned at one side of the photodiode, and forming an electron potential well between the first metal pad and the photodiode through the first P-type doped region and the P-type epitaxial layer.
10. The method of manufacturing a CMOS image sensor according to claim 9, further comprising:
forming a second P-type contact region and a second P-type doped region in the P-type epitaxial layer, wherein the second P-type contact region is positioned above the second P-type doped region, and a second metal pad is formed above the second P-type contact region;
the first P-type contact region and the second P-type contact region are formed simultaneously, the first P-type doped region and the second P-type doped region are formed simultaneously, and an electron potential well is formed between the second metal pad and the photodiode through the second P-type doped region and the P-type epitaxial layer.
CN202111657644.4A 2021-12-30 2021-12-30 CMOS image sensor and method of manufacturing the same Pending CN114256283A (en)

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