CN114256279A - Packaging method of CIS chip - Google Patents

Packaging method of CIS chip Download PDF

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Publication number
CN114256279A
CN114256279A CN202111528175.6A CN202111528175A CN114256279A CN 114256279 A CN114256279 A CN 114256279A CN 202111528175 A CN202111528175 A CN 202111528175A CN 114256279 A CN114256279 A CN 114256279A
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CN
China
Prior art keywords
chip
cis
packaging
substrate
cis chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111528175.6A
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Chinese (zh)
Inventor
蔡小虎
温建新
叶红波
史海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Original Assignee
Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai IC R&D Center Co Ltd, Shanghai IC Equipment Material Industry Innovation Center Co Ltd filed Critical Shanghai IC R&D Center Co Ltd
Priority to CN202111528175.6A priority Critical patent/CN114256279A/en
Publication of CN114256279A publication Critical patent/CN114256279A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C39/00—Shaping by casting, i.e. introducing the moulding material into a mould or between confining surfaces without significant moulding pressure; Apparatus therefor
    • B29C39/02—Shaping by casting, i.e. introducing the moulding material into a mould or between confining surfaces without significant moulding pressure; Apparatus therefor for making articles of definite length, i.e. discrete articles
    • B29C39/10—Shaping by casting, i.e. introducing the moulding material into a mould or between confining surfaces without significant moulding pressure; Apparatus therefor for making articles of definite length, i.e. discrete articles incorporating preformed parts or layers, e.g. casting around inserts or for coating articles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C39/00—Shaping by casting, i.e. introducing the moulding material into a mould or between confining surfaces without significant moulding pressure; Apparatus therefor
    • B29C39/22—Component parts, details or accessories; Auxiliary operations
    • B29C39/26—Moulds or cores
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention provides a method for packaging a CIS chip, which comprises the steps of attaching the CIS chip to a substrate; attaching a cover plate to a photosensitive area of the CIS chip; the bonding wire is used for realizing the connection between the bonding pad and the pin; covering the die on the substrate, and placing the CIS chip and the pins in a die position; injecting glue or plastic packaging material into the mold position to cover the exposed chip position surface, the bonding wire and the exposed CIS chip surface in the mold position; the method comprises the steps of removing a mould, then uncovering a film and picking up a wafer to complete packaging of the CIS chip, wherein the substrate is flat, removing a platform support structure, covering the mould on the substrate, placing the CIS chip and pins in a mould position, injecting glue or plastic package material into the mould position to cover the exposed chip position surface, bonding wires and the exposed CIS chip surface in the mould position, removing a cavity, improving the overall bonding force, forming thinning marks on the boundary of the chip position, and avoiding thick-path cutting, thereby improving the warping.

Description

Packaging method of CIS chip
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging method of a CIS chip.
Background
Fig. 1 is a schematic diagram of a package structure in the prior art. Fig. 2 is a flow chart of a prior art package. As shown in fig. 1, the package 100 is generally frame-shaped, and the chip can be connected to the bottom surface of the package 100 by silver paste during packaging. A plurality of bonding pads are disposed on the peripheral edge of the surface of the chip 102, and a plurality of leads 101 are correspondingly disposed on the peripheral edge of the bottom surface of the package 100 around the chip 102. The bond pads and corresponding leads 101 are connected by bond wires 103, and a glass cover plate 104 is mounted over the package 100.
As shown in fig. 2, the conventional packaging process includes chip thinning, dicing, mounting, bonding, and glass packaging, and applies the package 100 shown in fig. 1 to form the package structure shown in fig. 1.
In the above packaging Technology, the frame has a stand, a cavity, etc., the whole bonding force is poor, the bonding wire is suspended and easily broken, and if a single tube shell is adopted, the unit price is high, the die sinking cost is large, and if a long substrate is adopted, the cutting stress is large, the warpage is easily caused, and the subsequent Surface Mount Technology (SMT) process is affected.
Therefore, there is a need to provide a novel method for packaging a CIS chip to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a packaging method of a CIS chip, which reduces cavities, improves the integral bonding force, and does not need thick cutting, thereby improving the warping.
In order to achieve the above object, the method for packaging a CIS chip according to the present invention includes:
providing a CIS chip, a cover plate, a substrate and a mold, wherein a plurality of bonding pads are formed on the CIS chip, the substrate is in a flat plate shape, at least one chip position matched with the CIS chip is arranged on the substrate, thinning marks are formed on the boundary of the chip position, pins corresponding to the bonding pads one by one are formed on the chip position, the mold is in a flat plate shape, a mold position penetrating through the mold is formed on the mold, the shape of the mold position is matched with that of the chip position, and the thickness of the mold is larger than that of the CIS chip;
mounting the CIS chip on the substrate;
attaching the cover plate to a photosensitive area of the CIS chip;
the bonding wires are used for realizing the connection between the bonding pads and the pins;
covering the die on the substrate, and placing the CIS chip and the pins in the die position;
injecting glue or plastic packaging materials into the mould position so as to cover the exposed chip position surface, the bonding wires and the exposed CIS chip surface in the mould position;
and removing the die, and then carrying out film uncovering and sheet picking to finish the packaging of the CIS chip.
The packaging method has the beneficial effects that: the base plate is flat, a table support structure is removed, the base plate is covered with the die, the CIS chip and the pins are arranged in the die position, glue or plastic package materials are injected into the die position to cover the exposed chip position surface in the die position, the bonding wires and the exposed CIS chip surface, the cavity is removed, the overall bonding force is improved, thinning marks are formed on the boundary of the chip position, thick cutting is not needed, and therefore warping is improved.
Optionally, a chip pasting position adapted to the CIS chip is disposed on the chip position, the pin is located outside the chip pasting position, and the CIS chip is pasted on the substrate, including: dispensing glue on the chip pasting position, and then covering the CIS chip on the chip pasting position. The beneficial effects are that: the position of the CIS chip is conveniently and accurately fixed.
Optionally, the connecting the pad and the pin by a bonding wire includes: and the bonding pad is connected with the pin through a bonding wire by a routing process.
Optionally, the method for packaging a CIS chip further includes: and forming a plurality of CIS chips on the semiconductor substrate, and forming independent CIS chips by scribing.
Optionally, the method for packaging a CIS chip further includes: forming a plurality of CIS chips on a semiconductor substrate, thinning the substrate of the CIS chips, and then forming a plurality of independent CIS chips by scribing.
Optionally, the injecting glue or molding compound into the mold position to cover the exposed chip position surface, the bonding wire, and the exposed CIS chip surface in the mold position includes: and injecting glue or plastic packaging materials into the mould position so as to cover the exposed surface of the chip position, the bonding wires and the exposed surface of the CIS chip in the mould position until only the upper surface of the cover plate is exposed.
Optionally, the method for packaging a CIS chip further includes: and forming the thinning trace at the boundary of the chip position by etching or punching.
Optionally, the method for packaging a CIS chip further includes: and forming a mould position penetrating through the mould on the mould through etching.
Optionally, the material of the cover plate is glass.
Optionally, the material of the substrate is ceramic.
Drawings
FIG. 1 is a diagram of a prior art package structure;
FIG. 2 is a schematic diagram of a packaging process of the prior art;
FIG. 3 is a schematic view of a substrate according to some embodiments of the present invention;
FIG. 4 is a schematic diagram of a mold in accordance with some embodiments of the invention;
FIG. 5 is a flow chart of a CIS chip packaging method of the present invention;
FIG. 6 is a cross-sectional view of the structure formed after step S1 according to the present invention;
FIG. 7 is a cross-sectional view of the structure formed after step S2 according to the present invention;
FIG. 8 is a cross-sectional view of the structure formed after step S3 according to the present invention;
FIG. 9 is a cross-sectional view of the structure formed after step S4 according to the present invention;
FIG. 10 is a cross-sectional view of the structure formed after step S5 according to the present invention;
FIG. 11 is a cross-sectional view of the structure after the mold has been removed in step S6;
fig. 12 is a cross-sectional view of a CIS chip package structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In view of the problems in the prior art, an embodiment of the present invention provides a substrate, which is a flat plate and includes at least one chip site, where the chip site is provided with pins, and a boundary of the chip site is provided with thinning marks. The thinning mark is formed by etching or stamping the substrate, so that the chip position is taken down from the substrate.
In some embodiments, a chip attach site is disposed on the chip site, and the pin is located outside the chip attach site.
In some embodiments, the substrate has a separate trace therein, and the trace is connected to the outside of the substrate to enable external pin extraction.
Fig. 3 is a schematic structural diagram of a substrate in some embodiments of the invention. Referring to fig. 3, the substrate 200 is flat, 6 chip positions 201 matched with the CIS chip are arranged on the substrate 200, pins 202 corresponding to bonding pads of the CIS chip are arranged on the chip positions 201, and thinning marks 203 are arranged on the boundary of the chip positions.
Referring to fig. 3, a chip pasting position 204 adapted to a CIS chip is disposed on the chip position 201, and the pin 202 is disposed outside the chip pasting position 204 and surrounds the chip pasting position 204.
The invention also provides a mould which is flat, a mould position penetrating through the mould is formed on the mould, and the shape of the mould position is matched with that of the chip position. Wherein the mold sites are formed on the mold by etching.
FIG. 4 is a schematic diagram of a mold in accordance with some embodiments of the invention. Referring to fig. 4, the mold 300 is shaped like a flat plate, a mold site 301 penetrating through the mold is formed on the mold 300, the shape of the mold site 301 is adapted to the chip site, and the thickness of the mold 300 is greater than that of the CIS chip.
In some embodiments, the die site forms a shape on a side of the die that is substantially the same size as the shape formed by the thinning mark of one of the die sites.
Fig. 5 illustrates a method for packaging a CIS chip according to the present invention. Referring to fig. 5, the method of packaging the CIS chip includes the steps of:
s0: providing a CIS chip, a cover plate, a substrate and a mold, wherein a plurality of bonding pads are formed on the CIS chip, the substrate is in a flat plate shape, at least one chip position matched with the CIS chip is arranged on the substrate, thinning marks are formed on the boundary of the chip position, pins corresponding to the bonding pads one by one are formed on the chip position, the mold is in a flat plate shape, a mold position penetrating through the mold is formed on the mold, the shape of the mold position is matched with that of the chip position, and the thickness of the mold is larger than that of the CIS chip;
s1: mounting the CIS chip on the substrate;
s2: attaching the cover plate to a photosensitive area of the CIS chip;
s3: the bonding wires are used for realizing the connection between the bonding pads and the pins;
s4: covering the die on the substrate, and placing the CIS chip and the pins in the die position;
s5: injecting glue or plastic packaging materials into the mould position so as to cover the exposed chip position surface, the bonding wires and the exposed CIS chip surface in the mould position;
s6: and removing the die, and then carrying out film uncovering and sheet picking to finish the packaging of the CIS chip.
In some embodiments, the peeling film comprises a peeling back film serving as a support, and the picking up includes placing the packaged CIS chip into a corresponding container. Wherein the back film is the substrate.
In some embodiments, a semiconductor substrate, such as a silicon substrate, may be used, although the invention is not limited thereto. A plurality of CIS chips are formed on a silicon substrate.
In some embodiments, the method of packaging a CIS chip further includes: and forming a plurality of CIS chips on the semiconductor substrate, and forming independent CIS chips by scribing.
In some embodiments, the method of packaging a CIS chip further includes: forming a plurality of CIS chips on a semiconductor substrate, thinning the substrate of the CIS chips, and then forming a plurality of independent CIS chips by scribing.
In some embodiments, a chip attach position adapted to the CIS chip is disposed on the chip position, the pin is located outside the chip attach position, and attaching the CIS chip to the substrate includes: dispensing glue on the chip pasting position, and then covering the CIS chip on the chip pasting position.
FIG. 6 is a cross-sectional view of the structure formed after step S1. Referring to fig. 6, the CIS chip 400 is attached to the substrate 200 through a dispensing and mounting process.
Fig. 7 is a cross-sectional view of the structure formed after step S2 according to the present invention. Referring to fig. 7, the cover plate 401 is attached to a photosensitive region on the upper side of the CIS chip 400, wherein the cover plate 401 is made of glass.
In some embodiments, the connecting the pad and the pin by a bonding wire includes: and the bonding pad is connected with the pin through a bonding wire by a routing process. Specifically, the wire bonding process comprises the following steps: melting one end of the bonding wire into a spherical shape by heating, then attaching the melted spherical end of the bonding wire to the bonding pad, and applying pressure and ultrasound to form a first welding point, namely realizing the connection of the bonding wire and the bonding pad; drawing the bonding wire, attaching the middle part of the bonding wire to the pin, and applying pressure and ultrasound to form a second welding point, namely realizing the connection of the bonding wire and the pin; and cutting off the rest bonding wires to finish the connection of the bonding pad and the pin through the bonding wires.
In some embodiments, the bonding wire is a gold wire or an aluminum wire.
Fig. 8 is a cross-sectional view of the structure formed after step S3 according to the present invention. Referring to fig. 8, the pad 402 and the lead 202 are connected by the bonding wire 403.
Fig. 9 is a cross-sectional view of the structure formed after step S4 according to the present invention. Referring to fig. 9, the mold 300 covers the upper side of the substrate 200, and the sidewall of the mold 301 is aligned with the thinning mark 203.
Some embodiments specifically include: and injecting glue or plastic packaging materials into the mould position so as to cover the exposed surface of the chip position, the bonding wires and the exposed surface of the CIS chip in the mould position until only the upper surface of the cover plate is exposed.
Fig. 10 is a cross-sectional view of the structure formed after step S5 according to the present invention. Referring to fig. 10, the molding compound 302 in the mold site 301 covers the exposed surface of the chip site (not shown), the bonding wires 403, and the exposed surface of the CIS chip 400, and the uppermost side of the molding compound 302 is flush with the upper surface of the cover plate 401.
FIG. 11 is a cross-sectional view of the structure formed after the mold is removed in step S6. Fig. 11 is different from fig. 10 in that the mold 300 is removed in fig. 11, thereby forming a CIS chip encapsulation structure integrally coupled with the substrate.
Fig. 12 is a cross-sectional view of a CIS chip package structure according to the present invention. And applying opposite directions and vertical force to the surface of the substrate 200 outside the CIS chip packaging structure and the thinning mark 203 respectively, wherein the substrate 200 at the thinning mark 203 is very thin, so that the substrate 200 can be broken and separated at the thinning mark 203, and the CIS chip packaging structure and the substrate 200 are integrally separated to form an independent CIS chip packaging structure, as shown in fig. 12.
In some embodiments, the cover plate is made of glass, and the substrate is made of ceramic.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (10)

1. A method for packaging a CIS chip, comprising:
providing a CIS chip, a cover plate, a substrate and a mold, wherein a plurality of bonding pads are formed on the CIS chip, the substrate is in a flat plate shape, at least one chip position matched with the CIS chip is arranged on the substrate, thinning marks are formed on the boundary of the chip position, pins corresponding to the bonding pads one by one are formed on the chip position, the mold is in a flat plate shape, a mold position penetrating through the mold is formed on the mold, the shape of the mold position is matched with that of the chip position, and the thickness of the mold is larger than that of the CIS chip;
mounting the CIS chip on the substrate;
attaching the cover plate to a photosensitive area of the CIS chip;
the bonding wires are used for realizing the connection between the bonding pads and the pins;
covering the die on the substrate, and placing the CIS chip and the pins in the die position;
injecting glue or plastic packaging materials into the mould position so as to cover the exposed chip position surface, the bonding wires and the exposed CIS chip surface in the mould position;
and removing the die, and then carrying out film uncovering and sheet picking to finish the packaging of the CIS chip.
2. The method for packaging a CIS chip according to claim 1, wherein the chip site is provided with a chip pasting site adapted to the CIS chip, the pin is located outside the chip pasting site, and the attaching of the CIS chip to the substrate comprises:
dispensing glue on the chip pasting position, and then covering the CIS chip on the chip pasting position.
3. The packaging method of the CIS chip according to claim 1, wherein the connection of the pad and the lead by the bonding wire comprises:
and the bonding pad is connected with the pin through a bonding wire by a routing process.
4. The method of packaging a CIS chip according to claim 1, further comprising: and forming a plurality of CIS chips on the semiconductor substrate, and forming independent CIS chips by scribing.
5. The method of packaging a CIS chip according to claim 1, further comprising: forming a plurality of CIS chips on a semiconductor substrate, thinning the substrate of the CIS chips, and then forming a plurality of independent CIS chips by scribing.
6. The method for packaging a CIS chip according to claim 1, wherein the step of injecting or molding a compound into the mold position to cover the exposed chip position surface, the bonding wires and the exposed CIS chip surface in the mold position comprises:
and injecting glue or plastic packaging materials into the mould position so as to cover the exposed surface of the chip position, the bonding wires and the exposed surface of the CIS chip in the mould position until only the upper surface of the cover plate is exposed.
7. The method of packaging a CIS chip according to claim 1, further comprising:
and forming the thinning trace at the boundary of the chip position by etching or punching.
8. The method of packaging a CIS chip according to claim 1, further comprising:
and forming a mould position penetrating through the mould on the mould through etching.
9. The method for packaging a CIS chip according to claim 1, wherein the cover plate is made of glass.
10. The method for packaging a CIS chip according to claim 1, wherein the substrate is made of ceramic.
CN202111528175.6A 2021-12-14 2021-12-14 Packaging method of CIS chip Pending CN114256279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111528175.6A CN114256279A (en) 2021-12-14 2021-12-14 Packaging method of CIS chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111528175.6A CN114256279A (en) 2021-12-14 2021-12-14 Packaging method of CIS chip

Publications (1)

Publication Number Publication Date
CN114256279A true CN114256279A (en) 2022-03-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111528175.6A Pending CN114256279A (en) 2021-12-14 2021-12-14 Packaging method of CIS chip

Country Status (1)

Country Link
CN (1) CN114256279A (en)

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