CN114256147A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN114256147A CN114256147A CN202011003762.9A CN202011003762A CN114256147A CN 114256147 A CN114256147 A CN 114256147A CN 202011003762 A CN202011003762 A CN 202011003762A CN 114256147 A CN114256147 A CN 114256147A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The embodiment of the application provides a preparation method of a semiconductor structure, relates to the technical field of microelectronics, and can form a P-type heavily doped nanowire or an N-type doped nanowire under a process environment at a lower temperature, so that the cost is lower. The preparation method of the semiconductor structure comprises the following steps: forming a base material layer, and forming at least one groove on the surface of the base material layer; forming a catalytic metal in the trench; depositing a doped amorphous precursor on the surface of the substrate layer at a position including the trench, the doped amorphous precursor contacting the catalytic metal; and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form the doped nanowire along the way.
Description
Technical Field
The application relates to the technical field of microelectronics, in particular to a semiconductor structure preparation method.
Background
With the development of microelectronic technology, crystalline semiconductor nanowires can be stacked and arranged due to their extremely low defect states and good charge transport capabilities, and thus become the mainstream choice of semiconductor technology. However, the current methods for doping nanowires, such as ion implantation, molecular diffusion, etc., all require high-temperature annealing (>600 ℃) to activate the doping atoms, which is costly.
Disclosure of Invention
The technical scheme provides a semiconductor structure preparation method, which can form a P-type heavily doped nanowire or an N-type doped nanowire under a low-temperature process environment and is low in cost.
In a first aspect, a technical solution of the present application provides a method for manufacturing a semiconductor structure, including: forming a base material layer, and forming at least one groove on the surface of the base material layer; forming a catalytic metal in the trench; depositing a doped amorphous precursor on the surface of the substrate layer at a position including the trench, the doped amorphous precursor contacting the catalytic metal; and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form the doped nanowire along the way.
In one possible embodiment, the process of forming the substrate layer and forming the at least one trench on the surface of the substrate layer includes: forming a substrate layer, and forming at least one groove with the depth of d and the width of w on the surface of the substrate layer, wherein d is more than or equal to 50nm and less than or equal to 1 mu m, and w is more than or equal to 1 mu m and less than or equal to 100 mu m.
In one possible embodiment, the process of forming the catalytic metal in the trench includes: depositing catalytic metal with the thickness h1 in the groove, wherein h is more than or equal to 5nm and less than or equal to 200 nm.
In one possible embodiment, after forming the catalytic metal in each trench, the method further includes: and (3) treating the catalytic metal by using plasma in an environment with the temperature above the melting point of the catalytic metal, so that an oxide layer on the surface of the catalytic metal is removed, and the catalytic metal is converted into the catalytic metal in a discrete liquid state.
In one possible embodiment, the process of depositing the doped amorphous precursor on the surface of the substrate layer at a location including the trench comprises: and under the environment of the temperature below the melting point of the catalytic metal, depositing a doped amorphous precursor with the thickness of h1 at the position including the groove on the surface of the substrate layer, wherein h2 is more than or equal to 10nm and less than or equal to 200 nm.
In one possible embodiment, the annealing process of the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding trench and absorbs the doped amorphous precursor, and the doped nanowires are formed along the substrate layer, includes:
and annealing the substrate layer on which the catalytic metal and the doped amorphous precursor are formed at a temperature above the melting point of the catalytic metal and in a non-oxygen environment, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form the doped nanowire along the way.
In one possible embodiment, the catalytic metal is an alloy of one or more of the following metals: indium, tin, bismuth, gallium, and aluminum.
In one possible embodiment, the doped amorphous precursor is a heterogeneous stack of one or more of the following: doped amorphous silicon, doped amorphous germanium and doped amorphous carbon.
In one possible embodiment, the doping element in the doped amorphous precursor is phosphorus or boron.
In one possible embodiment, the doped nanowire is an N-type doped nanowire or a P-type heavily doped nanowire.
In one possible embodiment, the nanowire includes two end portions and an intermediate portion between the two end portions, and after forming the doped nanowire, the method further includes:
forming a source metal covering one end portion of the nanowire, the source metal being connected to one end portion of the nanowire, forming a drain metal covering the other end portion of the nanowire, the drain metal being connected to the other end portion of the nanowire;
forming a gate dielectric layer covering the middle part of the nanowire;
after the gate dielectric layer is formed, the method further comprises the following steps: and forming a gate metal covering the middle part of the nanowire, wherein a gate dielectric layer is positioned between the nanowire and the gate metal.
The preparation method can directly grow the N-type doped or P-type heavily doped nanowire without doping process, and the process temperature in the nanowire growth process is lower and can not exceed 600 ℃, so that the compatibility is higher, the cost is low, in addition, because the nanowire grows along the groove, the growth direction of the nanowire can be controlled in the whole process, the appearance of the nanowire is controlled, and the doping atoms in the nanowire are uniformly distributed, thus the preparation method is suitable for high-performance semiconductor devices.
Drawings
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 2a is a schematic structural diagram of a semiconductor structure after a substrate layer is formed in a method for manufacturing the semiconductor structure according to an embodiment of the present disclosure;
FIG. 2b is a schematic diagram of the structure of FIG. 2a after forming a trench;
FIG. 2c is a schematic diagram of the structure of FIG. 2b after deposition of a catalytic metal;
FIG. 2d is a schematic diagram of the structure of FIG. 2c after plasma treatment;
FIG. 2e is a schematic diagram of the structure of FIG. 2d after deposition of a doped amorphous precursor;
FIG. 2f is a schematic diagram of the structure of FIG. 2e after annealing to form doped nanowires;
FIG. 3 is a schematic cross-sectional view of each of FIGS. 2a to 2 f;
FIG. 4 is a schematic structural diagram of another trench in the embodiment of the present application;
FIG. 5 is a flow chart of another method of fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 6a is a schematic diagram of the structure of FIG. 2f after source and drain metal deposition;
FIG. 6b is a schematic diagram illustrating the structure of FIG. 6a after a gate dielectric layer is deposited thereon;
fig. 6c is a schematic structural diagram of the structure in fig. 6b after gate metal deposition.
Detailed Description
The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.
Before describing the embodiments of the present application, a description will be given of a problem finding process of the related art. In the process of doping the nanowire to form the N-type and P-type structures, the doping process can be performed at a high temperature, but for flexible electronic products, most of the adopted substrates are Polyimide (PI) materials, the maximum temperature which can be borne by the PI materials is about 400 ℃, and the temperature required by the current doping process exceeds 600 ℃, so that the compatibility of the method for forming the doped nanowire through the doping process is poor. Another method for obtaining doped nanowires is to directly grow doped nanowires, but the doped nanowires are directly grown by Vapor-liquid-solid (VLS) growth, which, on one hand, is difficult to control the growth direction of the nanowires, and on the other hand, may generate an amorphous layer on the sidewalls of the nanowires, affecting the quality of the nanowires. In addition, only P-type lightly doped nanowires can be obtained through other growth modes, and P-type heavily doped nanowires or N-type doped nanowires cannot be obtained through growth. In order to solve the above problems, the inventors provide the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are explained below.
An embodiment of the present application provides a method for manufacturing a semiconductor structure, as shown in fig. 1, fig. 2a to fig. 2f, and fig. 3, the method including:
the trench 11 may be formed on the surface of the substrate layer 1 by photolithography and etching.
103, depositing a doped amorphous precursor 3 at a position including the groove 11 on the surface of the substrate layer 1, wherein the doped amorphous precursor 3 contacts the catalytic metal 2;
the doped amorphous precursor 3 in the embodiment of the present application refers to an amorphous precursor 3 with a doping concentration different from 0. The doped amorphous precursor 3 may be, for example, amorphous silicon doped with phosphorus or boron, the doped amorphous precursor 3 at least covers the trench 11 and the catalytic metal 2 in the trench 11, for example, a whole layer of the doped amorphous precursor 3 may be formed on the surface of the substrate layer 1, and it should be noted that, in the embodiment of the present application, the order of the step 102 and the step 103 is not limited, for example, the catalytic metal 2 may be deposited first, and then the doped amorphous precursor 3 may be deposited; it is also possible to deposit the doped amorphous precursor 3 first and then the catalytic metal 2 as long as the catalytic metal 2 contacts the doped amorphous precursor 3 in the trench 11.
The annealing process in step 104 may be performed in a non-oxygen environment, and the annealing temperature is above the melting point of the catalytic metal 2, for example, 300 ℃, at which time the catalytic metal 2 droplet melts and absorbs the nearby doped amorphous precursor 3, and when the silicon atom concentration reaches a supersaturated concentration, the doped nanowire 4 is precipitated at the rear end of the catalytic metal 2 droplet, and the doped nanowire 4 grows along the trench 11. It should be noted that the cross-sectional views of fig. 2a to 2e in fig. 3 are schematic cross-sectional structures along AA ', and the cross-sectional view of fig. 2f in fig. 3 is a schematic cross-sectional structure along BB'. Wherein the doping concentration and type of the nanowire 4 are related to the doping concentration and type of the amorphous precursor, for example, if the N-type doped amorphous precursor 3 is used, the N-type doped nanowire 4 can be grown, and if the P-type heavily doped amorphous precursor 3 is used, the P-type lightly doped nanowire 4 can be grown. It should be noted that, in fig. 2f, only one nanowire 4 in each trench 11 is illustrated, and in fig. 3, two nanowires 4 in each trench 11 are illustrated, and the number of nanowires 4 in one trench 11 is not limited in the embodiment of the present application, when the width of the trench 11 is large, two nanowires 4 may be formed therein along two sidewalls of the trench 11, and when the width of the trench 11 is small, only one nanowire 4 may be formed in one trench 11.
According to the preparation method of the semiconductor structure in the embodiment of the application, the catalytic metal and the doped amorphous precursor are deposited in the groove through the groove, then annealing is carried out to enable the catalytic metal to move along the groove and absorb the doped amorphous precursor, and the doped nanowire extending along the groove is grown.
It is emphasized that, by the semiconductor structure preparation method of the embodiment of the present application, the corresponding heavily doped nanowires can be grown by absorbing the amorphous precursor, while if the intrinsic amorphous precursor is used, although the nanowires can be grown by absorbing the catalytic metal, only lightly doped nanowires can be grown, and thus the semiconductor structure preparation method of the embodiment of the present application has stronger compatibility and can be used for manufacturing more types of nanowires.
In addition, the above-mentioned toolsIn the process, if the doped amorphous precursor is changed to be the intrinsic amorphous precursor, the P-type atoms In the catalytic metal, such as In metal, are absorbed during the growth process of the nanowire, so that the formed nanowire is the P-type lightly doped nanowire, and on the basis, if the conventional VLS process is used for reference, the doped nanowire is easily conceived to be In the doping gas atmosphere (such as the P-doped PH)3Atmosphere) growth of nanowires, but in a practical process, PH3The reaction with catalytic metal to generate stable InP can not realize the doping of the nano-wire and stop the growth of the nano-wire.
In a possible embodiment, the step 101 of forming the substrate layer 1 and forming the at least one groove 11 on the surface of the substrate layer 1 includes: forming a substrate layer 1, and forming at least one groove 11 with the depth d and the width w on the surface of the substrate layer 1, wherein d is more than or equal to 50nm and less than or equal to 1 mu m, and w is more than or equal to 1 mu m and less than or equal to 100 mu m. For example, a trench 11 having a depth d of 100nm and a width w of 2 μm is formed on the surface of the base material layer 1 made of a silicon dioxide material by photolithography. The process of forming the trench 11 may adopt dry Etching processes such as photolithography, Inductively Coupled Plasma (ICP) Etching, Reactive Ion Etching (RIE) Etching, and the like, or adopt an alkaline Etching system such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and the like, or an acidic Etching system such as hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3+ CH3COOH), and the like, or a wet Etching process of a system such as ethylenediamine Pyrocatechol (Ethylene Diamine Pyrocatechol), and the like.
In one possible embodiment, the step 102 of forming the catalytic metal 2 in the trench 11 includes: depositing the catalytic metal 2 with the thickness h1 in the groove 11, wherein h is more than or equal to 5nm and less than or equal to 200 nm. For example, the position to be deposited of the catalytic metal 2 is first defined by a photolithography process, and then a metal of, for example, 20nm is deposited at a certain position of the trench 11 by a thermal evaporation method.
In a possible embodiment, after the step 103 of forming the catalytic metal 2 in each trench 11, the method further includes: in an environment at a temperature above the melting point of the catalytic metal 2,the catalytic metal 2 is treated with plasma so that the oxide layer on the surface of the catalytic metal 2 is removed and the catalytic metal 2 is converted into the catalytic metal 2 in a separate liquid state. For example, after step 102, the substrate layer 1 on which the catalytic metal 2 is deposited is first placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus, heated to a temperature higher than the melting point of the catalytic metal 2 (about 200 ℃), and H is used2The plasma treats the surface oxide layer of the catalytic metal 2, for example, in a range of 3min to 20min, and converts the catalytic metal 2 into discrete catalytic metal 2 droplets in, for example, 5 minutes and 30 seconds.
In one possible embodiment, the step 103 of depositing the doped amorphous precursor 3 on the surface of the substrate layer 1 at the position including the trench 11 comprises: under the environment of the temperature below the melting point of the catalytic metal 2, depositing a doped amorphous precursor 3 with the thickness h1 at the position including the groove 11 on the surface of the substrate layer 1, wherein h2 is more than or equal to 10nm and less than or equal to 200 nm. For example, a doped amorphous precursor 3, for example 15nm, is deposited at a temperature of around 100 ℃.
In one possible embodiment, the step 104 of annealing the substrate layer 1 formed with the catalytic metal 2 and the doped amorphous precursor 3, so that the catalytic metal 2 moves along the corresponding trench and absorbs the doped amorphous precursor 3, and the doped nanowires 4 are formed along the way, includes: the substrate layer 1 on which the catalytic metal 2 and the doped amorphous precursor 3 are formed is annealed at a temperature higher than the melting point of the catalytic metal 2 and in a non-oxygen atmosphere, so that the catalytic metal 2 moves along the corresponding groove 11 and absorbs the doped amorphous precursor 3 to form the doped nanowire 4 along the way.
In one possible embodiment, the catalytic metal 2 is an alloy of one or more of the following metals: indium, tin, bismuth, gallium, and aluminum.
In one possible embodiment, the doped amorphous precursor 3 is a heterogeneous stack of one or more of the following: doped amorphous silicon, doped amorphous germanium and doped amorphous carbon. For example, if the doped amorphous precursor 3 is doped amorphous silicon, the nanowire 4 prepared by the above method is a doped silicon nanowire; if the doped amorphous precursor 3 is doped amorphous germanium, the nanowire 4 prepared by the method is the doped germanium nanowire 4; if the doped amorphous precursor 3 is a heterogeneous stack of doped amorphous germanium and doped amorphous silicon, the nanowire 4 prepared by the above method is a heterogeneous stack nanowire 4 of doped silicon and germanium.
In one possible embodiment, the doping element in the doped amorphous precursor 3 is phosphorus or boron, i.e. the doped amorphous precursor 3 may be an N-type doped amorphous precursor 3, to grow N-type doped nanowires 4; the doped amorphous precursor 3 can also be a P-type doped amorphous precursor 3 to grow a P-type heavily doped nanowire 4.
It should be noted that, in the above embodiments, the trench 11 is a straight-line structure, but the structure of the trench 11 is not limited in the embodiments of the present application, and since the doped nanowire 4 grows along the trench 11, the structure of the trench 11 determines the structure of the doped nanowire 4, as shown in fig. 4, in other realizable embodiments, the trench 11 has a bent or curved structure, and correspondingly, the doped nanowire 4 growing along the trench 11 also has a corresponding bent or curved structure, so as to meet the requirement on the morphology of the doped nanowire 4.
In the above embodiment, a process of growing a nanowire by the semiconductor structure manufacturing method provided in the embodiment of the present application is described, and a process of manufacturing a semiconductor device based on the semiconductor structure manufacturing method provided in the embodiment of the present application is further described below, in a possible implementation manner, as shown in fig. 2f, fig. 5, and fig. 6a to fig. 6c, the nanowire 4 includes two end portions 41 and an intermediate portion 42 located between the two end portions 41, and after forming the doped nanowire 4, the method further includes:
step 201, forming a source metal 51 covering one end portion 41 of the nanowire 4, wherein the source metal 51 is connected to the one end portion 41 of the nanowire 4, forming a drain metal 52 covering the other end portion 41 of the nanowire 4, and the drain metal 52 is connected to the other end portion 41 of the nanowire 4;
Specifically, after step 203, in order to facilitate the top wiring of the overall structure, the gate dielectric layer 6 above the source metal 51 and the drain metal 52 may be further etched by an etching process, so as to expose the source metal 51 and the drain metal 52 on the upper surface of the overall structure, so as to facilitate the electrical connection between the transistor and other devices. After the above steps 101 to 203, a transistor structure is formed, in which the doped nanowire 4 is used as a channel of a transistor, and the embodiment of the present application is not limited to the specific structure of the transistor, for example, the structure shown in fig. 6c is a transistor with a top gate structure, but in other realizable implementations, a transistor with a bottom gate structure or a transistor with other structures may also be formed by using the generated doped nanowire 4 as a channel.
In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, and may mean that a exists alone, a and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. A method for fabricating a semiconductor structure, comprising:
forming a base material layer, and forming at least one groove on the surface of the base material layer;
forming a catalytic metal in the trench;
depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench, the doped amorphous precursor contacting the catalytic metal;
and annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form a doped nanowire along the way.
2. The method of claim 1,
the process of forming a substrate layer and forming at least one trench on a surface of the substrate layer includes:
forming a substrate layer, and forming at least one groove with the depth of d and the width of w on the surface of the substrate layer, wherein d is more than or equal to 50nm and less than or equal to 1 mu m, and w is more than or equal to 1 mu m and less than or equal to 100 mu m.
3. The method of claim 2,
the process of forming a catalytic metal in the trench includes:
and depositing catalytic metal with the thickness h1 in the groove, wherein h is more than or equal to 5nm and less than or equal to 200 nm.
4. The method of claim 3,
after forming the catalytic metal in each of the trenches, further comprising:
and under the environment of the temperature above the melting point of the catalytic metal, treating the catalytic metal by using plasma to remove an oxide layer on the surface of the catalytic metal and convert the catalytic metal into the catalytic metal in a discrete liquid state.
5. The method of claim 4,
the process of depositing a doped amorphous precursor on the surface of the substrate layer at a location including the trench comprises:
and under the environment of the temperature below the melting point of the catalytic metal, depositing a doped amorphous precursor with the thickness of h1 at the position including the groove on the surface of the substrate layer, wherein h2 is more than or equal to 10nm and less than or equal to 200 nm.
6. The method of claim 5,
the process of annealing the substrate layer formed with the catalytic metal and the doped amorphous precursor, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor, and the doped nanowire is formed along the way includes:
and annealing the substrate layer on which the catalytic metal and the doped amorphous precursor are formed at a temperature above the melting point of the catalytic metal and in a non-oxygen environment, so that the catalytic metal moves along the corresponding groove and absorbs the doped amorphous precursor to form doped nanowires along the way.
7. The method according to any one of claims 1 to 6,
the catalytic metal is an alloy of one or more of the following metals: indium, tin, bismuth, gallium, and aluminum.
8. The method according to any one of claims 1 to 6,
the doped amorphous precursor is a heterogeneous stack of one or more of: doped amorphous silicon, doped amorphous germanium and doped amorphous carbon.
9. The method of claim 8,
the doping element in the doped amorphous precursor is phosphorus or boron.
10. The method of claim 1,
the doped nanowire is an N-type doped nanowire or a P-type heavily doped nanowire.
11. The method according to any one of claims 1 to 6,
the nanowire comprises two end portions and an intermediate portion between the two end portions, and after forming the doped nanowire, further comprises:
forming a source metal covering one end portion of the nanowire, the source metal being connected to one end portion of the nanowire, forming a drain metal covering the other end portion of the nanowire, the drain metal being connected to the other end portion of the nanowire;
forming a gate dielectric layer covering the middle part of the nanowire;
after the gate dielectric layer is formed, the method further comprises the following steps: and forming a gate metal covering the middle part of the nanowire, wherein the gate dielectric layer is positioned between the nanowire and the gate metal.
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