CN114253588A - Method, device and storage medium for patching chip software - Google Patents
Method, device and storage medium for patching chip software Download PDFInfo
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- CN114253588A CN114253588A CN202210190114.1A CN202210190114A CN114253588A CN 114253588 A CN114253588 A CN 114253588A CN 202210190114 A CN202210190114 A CN 202210190114A CN 114253588 A CN114253588 A CN 114253588A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/656—Updates while running
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
Abstract
The application relates to the technical field of computers, and discloses a method for patching chip software, which comprises the following steps: setting the address of an original target function to be patched as a read protection address based on an ARM architecture of a reduced instruction set machine, and generating MPU interruption when a main program accesses the read protection address; the MPU interrupts and jumps to an interrupt processing program; the interrupt handler executes a patch function; the patch function executes back out of the interrupt handler. In the main program, only the address of the target function to be patched needs to be set as read protection, when the main program executes the target function, a storage protection mechanism of the chip is automatically triggered to generate MPU interruption, and the patch function can be executed in an interruption processing program, so that the execution of the patch function is realized. The application also discloses a device and a storage medium for patching the chip software.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method, an apparatus, and a storage medium for patching chip software.
Background
At present, when a new version chip is imported into an ARM (Advanced RISC Machine) architecture, a function library compiled based on the old version chip needs to be used, and a Non-Volatile memory (NVM) bottom function called by the function library cannot be directly run on the new version chip, and the NVM bottom function called by the function library must be functionally updated. In order to solve the problem of updating the NVM underlying function, the prior art discloses an SVC (supervisory Call, access management instruction) command mode, which is a mode of patching software and requires software or hardware to trigger an interrupt after executing an SVC instruction, and replace a target function in the interrupt.
In the process of implementing the embodiment of the present disclosure, there is a case that a function library provided by a third party does not have a reserved patch interface and does not support recompilation, and the SVC command mode cannot implement a patching mechanism for a software program or hardware that does not have a reserved patch interface.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a method for patching chip software, a device for software patching based on an ARM architecture MPU mechanism, and a storage medium for software patching based on the ARM architecture MPU mechanism by using an MPU (Memory Protection Unit) mechanism, wherein the MPU mechanism generates an interrupt by triggering access Protection of a program address, and can still realize function replacement without reserving a patch interface.
In some embodiments, the method comprises: setting the address of an original target function to be patched as a read protection address based on an ARM architecture of a reduced instruction set machine, and generating MPU interruption when a main program accesses the read protection address; the MPU interrupts and jumps to an interrupt processing program; the interrupt handler executes a patch function; the patch function executes back out of the interrupt handler.
In the main program, only the address of the target function to be patched needs to be set as read protection, when the main program executes the target function, a storage protection mechanism of the chip is automatically triggered to generate MPU interruption, and the patch function can be executed in an interruption processing program, so that the execution of the patch function is realized.
Optionally, the original objective function has no patch interface.
The MPU mechanism can still access the read protection address through the CPU to trigger MPU interruption under the condition that the target function has no patch interface, and the MPU mechanism is not limited by whether the patch interface exists or not.
Optionally, the read protection address is set as follows: the address of the original objective function to be patched is set to an MPU unreadable by the CPU in the program initialization stage.
In the program initialization stage, only the address of the original target function needing to be patched needs to be set as an unreadable MPU, and an MPU interrupt can be triggered in any other execution step of the program.
Optionally, the memory protection unit MPU interrupt is generated as follows: when the program is executed to the MPU which is unreadable by the CPU, the CPU read operation triggers the memory protection mechanism, generating an MPU interrupt.
The MPU interrupt can be triggered by the existing mechanism of CPU read operation in the ARM architecture without adding other functions.
Optionally, when the MPU generates an interrupt, the return address of the original target function and the parameters to be passed by the patch function are pushed into the stack.
Optionally, the interrupt handler executes a patch function, including: obtaining a return address of an original target function when the interruption is generated from a stack; acquiring parameters required to be transferred by the patch function from a stack; calling a patch function and transferring the parameters; and after the patch function calling is finished, skipping to the return address of the original target function.
The return address of the original target function is pushed into the stack, and before the patch function is called, the return address of the original target function is obtained from the stack, so that whether the currently executed patch function is the patch function called when the original target function is executed or not can be verified. Thus, the safety of calling the patch function is ensured.
Optionally, after the patch function executes to exit the interrupt handler, the patch function continues to execute subsequent codes of the original program.
After the patch is executed, the code specified by the return address of the original target function is executed.
In some embodiments, the apparatus comprises: a processor and a memory storing program instructions, the processor being configured to, when executing the program instructions, perform the above-described method of chip software patching.
In some embodiments, an apparatus for chip software patching as described above is included.
In some embodiments, program instructions are stored which, when executed, perform the above-described method of chip software patching.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is a schematic diagram of an operating environment for a method of chip software patching;
FIG. 2 is a schematic logical structure diagram of a method for patching chip software according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for patching chip software according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating interrupt processing of a method for patching chip software according to an embodiment of the present disclosure;
FIG. 5 is a schematic application diagram of a method for patching chip software according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an apparatus for patching chip software according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.
With reference to fig. 1, the operating environment of the method for patching chip software includes: and patching an object function on the ARM architecture, wherein the object function is an NVM bottom layer function. When the command of calling the target function is executed in the main program, interruption is generated, and the main program does not execute the original target function any more but jumps to the patch function. And transferring parameters to the patch function and executing, exiting interruption after executing the patch function, returning to the main program, and executing subsequent codes in the main program.
Referring to fig. 2, a logic structure of a method for patching chip software according to an embodiment of the present disclosure includes:
on the ARM architecture, patch an object function, wherein the object function is an NVM bottom-layer function, and the NVM bottom-layer function has no patch interface.
The main function of the chip firstly sets read protection for the address of the target function to be patched, and when the command of calling the target function is executed, the system automatically triggers the storage protection mechanism of the chip to generate MPU interruption.
After the MPU interruption of the chip occurs, the return address of the original target function and the parameter needing to be transmitted are pushed into the stack, and the stack jumps to an interruption processing program.
The interrupt processing program of the chip acquires the return address and the parameters of the original target function from the stack, and calls the patch function of the chip and transmits the parameters.
After the patch function of the chip is executed, the interrupt processing program of the chip returns to the subsequent code of the main program according to the return address of the original target function.
Based on the logic structure of the method for patching chip software shown in fig. 2 and shown in fig. 3, an embodiment of the present disclosure provides a flowchart of the method for patching chip software, including:
s01, the main program of the chip sets the address of the original target function to be patched as the read protection address.
And S02, generating MPU interrupt when the main program of the chip accesses the read protection address.
S03, the MPU interrupt of the chip jumps to the interrupt processing program.
S04, the interrupt handler of the chip executes the patch function.
S05, the patch function of the chip executes the back exit interrupt handler.
The method comprises the steps that the target function address is set as read protection in the initial stage of a main program of a chip, when the main program or a subprogram executes the target function, a storage protection mechanism of the chip is automatically triggered to generate MPU interruption, and a patch function is executed in an interruption processing program, so that execution of the patch function is realized. The method for calling the patch function is simple and easy to realize.
Optionally, the original objective function of step S01 has no patch interface.
Thus, the MPU mechanism can still trigger MPU interruption through the CPU accessing the read protection address under the condition that the target function has no patch interface, and has no limitation that the SVC needs to reserve the patch interface, so the MPU mechanism has more universality.
Alternatively, step S01 sets the read protection address as follows: the address of the original objective function to be patched is set to an MPU unreadable by the CPU in the program initialization stage.
In this way, the MPU interrupt may be triggered in any execution step of the main program or the sub program.
Alternatively, step S02 generates the memory protection unit MPU interrupt as follows: when the program is executed to the MPU which is unreadable by the CPU, the CPU read operation triggers the memory protection mechanism, generating an MPU interrupt.
Thus, MPU interrupts can be triggered by the existing CPU read operation mechanism without adding any other interrupt function.
Alternatively, when the MPU interrupt is generated in step S02, the return address of the original target function and the parameters to be passed by the patch function are pushed onto the stack.
Optionally, the interrupt handler of step S04 executes a patch function, including: obtaining a return address of an original target function when the interruption is generated from a stack; acquiring parameters required to be transferred by the patch function from a stack; calling a patch function and transferring the parameters; and after the patch function calling is finished, skipping to the return address of the original target function.
Therefore, the return address of the original target function is obtained from the stack, whether the currently executed patch function is the patch function to be executed by the original target function or not can be verified, and the safety of calling the patch function is guaranteed.
Optionally, after the patch function is executed to exit the interrupt handler in step S05, the method further includes: the subsequent code of the main program continues to be executed.
In this way, the calling process of the patch function can be completed.
As shown in fig. 4, an interrupt processing method of a method for patching chip software according to an embodiment of the present disclosure includes:
s11, the interrupt program of the chip acquires the return address of the original target function when the interrupt is generated from the stack.
And S12, the interrupt program of the chip acquires the parameters required to be transferred by the patch function from the stack.
S13, the interrupt program of the chip calls the patch function and passes the parameters.
And S14, jumping to the return address of the original target function after the patch function calling is finished.
The return address of the original target function is obtained from the stack, and whether the currently executed patch function is the patch function to be executed by the original target function or not can be verified, so that the safety of calling the patch function is ensured.
Referring to fig. 5, an application of the method for patching chip software according to the embodiment of the present disclosure includes:
and S21, setting read protection for the address of the original target function by the chip main program.
S22, calling the original target function by the main program of the chip, generating MPU interruption, and jumping to the interruption processing function.
S23, when the main program of the chip generates MPU interrupt, the return address and parameters are pushed into the stack.
S24, the interrupt handling function of the chip pops the return address from the stack.
And S25, calling a patch function after the interrupt processing function of the chip judges that the address is the pop address in the stack.
S26, patch function execution of the chip, and back-out interrupt processing function execution.
S27, the main program of the chip executes the code of the return address of the original target function.
Therefore, when the main program executes the original target function, the storage protection mechanism of the chip is automatically triggered to generate MPU interrupt, the interrupt processing program obtains the address returning to the main program from the stack and calls the patch function, so that the main program returns after the patch function is executed, and the main program continues to execute subsequent codes.
As shown in fig. 6, an apparatus for patching chip software according to an embodiment of the present disclosure includes a processor (processor) 100 and a memory (memory) 101. Optionally, the apparatus may also include a Communication Interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via a bus 103. The communication interface 102 may be used for information transfer. The processor 100 may call logic instructions in the memory 101 to perform the chip software patching method of the above embodiments.
In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a storage medium readable by a mobile phone when the logic instructions are sold or used as independent products.
The memory 101 is used as a storage medium for storing software programs, mobile phone executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing, i.e. implements the method for chip software patching in the above embodiments, by running program instructions/modules stored in the memory 101.
The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.
The embodiment of the disclosure provides a terminal device, which comprises the chip software patching device.
The disclosed embodiments provide a storage medium storing computer-executable instructions configured to perform the above-described chip software patching method.
The storage medium may be a transitory readable storage medium or a non-transitory readable storage medium.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the mobile phone software product is stored in a storage medium and includes one or more instructions to enable a mobile phone device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of both software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and handset program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and cell phone instructions.
Claims (10)
1. A method for patching chip software, comprising:
setting the address of an original target function to be patched as a read protection address based on an ARM architecture of a reduced instruction set machine, and generating MPU interruption when a main program accesses the read protection address;
the MPU interrupts and jumps to an interrupt processing program;
the interrupt handler executes a patch function;
the patch function executes back out of the interrupt handler.
2. The method of claim 1, wherein the original objective function has no patch interface.
3. The method of claim 1, wherein the read protection address is set as follows:
the address of the original objective function to be patched is set to an MPU unreadable by the CPU in the program initialization stage.
4. The method of claim 1, wherein the memory protection unit MPU interrupt is generated as follows:
when the program is executed to the MPU which is unreadable by the CPU, the CPU read operation triggers the memory protection mechanism, generating an MPU interrupt.
5. The method of claim 4, wherein the return address of the original target function and the parameters to be passed by the patch function are pushed onto the stack when the MPU interrupt is generated.
6. The method of claim 1, wherein the interrupt handler executes a patch function, comprising:
obtaining a return address of an original target function when the interruption is generated from a stack;
acquiring parameters required to be transferred by the patch function from a stack;
calling a patch function and transferring the parameters;
and after the patch function calling is finished, skipping to the return address of the original target function.
7. The method of any of claims 1 to 6, wherein after the patch function executes back out of an interrupt handler, further comprising: the subsequent code of the main program continues to be executed.
8. An apparatus for chip software patching comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the method for chip software patching according to any one of claims 1 to 7 when the program instructions are executed.
9. A terminal device comprising means for chip software patching according to claim 8.
10. A storage medium storing program instructions which, when executed, perform a method of chip software patching according to any one of claims 1 to 7.
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| KR20100127492A (en) * | 2009-05-26 | 2010-12-06 | 주식회사 옵토멕 | Non-volitile read-writable recording medium where a program executing a method for correcting control program is recorded |
| CN111143821A (en) * | 2019-12-20 | 2020-05-12 | 上海爱信诺航芯电子科技有限公司 | Processor and SBoot processing method of native MPU thereof |
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Application publication date: 20220329 |