CN115344434A - Patching method and device, electronic equipment and storage medium - Google Patents
Patching method and device, electronic equipment and storage medium Download PDFInfo
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- CN115344434A CN115344434A CN202211279827.1A CN202211279827A CN115344434A CN 115344434 A CN115344434 A CN 115344434A CN 202211279827 A CN202211279827 A CN 202211279827A CN 115344434 A CN115344434 A CN 115344434A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1458—Management of the backup or restore process
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F8/658—Incremental updates; Differential updates
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Abstract
The application relates to the technical field of patches and discloses a method for patching, which comprises the following steps: acquiring a patch address of an installed patch of a security chip; comparing the patch address with a preset first address and a preset second address respectively, and determining a backup patch according to a comparison result; the first address and the second address are both memory addresses within the secure chip for storing the patch. Thus, two addresses for storing patches are set in the security chip, and backup patches are determined in advance. When a new patch is printed on the security chip, the security chip can be recovered by using the backup patch even if the patch printing fails or the patch writing fails. Therefore, the security chip can be recovered under the condition of failure patching. The application also discloses a patching device, electronic equipment and a storage medium.
Description
Technical Field
The present application relates to the field of patch technologies, and for example, to a method and an apparatus for patching, an electronic device, and a storage medium.
Background
Currently, there is a technical need for patching, whether for a system or a chip. In the patching process, there may be a situation of patching failure, for example: chinese patent document No. CN102156651A discloses: because the client cannot meet the requirements of the patch installation conditions due to some technical reasons, the patch cannot be installed.
However, in case of failure of patching, the original function may not be used normally. For example: chinese patent document CN101931944A discloses: because the online upgraded version is the running version in the mobile phone, the original data can be deleted when new data is written in the flash memory, which causes some functions to be abnormal because the original data is inconsistent with the updated data.
Various problems still occur after the safety chip leaves the factory, and at the moment, the safety chip needs to be patched so that the safety chip can be normally and safely used. In the related art, when a security chip is patched, an installed patch in the security chip is erased, and then a new patch is directly downloaded to the security chip, so as to directly patch the security chip. However, in the process of patching the security chip, a situation of failure in patching may occur, so that the original functions of the security chip cannot be used normally.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a patching method and device, electronic equipment and a storage medium, so that a security chip can be recovered under the condition of failure in patching.
In some embodiments, the method for patching includes: acquiring a patch address of an installed patch of a security chip; respectively comparing the patch address with a preset first address and a preset second address, and determining a backup patch according to a comparison result; the first address and the second address are both storage addresses within the security chip for storing patches.
In some embodiments, the means for patching comprises: an obtaining module configured to obtain a patch address of an installed patch of a security chip; the comparison module is configured to compare the patch address with a preset first address and a preset second address respectively, and determine a backup patch according to a comparison result; the first address and the second address are both storage addresses within the security chip for storing patches.
In some embodiments, the electronic device comprises a processor and a memory storing program instructions, the processor being configured to, when executing the program instructions, perform the method for patching described above.
In some embodiments, the storage medium stores program instructions that, when executed, perform the above-described method for patching.
The method and the device for patching, the electronic equipment and the storage medium provided by the embodiment of the disclosure can realize the following technical effects: by obtaining the patch address of the installed patch of the security chip. And comparing the patch address with a preset first address and a preset second address respectively, and determining a backup patch according to a comparison result. The first address and the second address are both memory addresses within the secure chip for storing the patch. Thus, two addresses for storing patches are set in the security chip, and backup patches are determined in advance. When a new patch is applied to the security chip, even if the patch application fails or the patch writing fails, the security chip can be recovered by using the backup patch. Therefore, the safety chip can be recovered conveniently under the condition of failure in patching.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated in the accompanying drawings, which correspond to the accompanying drawings and not in a limiting sense, in which elements having the same reference numeral designations represent like elements, and in which:
fig. 1 is a schematic diagram of a first method for patching provided by an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a second method for patching provided by embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a third method for patching provided by embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a fourth method for patching provided by the embodiments of the present disclosure;
FIG. 5 is a schematic diagram of an apparatus for patching provided by an embodiment of the disclosure;
fig. 6 is a schematic diagram of an electronic device provided by an embodiment of the disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and claims of the embodiments of the disclosure and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged as appropriate for the embodiments of the disclosure described herein. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.
The security chip provided by the embodiment of the disclosure is provided with two patch areas with the same size. The patch area is a storage area in the security chip for storing the patch. The first address is the address of one of the patch areas and the second address is the address of the other patch area. The size is the same, i.e. the storage capacity is the same. Therefore, when the security chip is upgraded, one patch area can be selected as a backup area of the installed patch, and the other patch area can be used as an upgrading area of the patch to be installed. In the process of patching the security chip, even if patching failure or patch writing failure occurs, the security chip can be recovered by using the backup patch. Therefore, the security chip can be recovered under the condition of failure patching.
In some embodiments, the patch area is for storing patch data, the patch data including: a patch code corresponding to the patch, a 2-byte patch version number, and a 4-byte CRC (Cyclic Redundancy Check) Check value.
With reference to fig. 1, an embodiment of the present disclosure provides a method for patching, including:
step S101, the electronic equipment acquires a patch address of an installed patch of the security chip.
Step S102, the electronic equipment respectively compares the patch address with a preset first address and a preset second address, and determines a backup patch according to the comparison result; the first address and the second address are both memory addresses within the secure chip for storing the patch.
By adopting the method for patching provided by the embodiment of the disclosure, the patch address of the installed patch of the security chip is obtained. And comparing the patch address with a preset first address and a preset second address respectively, and determining a backup patch according to a comparison result. The first address and the second address are both memory addresses within the secure chip for storing the patch. Thus, two addresses for storing patches are set in the security chip, and backup patches are predetermined. When a new patch is applied to the security chip, even if the patch application fails or the patch writing fails, the security chip can be recovered by using the backup patch. Therefore, the security chip can be recovered under the condition of failure patching.
In some embodiments, the stored patch is used as the installed patch after the patch operation is performed on the security chip by using the stored patch. The patch address of the installed patch is the address to be installed of the stored patch. And storing the patch address of the installed patch in a preset address of the security chip. Obtaining a patch address of an installed patch of the security chip, that is, obtaining a patch address of the installed patch at a preset address of the security chip.
Optionally, determining the backup patch according to the comparison result includes: under the condition that the patch address is the same as the first address, determining the patch stored in the first address as a backup patch; in the case where the patch address is the same as the second address, the patch stored at the second address is determined as a backup patch. The first address and the second address are different storage addresses of the security chip. In this way, by comparing the patch address with the first address and the second address, it is possible to determine at which memory address the installed patch that is being executed by the security chip is stored, and determine the installed patch that is being executed and stored in the memory address as the backup patch. So that the function of the security chip can be restored by using the backup patch under the condition of failure in patching or failure in writing the patch.
Optionally, determining a backup patch according to the comparison result, further comprising: under the condition that the patch address, the first address and the second address are different, obtaining an installed patch; the installed patch is stored to the first address or the second address and the installed patch is determined to be a backup patch. Therefore, under the condition that the patch address, the first address and the second address are different, the patch needs to be stored in the patch area first, so that a backup patch can be determined during subsequent patching.
Optionally, after determining the backup patch according to the comparison result, the method further includes: obtaining a patch to be installed; and determining the storage address where the backup patch is not stored as the address to be installed, and storing the patch to be installed to the address to be installed. Therefore, the installed patch used by the security chip can be reserved when the patch to be installed is stored in the storage address where the backup patch is not stored, and the security chip can be recovered by using the backup patch even if the patching fails or the patch writing fails when a new patch is patched for the security chip.
Further, determining a storage address where the backup patch is not stored as an address to be installed includes: and determining the second address as the address to be installed under the condition that the storage address corresponding to the backup patch is the first address. And determining the first address as the address to be installed under the condition that the storage address corresponding to the backup patch is the second address.
With reference to fig. 2, a second method for patching is provided in an embodiment of the present disclosure, which includes:
in step S201, the electronic device obtains a patch address of an installed patch of the security chip.
Step S202, the electronic equipment compares the patch address with a preset first address and a preset second address respectively, and determines a backup patch according to the comparison result; the first address and the second address are both memory addresses within the secure chip for storing the patch.
In step S203, the electronic device obtains a patch to be installed.
Step S204, the electronic device determines the storage address where the backup patch is not stored as the address to be installed, and stores the patch to be installed to the address to be installed.
By adopting the method for patching provided by the embodiment of the disclosure, the patch address of the installed patch of the security chip is obtained. And comparing the patch address with a preset first address and a preset second address respectively, and determining a backup patch according to a comparison result. And obtaining a patch to be installed. And determining the storage address where the backup patch is not stored as the address to be installed, and storing the patch to be installed to the address to be installed. Thus, two addresses for storing patches are set in the security chip, and the backup patches are predetermined. And then storing the patch to be installed to the address to be installed, wherein the backup patch cannot be covered by the patch to be installed. When a new patch is printed on the security chip, the security chip can be recovered by using the backup patch even if the patch printing fails or the patch writing fails. Therefore, the safety chip can be recovered conveniently under the condition of failure in patching.
Further, before storing the patch to be installed to the address to be installed, the method further includes: and erasing the patch data stored in the address to be installed. Wherein the patch data includes: the corresponding patch code of the patch, the version number of the patch of 2 bytes and the CRC check value of 4 bytes. In this way, the secure chip may perform a plurality of patching operations, so that the first address and the second address both store patches. And the patch data stored in the address to be installed is erased, so that a new patch can be conveniently downloaded to the address to be installed, and the new patch and the old patch can not conflict.
Further, storing the patch to be installed to the address to be installed includes: calculating a first CRC (cyclic redundancy check) value of a patch to be installed; and comparing the first CRC value with a preset verification value, and storing the patch to be installed to the address to be installed under the condition that the first CRC value is consistent with the preset verification value. In this way, cyclic redundancy checks can be used to detect or check for errors that may occur after data transmission or storage. Whether errors occur in the data transmission process can be detected by comparing the first CRC check value with a preset verification value, and therefore the correctness of the patch to be installed is guaranteed.
Optionally, after storing the patch to be installed to the address to be installed, the method further includes: verifying whether the stored patch is complete; the stored patch is a to-be-installed patch stored in the to-be-installed address; and under the condition that the stored patch is complete, performing patching operation on the security chip by using the stored patch. Therefore, the safe chip is patched by using the stored patch under the condition that the stored patch is complete, so that the safe chip can smoothly complete patching operation.
With reference to fig. 3, a third method for patching is provided in an embodiment of the present disclosure, including:
in step S301, the electronic device obtains a patch address of an installed patch of the security chip.
Step S302, the electronic device compares the patch address with a preset first address and a preset second address, and determines a backup patch according to the comparison result.
Step S303, the electronic device obtains a patch to be installed.
Step S304, the electronic device determines the storage address where the backup patch is not stored as the address to be installed, and stores the patch to be installed to the address to be installed.
Step S305, the electronic equipment verifies whether the stored patch is complete; the stored patch is a to-be-installed patch stored in the to-be-installed address.
Step S306, when the stored patch is complete, the electronic device performs a patching operation on the security chip by using the stored patch.
By adopting the method for patching provided by the embodiment of the disclosure, the patch address of the installed patch of the security chip is obtained. And acquiring the patch address of the installed patch of the security chip. The electronic device obtains a patch to be installed. And determining the storage address where the backup patch is not stored as the address to be installed, and storing the patch to be installed to the address to be installed. Verifying whether the stored patch is complete; the stored patch is a to-be-installed patch stored in the to-be-installed address. And under the condition that the stored patch is complete, performing patching operation on the security chip by using the stored patch. Thus, two addresses for storing the patch are set in the security chip, and the backup patch is determined in advance. And storing the patch to be installed to the address to be installed. When a new patch is printed on the security chip, the security chip can be recovered by using the backup patch even if the patch printing fails or the patch writing fails. Therefore, the safety chip can be recovered conveniently under the condition of failure in patching. Meanwhile, under the condition that the stored patch is complete, the stored patch is utilized to patch the security chip, so that the security chip can smoothly complete the patching operation.
Further, verifying whether the stored patch is complete includes: acquiring a patch version number of a stored patch; comparing the patch version number with a preset expected version number to obtain a first comparison result; calculating a second CRC value of the stored patch, and comparing the second CRC value with a preset verification value to obtain a second comparison result; and determining whether the stored patch is complete according to the first comparison result and the second comparison result. In this way, comparing the patch version number with a preset expected version number can determine whether the stored patch is the patch version that the user wishes to download. Meanwhile, the second CRC value is compared with a preset verification value, and whether the stored patch has a problem in the storage process can be determined. Whether the stored patch is complete or not is determined through the two comparison results, and the patching operation of the security chip can be completed smoothly.
In some embodiments, in response to a user's version number input instruction, a desired version number is input into the secure chip. The desired version number is obtained from the secure chip.
Further, determining whether the stored patch is complete according to the first comparison result and the second comparison result includes: determining that the stored patch is complete under the condition that the first comparison result is that the patch version number is consistent with a preset expected version number and the second comparison result is that the second CRC check value is consistent with a preset verification value; otherwise, the stored patch is determined to be incomplete.
With reference to fig. 4, a fourth method for patching is provided in an embodiment of the present disclosure, where the method includes:
in step S401, the electronic device obtains a patch address of an installed patch of the security chip, and then performs step S402.
Step S402, the electronic equipment determines whether the patch address is consistent with a preset first address, and if the patch address is consistent with the preset first address, the step S403 is executed; in the case where the patch address does not coincide with the preset first address, step S404 is performed.
In step S403, the electronic device determines the patch stored at the first address as a backup patch, and then performs step S406.
Step S404, the electronic device determines whether the patch address is consistent with a preset second address, and executes step S405 if the patch address is consistent with the preset second address; in the case where the patch address does not coincide with the preset second address, step S414 is performed.
In step S405, the electronic apparatus determines the patch stored at the second address as a backup patch, and then performs step S406.
Step S406, the electronic equipment acquires a patch to be installed; calculating a first CRC value of a patch to be installed; then, step S407 is executed.
Step S407, the electronic device determines whether the first CRC check value is consistent with a preset verification value; executing step S408 if the first CRC check value is consistent with the preset verification value; in the case where the first CRC check value does not coincide with the preset verification value, step S415 is performed.
Step S408, the electronic equipment stores the patch to be installed to the address to be installed; then, step S409 is performed.
Step S409, the electronic equipment acquires a patch version number of the stored patch; the stored patch is a to-be-installed patch stored in the to-be-installed address; then, step S410 is performed.
Step S410, the electronic equipment determines whether the patch version number is consistent with a preset expected version number; executing step S411 if the patch version number is consistent with the preset expected version number; in case the patch version number does not correspond to the preset desired version number, step S415 is performed.
Step S411, the electronic device calculates a second CRC check value of the stored patch; then, step S412 is performed.
Step S412, the electronic device determines whether the second CRC check value is consistent with a preset verification value; in case the second CRC check value is identical to the preset verification value, performing step S413; in the case where the second CRC check value does not coincide with the preset verification value, step S415 is performed.
In step S413, the electronic device performs a patching operation on the security chip by using the stored patch.
In step S414, the electronic device obtains the installed patch and stores the installed patch to the first address or the second address.
In step S415, the flow ends.
By adopting the method for patching provided by the embodiment of the disclosure, the backup patch is determined, and the patch to be installed is stored in the address to be installed. And verifying the patch to be installed, and performing patching operation on the security chip by using the patch to be installed under the condition of successful verification. Thus, two addresses for storing patches are set in the security chip, and backup patches are determined in advance. When a new patch is applied to the security chip, even if the patch application fails or the patch writing fails, the security chip can be recovered by using the backup patch. Therefore, the safety chip can be recovered conveniently under the condition of failure in patching.
Optionally, after the patch operation is performed on the security chip by using the stored patch, the method further includes: and determining whether the function of the security chip is normal according to a preset judgment flow, and performing patching operation on the security chip by using the backup patch under the condition that the function of the security chip is abnormal.
Optionally, after the patch operation is performed on the security chip by using the stored patch, the method further includes: and updating the patch address of the installed patch of the security chip.
Optionally, updating the patch address of the installed patch of the security chip includes: and determining whether the function of the security chip is normal according to a preset judgment flow, and updating the patch address of the installed patch of the security chip under the condition that the function of the security chip is normal.
In some embodiments, updating the patch address of the installed patch of the secure chip includes: and acquiring the storage address of the stored patch, and replacing the patch address of the installed patch with the storage address.
In some embodiments, the patch address of the installed patch is not stored at the preset address of the secure chip, i.e. the patch is first patched for the secure chip. And storing the patch to be installed acquired by the electronic equipment to the first address or the second address, and performing patching operation on the security chip by using the stored patch.
In some embodiments, updating the upgraded function B is referred to as B'. Patch A includes B'. After the secure chip finishes patching A, when the secure chip runs to the function B, the secure chip directly points to B ' in the patch A and executes B ', so that the function B is replaced by the B '.
In some embodiments, since there is only one patch package in use in the security chip, there may be one or more updated and upgraded functions in one patch package, so as to patch a plurality of places in the security chip that need to be patched.
As shown in fig. 5, an apparatus for patching according to an embodiment of the present disclosure includes an obtaining module 501 and a comparing module 502. An obtaining module 501 configured to obtain a patch address of an installed patch of a secure chip. A comparing module 502 configured to compare the patch address with a preset first address and a preset second address, respectively, and determine a backup patch according to the comparison result. The first address and the second address are both memory addresses within the secure chip for storing the patch.
By adopting the device for patching provided by the embodiment of the disclosure, the patch address of the installed patch of the security chip is obtained through the obtaining module. The comparison module compares the patch address with a preset first address and a preset second address respectively, and determines a backup patch according to a comparison result. Thus, two addresses for storing patches are set in the security chip, and backup patches are predetermined. When a new patch is applied to the security chip, even if the patch application fails or the patch writing fails, the security chip can be recovered by using the backup patch. Therefore, the safety chip can be recovered conveniently under the condition of failure in patching.
As shown in fig. 6, an embodiment of the present disclosure provides an electronic device including a processor (processor) 600 and a memory (memory) 601. Optionally, the apparatus may also include a Communication Interface 602 and a bus 603. The processor 600, the communication interface 602, and the memory 601 may communicate with each other via a bus 603. The communication interface 602 may be used for information transfer. The processor 600 may call logic instructions in the memory 601 to perform the method for patching of the above-described embodiments.
Optionally, the electronic device is a computer or a server.
By adopting the electronic equipment provided by the embodiment of the disclosure, the patch address of the installed patch of the security chip is obtained. And comparing the patch address with a preset first address and a preset second address respectively, and determining a backup patch according to a comparison result. The first address and the second address are both memory addresses within the secure chip for storing the patch. Thus, two addresses for storing patches are set in the security chip, and backup patches are predetermined. When a new patch is applied to the security chip, even if the patch application fails or the patch writing fails, the security chip can be recovered by using the backup patch. Therefore, the security chip can be recovered under the condition of failure patching.
In addition, the logic instructions in the memory 601 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.
The memory 601 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 600 executes functional applications and data processing, i.e. implements the method for patching in the above embodiments, by executing program instructions/modules stored in the memory 601.
The memory 601 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 601 may include a high speed random access memory, and may also include a non-volatile memory.
Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for patching.
Embodiments of the present disclosure provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the above-described method for patching.
The computer-readable storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.
The above description and the drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one of 8230," does not exclude the presence of additional like elements in a process, method or device comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosure, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be only one type of logical functional division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A method for patching, comprising:
acquiring a patch address of an installed patch of a security chip;
respectively comparing the patch address with a preset first address and a preset second address, and determining a backup patch according to a comparison result; the first address and the second address are both storage addresses within the security chip for storing patches.
2. The method of claim 1, wherein determining a backup patch based on the comparison comprises:
under the condition that the patch address is the same as the first address, determining a patch stored at the first address as a backup patch;
and determining the patch stored at the second address as a backup patch under the condition that the patch address is the same as the second address.
3. The method of any one of claims 1 or 2, wherein determining the backup patch based on the comparison further comprises:
obtaining a patch to be installed;
and determining the storage address where the backup patch is not stored as the address to be installed, and storing the patch to be installed to the address to be installed.
4. The method of claim 3, wherein storing the patch to be installed to the address to be installed comprises:
calculating a first CRC value of the patch to be installed;
and comparing the first CRC check value with a preset verification value, and storing the patch to be installed to the address to be installed under the condition that the first CRC check value is consistent with the preset verification value.
5. The method of claim 3, wherein after storing the patch to be installed to the address to be installed, further comprising:
verifying whether the stored patch is complete; the stored patch is a to-be-installed patch stored in the to-be-installed address;
and under the condition that the stored patch is complete, utilizing the stored patch to carry out patching operation on the security chip.
6. The method of claim 5, wherein verifying whether the stored patch is complete comprises:
acquiring a patch version number of the stored patch;
comparing the patch version number with a preset expected version number to obtain a first comparison result;
calculating a second CRC (cyclic redundancy check) value of the stored patch, and comparing the second CRC value with a preset verification value to obtain a second comparison result;
and determining whether the stored patch is complete according to the first comparison result and the second comparison result.
7. The method of claim 5, wherein after the patching operation of the security chip by using the stored patch, further comprising:
and updating the patch address of the installed patch of the security chip.
8. An apparatus for patching, comprising:
an obtaining module configured to obtain a patch address of an installed patch of a security chip;
the comparison module is configured to compare the patch address with a preset first address and a preset second address respectively, and determine a backup patch according to a comparison result; the first address and the second address are both storage addresses within the secure chip for storing patches.
9. An electronic device comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the method for patching according to any one of claims 1 to 7 when the program instructions are executed.
10. A storage medium storing program instructions which, when executed, perform a method for patching according to any of claims 1 to 7.
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