CN114252775A

CN114252775A - Current detection chip, battery and electronic equipment

Info

Publication number: CN114252775A
Application number: CN202110213271.5A
Authority: CN
Inventors: 唐晓
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2020-09-23
Filing date: 2020-09-23
Publication date: 2022-03-29
Anticipated expiration: 2040-09-23
Also published as: CN111929594A; CN111929594B; CN114252775B

Abstract

The embodiment of the application provides current detection chip, battery and electronic equipment, and the current detection chip is used for the battery to carry out current detection at the charge-discharge in-process, and the current detection chip includes: a current compensation circuit for generating a first compensation current that varies with a variation in a power supply voltage from the battery; the comparison circuit comprises a first input end and a second input end; the selection circuit is used for receiving the first compensation current and selecting the first compensation current to be input to a first input end of the comparison circuit or a second input end of the comparison circuit; the comparison circuit is used for outputting an indication signal according to a comparison result of the current of the second input end of the current of the first input end of the comparison circuit, and the indication signal is used for indicating whether the charging and discharging process of the battery is over-current or not. The application provides a current detection chip, a battery and electronic equipment for improving the current detection accuracy of the battery in the charging and discharging process.

Description

Current detection chip, battery and electronic equipment

Technical Field

The application relates to the technical field of quick charging, in particular to a current detection chip, a battery and electronic equipment.

Background

With the advent of the intelligent era, the continuous promotion of software and hardware greatly increases the power consumption of electronic equipment such as mobile phones, and therefore, the fast-charging technology comes along with the coming of the intelligent era. In the battery quick-charging technology, the voltage of the battery is changed rapidly, so that the on-resistance of a transistor in a battery protection circuit is changed, the current detection of the battery in the charging and discharging process is caused, and the use of a user is influenced.

Disclosure of Invention

The application provides a current detection chip, a battery and electronic equipment for improving the current detection accuracy of the battery in the charging and discharging process.

In a first aspect, an embodiment of the present application provides a current detection chip, configured to perform current detection during charging and discharging of a battery, including:

a current compensation circuit for generating a first compensation current that varies linearly with a variation in a power supply voltage from the battery;

the comparison circuit comprises a first input end and a second input end;

the selection circuit is used for receiving the first compensation current and selecting the first compensation current to be input to the first input end of the comparison circuit or the second input end of the comparison circuit;

the comparison circuit is used for comparing the current of the first input end of the comparison circuit with the current of the second input end of the comparison circuit and outputting an indication signal according to the comparison result, wherein the indication signal is used for indicating whether the charging and discharging process of the battery is over-current or not.

In a second aspect, an embodiment of the present application provides a battery, including an electric core and a current detection chip, where the current detection chip is electrically connected to the electric core, and the current detection chip is used for current detection in a charging and discharging process of the electric core.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the battery.

By designing the current detection chip, the selection circuit receives the first compensation current and selects the first compensation current to be input to the first input end of the comparison circuit or the second input end of the comparison circuit, so that only one current compensation circuit is needed to generate the first compensation current, and the selection circuit selectively inputs the first compensation current to the first input end of the comparison circuit or the second input end of the comparison circuit, and the problem that the current detection of the second input end is inaccurate due to the change of the on-resistance of the MOS transistor in the charging and discharging loop is solved under the condition of less current compensation circuits.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic view of an application scenario of an electronic device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a battery provided in an embodiment of the present application;

fig. 3 is a schematic circuit structure diagram of a battery protection board according to an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of current detection in a first discharge mode according to an embodiment of the present disclosure;

FIG. 5 is a circuit diagram illustrating current detection in a discharge mode according to the prior art;

fig. 6 is a schematic circuit diagram of current detection in a charging mode according to an embodiment of the present disclosure;

fig. 7 is a circuit block diagram of a first current compensation circuit provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of a first current compensation circuit according to an embodiment of the present disclosure;

FIG. 9 is a circuit diagram illustrating current detection in a first discharge mode according to an embodiment of the present disclosure;

fig. 10 is a circuit block diagram of a second current compensation circuit provided in an embodiment of the present application;

fig. 11 is a schematic partial structure diagram of a second current compensation circuit according to an embodiment of the present disclosure;

fig. 12 is a schematic partial structure diagram of a third current compensation circuit provided in the embodiment of the present application;

fig. 13 is a schematic structural diagram of a fourth current compensation circuit provided in the embodiment of the present application;

fig. 14 is a schematic partial structure diagram of a fifth current compensation circuit according to an embodiment of the present application;

fig. 15 is a circuit block diagram of a second current compensation circuit provided in an embodiment of the present application;

fig. 16 is a schematic partial structure diagram of a sixth current compensation circuit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The embodiments recited in the present application can be combined with each other as appropriate without departing from the scope of the invention.

With the development of science and technology, the functions of electronic devices (such as smart phones, wearable devices, tablet computers and other electronic devices) become more and more powerful, and users can work and entertain through the electronic devices, so that the electronic devices become an indispensable part of people's daily life. However, the endurance of the electronic device is limited, requiring the user to continuously charge the electronic device. In order to ensure that a user can normally use the electronic device, fast charging is a mainstream scheme of charging.

The currently common quick charging technology can be mainly divided into two categories: a low-voltage large-current quick charging technology and a high-voltage small-current quick charging technology. No matter the low-voltage large-current quick charging or the high-voltage small-current quick charging, when the battery is input into the charging circuit of the electronic device, the battery is converted into a larger charging current (the charging current cannot exceed the maximum safe charging current carried by the battery or the safe charging current which does not damage the service life of the battery), and at this time, how to ensure the charging safety of the quick charging is important when the large-current charging is carried out on the battery.

Referring to fig. 1, fig. 1 is an application scenario applicable to the embodiment of the present application. In the scenario shown in fig. 1, an electronic device 100, a charging cord 200, and a charger 300 are included. The electronic device 100 includes, but is not limited to, a mobile phone, a notebook computer, a palm top computer, a rechargeable headset, a rechargeable sound box, a rechargeable wearable device, a robot, a rechargeable home appliance, a rechargeable vehicle, a rechargeable transportation vehicle, and other rechargeable electronic products. The charger 300 is electrically connected to the electronic device 100 through the charging wire 200. The electronic device 100 includes at least a battery 10, a connection interface 20, a charge management chip 30, a load 40, and the like. The connection interface 20 is electrically connected to the charge management chip 30. The battery 10 is electrically connected to the charge management chip 30 and the load 40, respectively. The battery 10 includes a battery protection plate 101 and a battery core 102. The load 40 may be a power consuming device in the electronic device 100, for example, the load 40 may be a microphone, a camera, a display screen, a motor, and other various power consuming devices. The charge management chip 30 is a chip that manages charging of the battery 10. During charging, the current flow direction is as follows: charger 300 → charging wire 200 → connection interface 20 → charging management chip 30 → battery protection board 101 → battery core 102. During discharge, the current flow direction is as follows: cell 102 → battery protection plate 101 → load 40.

In the process of charging and discharging the battery 10, particularly in the field of quick charge technology, current detection of the battery 10 is an important issue. The current detection chip is generally designed to detect the current during the charge and discharge of the battery 10. The battery 10 includes, but is not limited to, a lithium ion battery, a lithium metal battery, and the like.

Referring to fig. 2, the current detecting chip 1 may be disposed on the battery protection plate 101 of the battery 10, may be disposed in the electronic device 100 and located outside the battery 10 (e.g., on a main board of the electronic device 100), and may be disposed in the charger 300. In the embodiment of the present application, the current detection chip 1 is provided on the battery protection plate 101 as an example. The current detection chip 1 is used for monitoring current information of the battery 10, and when the current reaches a protection threshold value, corresponding charge and discharge transistors are turned off, so that the purpose of protecting the battery 10 is achieved.

In the related art, under different power supply voltages, a charge-discharge MOS (Metal-Oxide-Semiconductor) transistor changes with the power supply voltage, which causes an inaccurate current value detected by the battery protection board 101, and further causes an inaccurate overcurrent protection of the battery by the battery protection board 101. The power supply voltage is the voltage of the port electrically connected with the positive terminal of the battery core.

The present application provides a current detection chip that improves the accuracy of current detection during charging and discharging of a battery 10. The application scenario in the present application includes a battery cell 102, a battery protection board 101, a discharging load (not shown), or an external charging device (not shown). The battery protection plate 101 is provided with a current detection chip 1. Of course, the battery protection plate 101 is also provided with a chip for voltage detection and the like. The chips may be packaged independently into a plurality of chips, and the pins of the chips are connected to each other, or the chips may be packaged together into a whole, in other words, the current detection chip 1 described herein may be an independent chip package or a part of a chip package. For convenience of description, please refer to fig. 3, the battery protection plate 101 is further provided with a first battery terminal interface BAT +, a second battery terminal interface BAT-, a first external interface EB + and a second external interface EB-. The first battery terminal interface BAT + is electrically connected with the positive terminal of the electric core 102, the second battery terminal interface BAT-is electrically connected with the negative terminal of the electric core 102, the first external interface EB + is electrically connected with the positive terminal of the discharging load or the positive terminal of the external charging equipment, and the second external interface EB-is electrically connected with the negative terminal of the load or the negative terminal of the external charging equipment.

Referring to fig. 4, the current detecting chip 1 at least includes a comparing circuit 2, a current compensating circuit 3 and a selecting circuit 4.

Referring to fig. 4, the comparison circuit 2 includes a first input terminal 21 and a second input terminal 22. The first input terminal 21 of the comparison circuit 2 may be a positive input terminal, and the second input terminal 22 of the comparison circuit 2 may be a negative input terminal; alternatively, the first input terminal 21 of the comparison circuit 2 may be a negative input terminal, and the second input terminal 22 of the comparison circuit 2 may be a positive input terminal. In this application, the first input terminal 21 of the comparison circuit 2 can be a positive input terminal, and the second input terminal 22 of the comparison circuit 2 can be a negative input terminal.

Referring to fig. 3 and 4, in the discharging mode, the current flows through the positive terminal of the battery cell 102, the first battery terminal interface BAT +, the first external interface EB +, the positive terminal of the load, the negative terminal of the load, the second external interface EB-, the second input terminal 22 of the comparison circuit 2, the first input terminal 21 of the comparison circuit 2, the second battery terminal interface BAT-, and the negative terminal of the battery cell 102 in sequence. In the charging mode, a current flows through the positive electrode of the external charging device, the first external interface EB +, the first battery terminal interface BAT +, the positive electrode terminal of the electric core 102, the negative electrode terminal of the electric core 102, the first input terminal 21 of the comparison circuit 2, the second input terminal 22 of the comparison circuit 2, and the second battery terminal interface BAT-in sequence.

The comparison circuit 2 is a current mode comparison circuit. The comparison circuit 2 is configured to compare a current of a first input terminal 21 of the comparison circuit 2 with a current of a second input terminal 22 of the comparison circuit 2 during charging and discharging of the battery 10, and output an indication signal according to a comparison result, where the indication signal is used to indicate whether a charging and discharging process of the battery 10 is over-current.

Specifically, the comparing circuit 2 may compare the current signal received by the first input terminal 21 with the current signal received by the second input terminal 22, and output an indication signal when the value of the current signal at the first input terminal 21 is greater than the value of the current signal at the second input terminal 22. The indication signal may be high or low. When the indication signal is a high level signal, the indication signal is used for controlling the charging transistor of the charging and discharging loop of the battery 10 to be switched off and the discharging transistor to be switched on, so that the battery 10 finishes the charging mode and is converted into a dischargeable mode, and the charging overcurrent protection is carried out on the battery 10; when the indication signal is a low level signal, the indication signal is used to control the discharging transistor of the charging and discharging circuit of the battery 10 to be turned off and the charging transistor to be turned on, so that the battery 10 ends the discharging mode and is converted into the chargeable mode, thereby performing discharging overcurrent protection on the battery 10.

It is understood that both the charging loop and the discharging loop have MOS transistors. The on-resistance of the MOS transistor is related to the voltage of the driving gate. When the power supply voltage Vdd (Vdd is the voltage at the Vdd terminal in fig. 3) decreases, the driving voltage of the MOS transistor decreases, which increases the on-resistance of the MOS transistor, and when the power supply voltage Vdd increases, the voltage of the driving MOS transistor increases, which decreases the on-resistance of the MOS transistor, which may cause inaccurate current detection in the comparison circuit 2 and cause a phenomenon of false triggering of the over-current protection.

In view of the above problems, the current detection chip 1 provided by the present application includes a current compensation circuit 3 and a selection circuit 4. The current compensation circuit 3 is used for generating a first compensation current. The first compensation current linearly changes with the change of the power supply voltage Vdd so as to compensate the influence generated by the change of the on-resistance of the MOS transistor with the change of the power supply voltage Vdd.

The selection circuit 4 is configured to receive the first compensation current and select the first compensation current to be input to the first input terminal 21 of the comparison circuit 2 or the second input terminal 22 of the comparison circuit 2. Specifically, in the discharge loop, the on-resistance change of the MOS transistor causes the current detection of the first input terminal 21 of the comparison circuit 2 to be inaccurate, and the selection circuit 4 selects the first compensation current to compensate for the first input terminal 21 of the comparison circuit 2, so as to reduce the problem that the current detection of the comparison circuit 2 is inaccurate due to the on-resistance change of the MOS transistor, which causes the phenomenon of false triggering of the over-current protection. In the charging loop, the on-resistance variation of the MOS transistor causes inaccurate current detection of the second input terminal 22, and the selection circuit 4 selects the first compensation current to compensate the second input terminal 22, so as to reduce the problem that the current detection of the second input terminal 22 is inaccurate due to the on-resistance variation of the MOS transistor, which causes a phenomenon of false triggering of the over-current protection. Therefore, only one current compensation circuit 3 is needed to generate the first compensation current, and the first compensation current is selectively input to the first input end 21 of the comparison circuit 2 or the second input end 22 of the comparison circuit 2 through the selection circuit 4, so that the problem that the current detection of the second input end 22 is inaccurate due to the change of the on-resistance of the MOS transistor in the charging and discharging loop and the phenomenon of false triggering of the over-current protection is caused is solved under the condition of less current compensation circuits 3.

The application aims at the problem that the on-resistance of an MOS transistor is increased due to the fact that the power supply voltage Vdd is reduced; the power supply voltage Vdd is increased to cause the on-resistance of the MOS transistor to be reduced, so that the on-resistance of the MOS transistor is reversely changed along with the change of the power supply voltage Vdd. In other words, the dynamic variation trend of the first compensation current along with the power supply voltage Vdd is the same as or similar to the dynamic variation trend of the on-resistance of the MOS transistor along with the power supply voltage Vdd, so as to improve the compensation accuracy of the influence on the on-resistance of the MOS transistor. In the process of adjusting the magnitude of the first compensation current, the first compensation current has better linearity and can be adjusted to a current which can counteract the influence of all the on-resistance of the MOS transistor more easily.

In one possible embodiment, referring to fig. 3, the current detecting chip 1 includes a power voltage terminal VDD, a first ground terminal GND, a charge management terminal DO, a discharge management terminal CO, and a second ground terminal VM.

The battery protection board 101 is further provided with a first resistor R1, a first capacitor C1, a second resistor R2, a discharge MOS transistor Q1, a first parasitic diode D1, a charge MOS transistor Q2, and a second parasitic diode D2.

One end of the first resistor R1 is electrically connected to the positive terminal of the battery cell 102, and the other end of the first resistor R1 is electrically connected to the power supply voltage terminal VDD. The voltage of the power supply voltage terminal VDD is the power supply voltage VDD.

The first ground terminal GND is electrically connected to the negative terminal of the battery cell 102. The two ends of the first capacitor C1 are connected to the power voltage terminal VDD and the first ground terminal GND, respectively. The first resistor R1 and the first capacitor C1 perform a filtering function. The first resistor R1 also has a voltage division protection function.

The source of the discharging MOS transistor Q1 is connected to the negative terminal of the battery cell 102, and the gate of the discharging MOS transistor Q1 is a discharging protection control terminal and is connected to the discharging management terminal CO.

The drain electrode of the discharging MOS transistor Q1 is connected with the drain electrode of the charging MOS transistor Q2, the source electrode of the charging MOS transistor Q2 is connected with a second external interface EB-, and the grid electrode of the charging MOS transistor Q2 is a charging protection control end and is connected with a charging management end DO. The discharge MOS transistor Q1 can be turned on or off to turn on or off to the discharge loop according to the control of the signal at its control terminal, and therefore, the discharge MOS transistor Q1 can also be referred to as a discharge control switch; the charging MOS transistor Q2 can be turned on or off to turn on or off the charging circuit according to the control of the signal at its control terminal, and therefore, the charging MOS transistor Q2 can also be referred to as a charging control switch.

The second ground terminal VM is a ground of the discharging load or a ground of the external charging device, and is connected to the load or the ground of the external charging device by the second resistor R2.

The first input terminal 21 of the comparison circuit 2 is electrically connected to the first ground GND, the second input terminal 22 of the comparison circuit 2 is electrically connected to the second ground VM, and the output terminal of the comparison circuit 2 is electrically connected to the charging management terminal DO and the discharging management terminal CO through the logic circuit. The comparison circuit 2 outputs an indication signal by comparing the current difference between the first input terminal 21 and the second input terminal 22. For example, when the current value of the first input terminal 21 is larger than the current value of the second input terminal 22, the indication signal is at a high level. When the current value of the first input terminal 21 is less than or equal to the current value of the second input terminal 22, the indication signal is at a low level. The indication signal can control the discharging MOS transistor Q1 to be switched off and the charging MOS transistor Q2 to be switched on; or controls the discharging MOS transistor Q1 to be turned on and the charging MOS transistor Q2 to be turned off.

In the conventional art, in the discharging mode, an equivalent circuit diagram of the comparison circuit 2 is shown in fig. 5, wherein the resistor R provides the fixed offset voltage Vos of the comparator. R is a fixed resistance. When the discharge current is larger than k (VM-GND)/R, where k is a ratio coefficient of the actual current to the detection current, GND is a voltage of the first ground terminal GND, and VM is a voltage of the second ground terminal VM. The output end OUT of the comparison circuit 2 is a high level to trigger overcurrent protection; when the discharge current is smaller than k (VM-GND)/R, the output end OUT of the comparison circuit 2 is at a low level, and overcurrent protection is not triggered.

Referring to fig. 4, when the on-resistance of the discharging MOS transistor Q1 and the charging MOS transistor Q2 in the discharging loop is affected by the variable resistor R0 disposed between the first input terminal 21 of the comparison circuit 2 and the first ground terminal GND, which results in a variable gate voltage-related Δ v (vdd) between the first input terminal 21 of the comparison circuit 2 and the first ground terminal GND, when the discharging current is greater than k { VM- [ GND + Δv (vdd)) ]/R0, the output of the output terminal OUT of the comparison circuit 2 is at a high level, triggering the over-current protection, and when the discharging current is less than k { VM- [ GND + Δv + (vdd))/R0, the output of the output terminal OUT of the comparison circuit 2 is at a low level, not triggering the over-current protection. Therefore, the current threshold of the overcurrent protection is changed, so that the problem of inaccurate overcurrent protection is caused. Referring to fig. 6, in the charging mode, the effect of the on-resistances of the discharging MOS transistor Q1 and the charging MOS transistor Q2 is equivalent to disposing a variable resistor R0 between the second input terminal 22 of the comparison circuit 2 and the second ground terminal VM, which is not described herein again.

In the current detection chip 1 of the embodiment of the present application, in the discharging mode, the selection circuit 4 connects the output terminal of the current compensation circuit 3 to the first input terminal 21 of the comparison circuit 2. In the discharging process, the first compensation current generated by the current compensation circuit 3 can dynamically adjust the over-discharge current trigger threshold, so that the occurrence of false triggering of over-current protection is prevented. The lower the power supply voltage Vdd is, the larger the charging and discharging MOS transistor on-resistance is, the larger the current compensated for the variable resistor R0 is, the higher the threshold value of triggering overcurrent is, thus, the influence on the triggering threshold of discharging current caused by the increase of the charging and discharging MOS transistor on-resistance is counteracted; the higher the power supply voltage Vdd is, the smaller the on-resistance of the charge and discharge MOS transistor is, the smaller the current compensated for the variable resistor R0 is, and the lower the threshold for triggering the overcurrent is, so as to offset the influence on the trigger threshold of the discharge current due to the decrease in the on-resistance of the charge and discharge MOS transistor, so as to dynamically adjust the threshold for triggering the overcurrent protection along with the power supply voltage Vdd, and to eliminate the influence on the threshold of the overcurrent protection due to the change in the on-resistance of the charge and discharge MOS transistor as much as possible.

In other words, when the power supply voltage Vdd changes, the on-resistances of the discharging MOS transistor Q1 and the charging MOS transistor Q2 change, equivalent to the presence of a variable resistor R0 between the second ground terminal VM and the first ground terminal GND, resulting in a changed gate voltage-dependent Δ v (Vdd) between the second ground terminal VM and the first ground terminal GND. The higher the power supply voltage Vdd, the smaller the on-resistance of the charge/discharge MOS transistor, and the smaller Δ v (Vdd). The power supply voltage Vdd decreases, the on-resistance of the charge/discharge MOS transistor increases, and Δ v (Vdd) increases. When the first compensation current is added to the first input terminal 21 of the comparison circuit 2, the higher the power supply voltage Vdd is, the smaller the voltage Δ V equivalent to the compensation at the second ground terminal VM is; the lower the power supply voltage Vdd, the larger the voltage Δ V compensated at the second ground terminal VM; when the discharge current is larger than k { (VM +. DELTA.V) - [ GND +. DELTA { (VM +. DELTA.V) ]

V (Vdd) ]/R0, the output end OUT of the comparison circuit 2 is at high level, and overcurrent protection is triggered; when the discharge current is less than k { (VM +. DELTA.V) - [ GND +. DELTA.V (Vdd) ] }/R0, the output of the output terminal OUT of the comparison circuit 2 is at a low level, and no overcurrent protection is triggered.

In one possible implementation, referring to fig. 7, the current compensation circuit 3 includes a first voltage generation module 31, a compensation load module 32, and a second voltage generation module 33.

The first voltage generating module 31 is configured to receive a first input voltage and output a first output voltage according to the first input voltage. The first input voltage is linearly related to the supply voltage Vdd. The first output voltage is linearly related to the first input voltage. The first output voltage is linearly related to the supply voltage Vdd. Further, the first input voltage is a times the supply voltage Vdd. The value range of a is 0-1.

The second voltage generating module 33 is configured to receive a second input voltage and output a second output voltage according to the second input voltage. The second input voltage is a reference voltage Vref. The second output voltage is linearly related to the second input voltage. The reference voltage Vref is an internal bandgap reference (bandgap) generation reference voltage. In other words, the second output voltage is linearly related to the reference voltage Vref.

The second output voltage is applied to the input terminal of the compensation load module 32. The first output voltage is loaded at the output terminal of the compensating load module 32 to generate a second compensating current I2. Wherein the first compensation current I1 is obtained according to the second compensation current I2. In other words, the first compensation current I1 may be generated according to the second compensation current I2.

In this embodiment, the first output voltage and the second output voltage are respectively loaded at two opposite ends of the compensation load module 32 to generate the second compensation current I2, since the first output voltage is linearly related to the power voltage Vdd, the second output voltage is linearly related to the reference voltage Vref, and further the second compensation current I2 is linearly related to the power voltage Vdd, so that the first compensation current I1 generated by the second compensation current I2 is also linearly related to the power voltage Vdd. The above may form the first compensation current I1 linearly related to the supply voltage Vdd.

In one possible implementation, referring to fig. 8, the first voltage generating module 31 includes a first operational amplifier a1 and a first transistor P1. The first transistor P1 may be a PMOS transistor or an NMOS transistor. In this embodiment, the first transistor P1 is a PMOS transistor. The first input A1+ of the first operational amplifier A1 is used for loading the first input voltage. The output end of the first operational amplifier A1 is electrically connected with the gate of the first transistor P1. A second input A1-of the first operational amplifier A1 connects the source of the first transistor P1 and the output of the compensating load module 32. The drain of the first transistor P1 is connected to ground.

Ideally, the voltage at the second input A1-of the first operational amplifier A1 is equal to the voltage at the first input A1+ of the first operational amplifier A1, and the first output voltage is equal to the voltage at the second input 22 of the first operational amplifier A1. The voltage at the output of the compensating load module 32 is a times the supply voltage Vdd. The first operational amplifier a1 and the first transistor P1 are arranged to output the input voltage of the first operational amplifier a1 completely under ideal conditions, so that the voltage at the output terminal of the compensation load module 32 is a times of the power supply voltage Vdd. In non-ideal cases, the voltage at the output of the compensating load module 32 is a voltage value linearly related to a times the supply voltage Vdd.

Referring to fig. 8, the second voltage generating module 33 includes a second operational amplifier a2 and a second transistor N1. The second transistor N1 may be a PMOS transistor or an NMOS transistor. In this embodiment, the second transistor N1 is an NMOS transistor. The first input A2+ of the second operational amplifier A2 is used for loading the second input voltage. The output end of the second operational amplifier A2 is electrically connected with the gate of the second transistor N1. A second input A2-of the second operational amplifier A2 is connected to the source of the second transistor N1 and to the input of the compensating load module 32.

Ideally, the voltage at the second input A2-of the second operational amplifier A2 is equal to the voltage at the first input A2+ of the second operational amplifier A2, and the second output voltage is equal to the voltage at the second input 22 of the second operational amplifier A2. The voltage at the input of the compensation load module 32 is the reference voltage Vref. The second operational amplifier a2 and the second transistor N1 are arranged to output the input voltage of the second operational amplifier a2 completely under ideal conditions, so that the voltage at the input terminal of the compensation load module 32 is the reference voltage Vref. In a non-ideal situation, the voltage at the input of the compensation load module 32 is a voltage value linearly related to the reference voltage Vref.

Through the above design, the reference voltage Vref is loaded at the input end of the compensation load module 32, and the power supply voltage Vdd which is a times larger than the reference voltage Vref is loaded at the output end of the compensation load module 32, so that the second compensation current I2 which is linearly related to the power supply voltage Vdd is generated.

Of course, in other embodiments, the supply voltage Vdd may be applied a times at the input end of the compensation load module 32, and the reference voltage Vref may be applied at the output end of the compensation load module 32, so that the second compensation current I2 linearly related to the supply voltage Vdd is generated.

Referring to fig. 7 and 8, the current compensation circuit 3 further includes a current mirror module 34. The current mirror module 34 includes a first output unit 341 and a second output unit 342 that are mirror-symmetric and electrically connected. The input terminal of the first output unit 341 and the input terminal of the second output unit 342 are both loaded with the power supply voltage Vdd. The output terminal of the first output unit 341 outputs a second compensation current I2. The output terminal of the second output unit 342 is used for outputting the first compensation current I1. The first compensation current I1 is linearly related to the second compensation current I2.

Specifically, the first output unit 341 and the second output unit 342 are transistors, wherein the types of the first output unit 341 and the second output unit 342 may be PMOS transistors or NMOS transistors. In this embodiment, the first output unit 341 and the second output unit 342 are both PMOS transistors.

Since the first output unit 341 and the second output unit 342 are arranged in mirror symmetry, the current at the output terminal of the second output unit 342 is equal to the current at the output terminal of the first output unit 341, and thus, the first compensation current I1 is generated according to the second compensation current I2, and the magnitude of the first compensation current I1 is the same as the magnitude of the second compensation current I2.

Specifically, referring to fig. 8, the current compensation circuit 3 at least includes: the circuit comprises a first transistor P1, a third transistor P2, a fourth transistor P3, a second transistor N1, a third resistor R3, a first operational amplifier A1 and a second operational amplifier A2. The gate of the third transistor P2 is connected to the gate of the fourth transistor P3, and the source of the third transistor P2 and the source of the fourth transistor P3 are both connected to the power supply voltage Vdd. The drain of the fourth transistor P3 is connected to output the first compensation current I1, the drain of the third transistor P2 is connected to the drain of the second transistor N1, the drain of the second transistor N1 is connected to the drain of the third transistor P2, the gate of the second transistor N1 is connected to the output stage of the second operational amplifier a2, the gate of the second transistor N1 is connected to the second input terminal a2 of the second operational amplifier a2, the first input terminal a2+ of the second operational amplifier a2 is connected to the reference voltage Vref, the second input terminal a 2-of the second operational amplifier a2 is connected to the source of the second transistor N1, and the output of the second operational amplifier a2 is connected to the gate of the second transistor N1. The third resistor R3 has one end connected to the source of the second transistor N1 and one end connected to the source of the first transistor P1. The source of the first transistor P1 is connected to the second input terminal a1 of the first operational amplifier a1, the drain of the first transistor P1 is grounded, and the gate of the first transistor P1 is connected to the output terminal of the first operational amplifier a 1. The second input terminal a1 of the first operational amplifier a1 is connected to the source of the first transistor P1, the second input terminal a1 of the first operational amplifier a1 is connected to the voltage divider circuit of the power supply voltage Vdd, the input voltage of the voltage divider circuit is Vbat, the magnitude of Vbat is a Vdd voltage division ratio, where a is Vdd voltage division ratio, and the magnitude of the second compensation current I2 is I2 ═ Vref-a Vdd)/R3. After compensation, when the discharge current is larger than k { (VM + I1 × R0) - [ GND + Δv (vdd) ] }/R0, the output of the output end OUT of the comparison circuit 2 is at a high level, and overcurrent protection is triggered; when the discharge current is less than k { (VM + I1 × R0) - [ GND + Δv (vdd) ]/R0, the output of the output terminal OUT of the comparator circuit 2 is at a low level, and the overcurrent protection is not triggered. Wherein, I1 × R0 can offset the influence voltage Δ v (vdd) caused by the on-resistance variation of the charging and discharging MOS transistor, so as to improve the accuracy of the overcurrent protection.

Referring to fig. 9, the selection circuit 4 includes a first control module 41, a first switch module 42 and a second switch module 43. The first switch module 42 electrically connects the first input terminal 21 of the comparison circuit 2 and the output terminal of the second output unit 342. The second switch module 43 electrically connects the second input terminal 22 of the comparison circuit 2 and the output terminal of the second output unit 342. The first control module 41 is configured to control the first switch module 42 to be turned on and the second switch module 43 to be turned off in the discharging mode, so that the first input terminal 21 of the comparison circuit 2 receives the first compensation current I1, and further performs current compensation in the discharging mode, so as to improve accuracy of the over-current protection.

The first control module 41 is configured to control the second switch module 43 to be turned on and the first switch module 42 to be turned off in the charging mode, so that the second input terminal 22 of the comparison circuit 2 receives the first compensation current I1, and then performs current compensation in the charging mode, so as to improve accuracy of detecting the overcurrent protection current.

It should be noted that, when the first compensation current I1 is compensated, multiple detections may be performed, and the magnitude of the first compensation current I1 detected in different times is different, in other words, the magnitude of the first compensation current I1 is continuously adjusted in the multiple detections, and the better first compensation current I1 is determined according to the output value of the comparison circuit 2, so as to more counteract the influence caused by the on-resistance of the MOS transistor, and improve the accuracy of current detection in the overcurrent protection.

In one possible implementation, referring to fig. 10 and 11, the number of the second output units 342 is multiple. Each of the second output units 342 is arranged in mirror symmetry with the first output unit 341. The plurality of second output units 342 are arranged in parallel. The current compensation circuit 3 further comprises an output selection module 35. One end of the output selection module 35 is electrically connected to the output end of each of the second output units 342. The other end of the output selection module 35 is electrically connected to the first switch module 42 and the second switch module 43. The first control module 41 is configured to control the output selection module 35 to select and receive the first compensation current I1 of one or more second output units 342.

Referring to fig. 11, the output selection module 35 includes a plurality of first switch units 351, and one end of each first switch unit 351 is electrically connected to one second output unit 342. The other end of each of the first switching units 351 is electrically connected to the first and

second switching modules

42 and 43. The first switch units 351 may be transistors, and the first control module 41 is configured to control a gate level of each of the first switch units 351 to control the number of the first switch units 351 being turned on. Referring to fig. 9, the first switch module 42 includes a second switch unit 421, and the second switch module 43 includes a third switch unit 431. One end of the second switch unit 421 is connected to the output end of the output selection module 35, one end of the third switch unit 431 is connected to the output end of the output selection module 35, the second switch unit 421 is electrically connected to the first input end 21 of the comparison circuit 2, and the third switch unit 431 is electrically connected to the second input end 22 of the comparison circuit 2.

In the discharging mode, the first control module 41 controls the second switching unit 421 to be turned on, and the third switching unit 431 to be turned off, and controls the amount of turning on of the first switching unit 351 to control the compensation current received by the first input terminal 21 of the comparing circuit 2. For example, the first control module 41 controls a first switch unit 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be the first compensation current I1 output by an output unit; the first control module 41 controls the 2 first switch units 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be 2 times the first compensation current I1. In the charging mode, the first control module 41 controls the third switching unit 431 to be turned on and the second switching unit 421 to be turned off, and controls the amount of the first switching unit 351 to be turned on so as to control the compensation current received by the second input terminal 22 of the comparison circuit 2.

By providing a plurality of second output units 342 connected in parallel and controlling the output selection module 35 to select the branch number of the first compensation current I1 output from the plurality of second output units 342, so that the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times of the first compensation current I1, where N is a positive integer, the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 is adjusted based on the second compensation current I2.

In another possible embodiment, referring to fig. 12, the present embodiment is substantially the same as the above embodiment, and is different from the above embodiment in that the plurality of second output units 342 are arranged in series. One end of the output selection module 35 is electrically connected to the output end of each of the second output units 342. The other end of the output selection module 35 is electrically connected to the first switch module 42 and the second switch module 43. The first control module 41 is configured to control the output selection module 35 to select and receive the first compensation current I1 of one or more second output units 342.

In the discharging mode, the first control module 41 controls the second switching unit 421 to be turned on, and the third switching unit 431 to be turned off, and controls the amount of turning on of the first switching unit 351 to control the compensation current received by the first input terminal 21 of the comparing circuit 2. For example, the total number of the second output units 342 is 10, the 10 second output units 342 are sequentially connected in series, and the gates of the second output units 342 are all electrically connected to the gate of the first output unit 341. The first control module 41 controls the first switch unit 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be 1 time of the first compensation current I1; the first control module 41 controls the first 5 first switch units 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be 0.5 times the first compensation current I1; the first control module 41 controls the 10 first switch units 351 to be turned on to control the compensation current received by the first input terminal 21 of the comparison circuit 2 to be 0.1 times the first compensation current I1. The charging mode is similar to the discharging mode, and is not described herein again.

By arranging a plurality of second output units 342 connected in series and controlling the output selection module 35 to select an effective number of the plurality of second output units 342, the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times of the first compensation current I1, where N ranges from 0 to 1, so that the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 is reduced based on the second compensation current I2.

In yet another possible embodiment, the main difference between the present embodiment and the two embodiments is that a part of the plurality of second output units 342 is arranged in series, and another part is arranged in parallel. The first switch module 42 is electrically connected to an output terminal of each of the second output units 342. The first control module 41 is configured to control the first switch module 42 to select the output terminal of one or more second output units 342 to be conducted with the first input terminal 21 of the comparison circuit 2 or the second input terminal 22 of the comparison circuit 2.

By providing a plurality of second output units 342 connected in series and in parallel and controlling the output selection module 35 to select an effective number of the plurality of second output units 342, so that the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 receives N times of the first compensation current I1, N may be greater than 1 or smaller than 1, and N is not limited to be an integer, thereby more flexibly comparing the compensation current received by the first input terminal 21 or the second input terminal 22 of the circuit 2 based on the second compensation current I2. The adjustment range of the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2 of this embodiment is more flexible than the two embodiments, and the adjustable parameter range is relatively larger.

In one possible implementation, referring to fig. 13, the number of the second output units 342 is multiple. The plurality of second output units 342 includes a first sub-output unit 343 and a second sub-output unit 344. The output terminal of the first sub-output unit 343 is configured to output a first sub-compensation current. The output terminal of the second sub-output unit 344 is used for outputting a second sub-compensation current. The first compensation current I1 is generated according to the first sub compensation current or the second sub compensation current. The first sub-output unit 343 is mirror-symmetric with the first output unit 341, the first sub-output unit 343 is electrically connected to the gate of the first output unit 341, and the first sub-output unit 343 is electrically connected to the source of the first output unit 341. The second sub-output unit 344 is mirror-symmetrical to the first output unit 341, the second sub-output unit 344 is electrically connected to the gate of the first output unit 341, and the second sub-output unit 344 is electrically connected to the source of the first output unit 341. The first sub-output unit 343 and the second sub-output unit 344 may be transistors. The first sub-compensation current has the same magnitude as the second compensation current I2, and the second sub-compensation current has the same magnitude as the second compensation current I2.

Further, the selection circuit 4 includes a first control module 41, a first switch module 42 and a second switch module 43. The first switch module 42 electrically connects the first input terminal 21 of the comparison circuit 2 and the output terminal of the first sub-output unit 343. The second switch module 43 electrically connects the second input terminal 22 of the comparison circuit 2 and the output terminal of the second sub-output unit 344. The first control module 41 is configured to control the first switch module 42 to be turned on and the second switch module 43 to be turned off in the discharging mode, so that the first sub-compensation current is input to the first input terminal 21 of the comparison circuit 2; alternatively, the first control module 41 is configured to control the second switch module 43 to be turned on and the first switch module 42 to be turned off in the charging mode, so that the second sub-compensation current is input to the second input terminal 22 of the comparison circuit 2.

The first input terminal 21 of the comparison circuit 2 is further arranged to receive a first input current. The second input terminal 22 of the comparison circuit 2 is further arranged to receive a second input current. The first input current is a current of a first ground terminal, and the second input current is a current of a second ground terminal.

Optionally, the first input current is a current flowing from the battery 10. The second input current is a current flowing into the load end. The load side is the device that discharges the battery 10. The first input current is used to synthesize the current of the first input terminal 21 of the comparison circuit 2 with the first compensation current I1.

Still alternatively, the first input current is a current flowing into the battery 10 terminal. The second input current is a current flowing out of the charging equipment terminal. The charging device side is an external charging device that charges the battery 10. The second input current is used to synthesize the current at the second input terminal 22 of the comparison circuit 2 with the second compensation current I2.

In one possible implementation, referring to fig. 14, the compensation load module 32 includes a plurality of first load units 321, a first load selection module 322, and a second control module 323. The plurality of first load units 321 are arranged in parallel; alternatively, the plurality of first load units 321 are arranged in series; alternatively, a part of the plurality of first load units 321 may be arranged in series and another part may be arranged in parallel. The first load selection module 322 is electrically connected to the first input terminal 21 of the first voltage generation module 31 and the output terminals of all the first load units 321. The second control module 323 is configured to control the first load selection module 322 to select one or more first load units 321 to be connected to the first voltage generation module 31.

The first load unit 321 may be a resistor. The first load selection module 322 may be a plurality of fourth switching units 324, and each of the fourth switching units 324 is electrically connected to one of the first load units 321 and the first input terminal 21 of the first voltage generation module 31. The second control module 323 controls the parallel connection number or the series connection number of the first load units 321 by controlling on/off of the fourth switch unit 324, so as to adjust a total resistance value of the plurality of first load units 321, thereby adjusting a magnitude of the second compensation current I2, and further adjusting the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2. The present embodiment can adjust the load resistance value of the compensation load module 32 to realize the output of different second compensation currents I2, without increasing the number of the second output units 342, and can reduce the complexity and the occupied area of the current mirror module 34.

In one possible implementation, referring to fig. 15, the current compensation circuit 3 further includes an input voltage adjustment circuit 36. The input voltage adjusting circuit 36 is configured to generate the first input voltage and adjust a magnitude of the first input voltage.

Referring to fig. 16, the input voltage adjusting circuit 36 includes a plurality of second load units 361, a second load selecting module 362 and a third control module 363. The plurality of second load units 361 are arranged in parallel; alternatively, the plurality of second load units 361 are arranged in series; alternatively, some of the second load units 361 are arranged in series, and the other are arranged in parallel; the second load selection module 362 electrically connects the output terminals of all the second load units 361 and the second input terminal 22 of the first voltage generation module 31. The third control module 363 is configured to control the second load selection module 362 to select one or more second load units 361 to be conducted with the first voltage generation module 31.

The second load unit 361 may be a resistor. The second load selection module 362 may be a plurality of fifth switching units 364, and each of the fifth switching units 364 is electrically connected to one of the second load units 361 and the second input terminal 22 of the first voltage generation module 31. The third control module 363 controls the on/off of the fifth switch unit 364 to control the parallel connection number or the series connection number of the second load units 361, so as to adjust the total resistance value of the plurality of second load units 361, thereby adjusting the voltage Vbat of the voltage divider circuit, i.e., adjusting the value of a, and further adjusting the second compensation current I2, so as to adjust the compensation current received by the first input terminal 21 or the second input terminal 22 of the comparison circuit 2.

In this embodiment, a voltage dividing circuit is designed, and a second control module 323 is provided to control the on/off of a fifth switch unit 364 in a second load selection module 362, so as to form different voltage dividing resistors, thereby adjusting the first input voltage of the first voltage generation module 31, and further adjusting the second compensation current I2. The present embodiment can perform voltage adjustment on the first input voltage to realize output of different second compensation currents I2, without increasing the number of second output units 342, and can reduce the complexity and occupied area of the current mirror module 34.

It will be appreciated that the above adjustment modes of the compensation current may be combined to achieve more flexible adjustment.

According to the current detection chip 1, when the power voltage Vdd is too low, internal resistance compensation is performed on the charge-discharge MOS transistor, so that false triggering of a protection circuit is prevented. When the power supply voltage Vdd is too low, internal resistance compensation is carried out on the charging and discharging MOS transistor, so that the amplitude of the charging and discharging MOS transistor along with the change of the grid voltage is reduced, and the false triggering of the protection circuit is prevented.

The embodiment of the present application further provides a battery 10, which includes a battery core 102 and the current detection chip 1 described in any of the above embodiments. The current detection chip 1 is electrically connected to the battery cell 102. The current detection chip 1 is used for detecting current in the charging and discharging process of the battery cell 102.

The embodiment of the application also provides an electronic device 100, and the electronic device 100 comprises the battery 10.

The foregoing is some embodiments of the present application. It should be noted that. As would be apparent to one of ordinary skill in the art. Without departing from the principles of the present application. Several improvements and refinements can also be made. Such modifications and refinements are also considered to be within the scope of the present application.

Claims

1. A current detection chip is used for detecting current of a battery in the charging and discharging processes, and is characterized by comprising:

a current compensation circuit for generating a first compensation current that varies with a variation in a power supply voltage from the battery;

the comparison circuit comprises a first input end and a second input end;

the comparison circuit is used for outputting an indication signal according to a comparison result of currents of a first input end and a second input end of the comparison circuit, wherein the indication signal is used for indicating whether the charging and discharging process of the battery is over-current or not.

2. The current sense chip of claim 1 wherein the current compensation circuit includes a first voltage generation module, a compensation load module, and a second voltage generation module, the first voltage generation module configured to receive a first input voltage and output a first output voltage based on the first input voltage, the first output voltage being linearly related to the supply voltage; the second voltage generation module is configured to receive a second input voltage and output a second output voltage according to the second input voltage, where the second output voltage is loaded at an input end of the compensation load module, and the first output voltage is loaded at an output end of the compensation load module to generate a second compensation current, where the first compensation current is obtained according to the second compensation current.

3. The current detection chip of claim 2, wherein the first voltage generation module comprises a first operational amplifier and a first transistor, a first input terminal of the first operational amplifier is used for loading the first input voltage, an output terminal of the first operational amplifier is electrically connected to a gate of the first transistor, a second input terminal of the first operational amplifier is connected to a source of the first transistor and an output terminal of the compensation load module, and a drain of the first transistor is grounded;

and/or the presence of a gas in the gas,

the second voltage generation module comprises a second operational amplifier and a second transistor, wherein a first input end of the second operational amplifier is used for loading the second input voltage, an output end of the second operational amplifier is electrically connected with a grid electrode of the second transistor, and a second input end of the second operational amplifier is connected with a source electrode of the second transistor and an input end of the compensation load module;

and/or the first input voltage is a times of the power supply voltage, the value range of a is 0-1, and the second input voltage is a reference voltage;

and/or, the current compensation circuit still includes the current mirror module, the current mirror module is including being mirror symmetry and the first output unit and the second output unit of electricity connection, the input of first output unit with the input of second output unit all loads mains voltage, the output of first output unit exports second compensating current, the output of second output unit is used for exporting first compensating current, first compensating current with second compensating current is the linear correlation.

4. The current detection chip of claim 3, wherein the selection circuit comprises a first control module, a first switch module and a second switch module, the first switch module electrically connects the first input terminal of the comparison circuit and the output terminal of the second output unit, the second switch module electrically connects the second input terminal of the comparison circuit and the output terminal of the second output unit, the first control module is configured to control the first switch module to be turned on and the second switch module to be turned off, so that the first input terminal of the comparison circuit receives the first compensation current; or, the second switch module is controlled to be switched on and the first switch module is controlled to be switched off, so that the second input end of the comparison circuit receives the first compensation current.

5. The current detection chip according to claim 4, wherein the number of the second output units is plural, and the plural second output units are arranged in parallel; or, a plurality of the second output units are arranged in series; or, one part of the second output units is arranged in series, and the other part is arranged in parallel; the current compensation circuit further comprises an output selection module, one end of the output selection module is electrically connected with the output end of each second output unit, the other end of the output selection module is electrically connected with the first switch module and the second switch module, and the first control module is used for controlling the output selection module to selectively receive the first compensation current of one or more second output units.

6. The current detection chip according to claim 3, wherein the number of the second output units is plural, the plural second output units include a first sub-output unit and a second sub-output unit, an output terminal of the first sub-output unit is configured to output a first sub-compensation current, an output terminal of the second sub-output unit is configured to output a second sub-compensation current, and the first compensation current is generated according to the first sub-compensation current or the second sub-compensation current.

7. The current detection chip of claim 6, wherein the selection circuit comprises a first control module, a first switch module and a second switch module, the first switch module electrically connects the first input terminal of the comparison circuit and the output terminal of the first sub-output unit, the second switch module electrically connects the second input terminal of the comparison circuit and the output terminal of the second sub-output unit, the first control module is configured to control the first switch module to be turned on and the second switch module to be turned off, so that the first sub-compensation current is input to the first input terminal of the comparison circuit; or, the second switch module is controlled to be switched on and the first switch module is controlled to be switched off, so that the second sub-compensation current is input to the second input end of the comparison circuit.

8. The current detection chip according to any one of claims 2 to 7, wherein the first input terminal of the comparison circuit is further configured to receive a first input current, and the second input terminal of the comparison circuit is further configured to receive a second input current; the first input current is a current flowing out of the battery, the second input current is a current flowing into a load end, the load end is a battery discharging device, and the first input current is used for synthesizing a current of a first input end of the comparison circuit with the first compensation current; or, the first input current is a current flowing into the battery, the second input current is a current flowing out from a charging device terminal, the charging device terminal is a device for charging the battery, and the second input current is used for synthesizing a current of a second input terminal of the comparison circuit with the second compensation current.

9. A battery, characterized by, including electric core and the current detection chip of any one of claims 1-8, the current detection chip is electrically connected with the electric core, the current detection chip is used for carrying out current detection in the charge and discharge process of the electric core.

10. An electronic device comprising the battery of claim 9.