CN114244920A - New and old chip stacking head compatible method and system, and chip - Google Patents
New and old chip stacking head compatible method and system, and chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The invention discloses a compatibility method, a system and a chip of a new chip and an old chip stacking head, wherein the method comprises the steps that when at least one Nth-M-generation chip exists on a transmission path between two Nth-generation chips, a source Nth-generation chip adds an Nth-generation chip head in a forwarded message and adds a first-generation chip head at the same time, and a chip closest to a target Nth-generation chip removes the first-generation chip head from the received message and forwards the message to the target Nth-generation chip. The invention can make the new chip support the function of the old chip while keeping the flexibility, and does not influence the function of the new chip on the transmission path.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a new chip stacking head compatible method, a system for realizing the new chip stacking head compatible method and a chip.
Background
In network communication, network devices, such as switches, routers, etc., are used for processing messages. The switching chip or the routing chip is a core component for processing messages. When the stack function or the frame device design is based, a plurality of message processing chips are needed. However, even for the same chip manufacturer, due to the increasing number of functions supported by the chip, the newly designed chip is more complex than the old chip, and the contents of the header of the stack for interaction are different between different chips.
In order to realize the compatibility of new and old chips, the chip newly designed at present can be compatible with the old chip head, and meanwhile, the chip also has a new chip head with stronger function. However, as chips are continuously changed, more chips are compatible with new chips, and once an old chip appears in a transmission link, all functions on the transmission link fall back to the old chip set. In addition, the new chip may also adopt a mode of designing a basic header and an extension header, for example, a method and an apparatus for implementing a variable-length stacking header in a stacking system disclosed in chinese patent CN106533991B, where the basic header includes basic information, and the basic information includes number information of the extension headers carried. And the chip header of the old chip does not contain the quantity information of the extension header, so that forward compatibility cannot be realized.
Disclosure of Invention
The invention aims to provide a new and old chip stacking head compatible method capable of realizing forward compatibility, and also provides a system and a chip for realizing the new and old chip stacking head compatible method.
In order to achieve the above object, the present invention provides a method for compatible new and old chip stacking heads, including:
when at least one Nth-M generation chip exists on a transmission path between two Nth generation chips, a source Nth generation chip adds a Nth generation chip head in a forwarded message and simultaneously adds a first generation chip head, and a chip closest to the target Nth generation chip removes the first generation chip head from the received message and forwards the message to the target Nth generation chip, wherein a source port in the Nth generation chip head is a message input port of the source Nth generation chip, a target port is a message output port of the target Nth generation chip, the source port in the first generation chip head is a message input port of the source Nth generation chip, the target port is a message output port of the chip closest to the target Nth generation chip, N is greater than M, N is an integer greater than or equal to 3, and M is an integer greater than or equal to 1.
Preferably, when the chip closest to the nth chip is a first-generation chip, an independent forwarding channel only supporting an egress forwarding function is configured in the first-generation chip, and the independent forwarding channel and the original stacking channel point to the same message egress port.
The invention also discloses a compatible system of the new chip stacking head and the old chip stacking head, which comprises at least two Nth generation chips and at least one Nth-M generation chip arranged between the two Nth generation chips, wherein the source Nth generation chip adds the Nth generation chip head and simultaneously adds the first generation chip head in a forwarded message, the chip closest to the target Nth generation chip removes the first generation chip head from the received message and forwards the message to the target Nth generation chip, a source port in the Nth generation chip head is a message input port of the source Nth generation chip, a target port is a message output port of the target Nth generation chip, a source port in the first generation chip head is a message input port of the source Nth generation chip, a target port is a message output port of the chip closest to the target Nth generation chip, N is more than M, N is an integer more than or equal to 3, m is an integer greater than or equal to 1.
Preferably, when the chip closest to the nth chip is a first-generation chip, an independent forwarding channel only supporting an egress forwarding function is configured in the first-generation chip, and the independent forwarding channel and the original stacking channel point to the same message egress port.
The invention also discloses a chip, which is an Nth-generation chip, and when at least one Nth-M-th-generation chip exists between two Nth-generation chips, the Nth-generation chip head is added in a forwarded message and simultaneously a first-generation chip head is added, wherein a source port in the Nth-generation chip head is a message input port of a source Nth-generation chip, a destination port is a message output port of a destination Nth-generation chip, the source port in the first-generation chip head is a message input port of the source Nth-generation chip, a destination port is a message output port of a chip closest to the destination Nth-generation chip, N is more than M, N is an integer more than or equal to 3, and M is an integer more than or equal to 1.
Preferably, the chip is selected from one of an ASIC chip, an FPGA chip, and an NP chip.
The invention has the beneficial effects that:
according to the invention, when a new chip processes a message, a first generation chip header is added besides the latest chip header, the source port of the first generation chip header is the message input port of the new chip, and the output port of the first generation chip header is the output port of the chip closest to the target chip (new chip), so that the chip closest to the target chip (new chip) can POP up (POP) the first generation chip header, the message received by the target chip (new chip) only carries the latest chip header, the flexibility is maintained, the new chip can support the functions of the old chip, and the functions of the new chip on the path are not influenced, namely forward compatibility can be realized.
Drawings
FIG. 1 is a flow chart of a method for compatibility between a new chip stack head and an old chip stack head according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating message processing of old and new chips according to an embodiment of the present invention.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
As shown in fig. 1, the new and old chip stacking head compatible method disclosed in the present invention can make the new chip support the functions of the old chip while maintaining the flexibility and does not affect the functions of the new chip on the transmission path. Specifically, a new and old chip stacking head compatible method includes the following steps:
when at least one Nth-Mth generation chip exists on a transmission path between two Nth generation chips, a source Nth generation chip adds an Nth generation chip header in a forwarded message and simultaneously adds a first generation chip header, wherein a source port in the Nth generation chip header is a message input port of the Nth generation chip, a destination port is a message output port of a destination Nth generation chip, a source port in the first generation chip header is a message input port of the source Nth generation chip, a destination port is a message output port of a chip closest to the destination Nth generation chip, N is greater than M, N is an integer greater than or equal to 3, and M is an integer greater than or equal to 1;
and the chip closest to the target Nth generation chip removes the first generation chip header from the received message and forwards the message to the target Nth generation chip.
Specifically, on the data transmission path, there are a plurality of nth generation chips and a plurality of nth-M generation chips, and there are one or more nth-M generation chips between two nth generation chips, where the nth generation chip generally refers to a new chip and the nth-M generation chip generally refers to an old chip, as shown in fig. 2, on a data transmission path, there are two fourth generation chips (respectively referred to as a fourth generation chip first and a fourth generation chip second), where there are a first generation chip and a third generation chip between the two fourth generation chips, the third generation chip is connected between the fourth generation chip first and the first generation chip, and the first generation chip is connected between the fourth generation chip second and the third generation chip.
In order to realize compatibility of the new chip stacking head and the old chip stacking head, the source Nth generation chip edits the message after receiving the message, so that the first generation chip head is added while the Nth generation chip head is added in the message. The source nth generation chip herein refers to an nth generation chip that receives a message and transmits the message to a destination chip. In the nth chip header, the source port is a message input port of the source nth chip, and the output port is a message output port of the destination nth chip. In the first generation chip header, the source port is a message input port of a source nth generation chip, and the output port is a message output port of a chip closest to a destination nth generation chip. As shown in fig. 2, the message input port of the first fourth generation chip is port 1, the message output port of the second fourth generation chip is port 2, and the message output port of the first generation chip closest to the second fourth generation chip is port P. And when the message 1 enters the first fourth-generation chip, the first fourth-generation chip adds the first fourth-generation chip header and the first-generation chip header in the message. The source port in the fourth generation chip header is port 1 of the fourth generation chip one, the destination port is port 2 of the fourth generation chip, the source port in the first generation chip header is port 1 of the fourth generation chip one, and the destination port is port P of the first generation chip one.
Further, after the nth generation new leader and the first generation new leader are added, the packet is forwarded to a chip nearest to the target nth generation chip, the chip further takes out the first generation chip leader and forwards the first generation chip leader to the target nth generation chip, and the target nth generation chip can remove the nth generation chip leader to obtain the original packet. If the fourth-generation chip I adds the fourth-generation chip header and the first-generation chip header in the message I, the processed message enters the third-generation chip, and the message is directly forwarded to the first-generation chip I because the destination address in the chip header is not the third-generation chip. Because the source port and the destination port in the first generation chip head point to the first generation chip I, the first generation chip I confirms that the message is the message terminated by the first generation chip I, and then the first generation chip head is removed, and only the fourth chip head exists in the message at this time. The first generation chip further forwards the message only containing the fourth generation chip head to a second generation chip, and the second generation chip removes the fourth generation chip head and forwards the message. If the fourth-generation chip I adds the fourth-generation chip header and the first-generation chip header to the message I, the processed message enters the third-generation chip, and the message is directly forwarded to the second-generation chip I because the destination address in the chip header is not the third-generation chip. And the first generation chip further removes the first generation chip header, and only a fourth chip header exists in the message at the moment. Therefore, the second generation chip only receives the message with the fourth generation chip head, and the second generation chip removes the fourth generation chip head and forwards the message.
In this embodiment, when the chip closest to the nth generation chip is the first generation chip, the first generation chip is further configured with an independent forwarding Channel, and the independent forwarding Channel and an original Stacking Channel (Stacking Channel) point to the same message output port. The independent forwarding channel only supports the function of forwarding according to the outlet without any editing and other function configuration, that is, the independent forwarding channel is only used for removing the first generation chip header in the message and forwarding the message without the first generation chip header from the message outlet port. As shown in fig. 2, the chip closest to the second fourth generation chip is the first generation chip, and the first generation chip is configured with an independent forwarding Channel, and the independent forwarding Channel and the original Stacking Channel (Stacking Channel) point to the same message output port, that is, both point to the message output port P.
The invention discloses a new and old chip stacking head compatible system, which comprises at least two Nth generation chips and at least one Nth-M generation chip. At least one Nth-M generation chip is arranged between the two Nth generation chips. When the method is implemented, the source Nth generation chip edits the message after receiving the message, so that the first generation chip header is added while the Nth generation chip header is added in the message. The source nth generation chip herein refers to an nth generation chip that receives a message and transmits the message to a destination chip. In the nth chip header, the source port is a message input port of the source nth chip, and the output port is a message output port of the destination nth chip. In the first generation chip header, the source port is a message input port of a source nth generation chip, and the output port is a message output port of a chip closest to a destination nth generation chip.
Further, after the nth generation new leader and the first generation new leader are added, the packet is forwarded to a chip nearest to the target nth generation chip, the chip further takes out the first generation chip leader and forwards the first generation chip leader to the target nth generation chip, and the target nth generation chip can remove the nth generation chip leader to obtain the original packet.
In this embodiment, when the chip closest to the nth generation chip is the first generation chip, the first generation chip is further configured with an independent forwarding Channel, and the independent forwarding Channel and an original Stacking Channel (Stacking Channel) point to the same message output port. The independent forwarding channel only supports the function of forwarding according to the outlet without any editing and other function configuration, that is, the independent forwarding channel is only used for removing the first generation chip header in the message and forwarding the message without the first generation chip header from the message outlet port. As shown in fig. 2, the chip closest to the second fourth generation chip is the first generation chip, and the first generation chip is configured with an independent forwarding Channel, and the independent forwarding Channel and the original Stacking Channel (Stacking Channel) point to the same message output port, that is, both point to the message output port P.
The invention also discloses a chip, which is an Nth-generation chip, and when at least one Nth-M-th-generation chip exists between two Nth-generation chips, the Nth-generation chip head is added in a forwarded message and simultaneously a first-generation chip head is added, wherein a source port in the Nth-generation chip head is a message input port of a source Nth-generation chip, a destination port is a message output port of a destination Nth-generation chip, the source port in the first-generation chip head is a message input port of the source Nth-generation chip, a destination port is a message output port of a chip closest to the destination Nth-generation chip, N is less than M, N is an integer greater than or equal to 3, and M is an integer greater than or equal to 1. For details, it is not described herein any more.
In this embodiment, the chip may be an ASIC chip, an FPGA chip, an NP chip, or the like, and may be selected according to actual requirements.
According to the invention, when a new chip processes a message, a first generation chip head is added besides the latest chip head, the source port of the first generation chip head is the message input port of the new chip, and the output port of the first generation chip head is the output port of the chip closest to the target chip (new chip), so that the chip closest to the target chip (new chip) can POP up the first generation chip head (POP), the message received by the target chip (new chip) only carries the latest chip head, the flexibility is maintained, the new chip can support the functions of the old chip, and the functions of the new chip on the path are not influenced, namely forward compatibility can be realized.
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (6)
1. A new and old chip stacking head compatibility method is characterized by comprising the following steps:
when at least one Nth-Mth generation chip exists on a transmission path between two Nth generation chips, a source Nth generation chip adds an Nth generation chip head in a forwarded message and simultaneously adds a first generation chip head, wherein a source port in the Nth generation chip head is a message input port of the source Nth generation chip, a destination port is a message output port of a destination Nth generation chip, a source port in the first generation chip head is a message input port of the source Nth generation chip, a destination port is a message output port of a chip closest to the destination Nth generation chip, N is larger than M, N is an integer larger than or equal to 3, and M is an integer larger than or equal to 1;
and the chip closest to the target Nth generation chip removes the first generation chip header from the received message and forwards the message to the target Nth generation chip.
2. The method of claim 1, wherein when the nearest chip to the target Nth generation chip is a first generation chip, an independent forwarding channel only supporting per-egress forwarding is configured in the first generation chip, and the independent forwarding channel and the original stacking channel point to the same message egress port.
3. A compatible system of a new chip stacking head and an old chip stacking head is characterized by comprising at least two Nth generation chips and at least one Nth-M generation chip arranged between the two Nth generation chips, wherein a source Nth generation chip adds a first generation chip head while adding an Nth generation chip head in a forwarded message, a chip closest to a destination Nth generation chip removes the first generation chip head from the received message and forwards the message to the destination Nth generation chip, a source port in the Nth generation chip head is a message input port of the source Nth generation chip, a destination port is a message output port of the destination Nth generation chip, a source port in the first generation chip head is a message input port of the source Nth generation chip, a destination port is a message output port of the chip closest to the destination Nth generation chip, N is more than M, and N is an integer more than or equal to 3, m is an integer greater than or equal to 1.
4. The system of claim 3, wherein when the nearest chip to the nth chip is the first chip, an independent forwarding channel only supporting the forwarding function by egress is configured in the first chip, and the independent forwarding channel and the original stacking channel point to the same message egress port.
5. The utility model provides a chip, its characterized in that, the chip is the Nth generation chip, just when the Nth generation chip has at least one Nth-M generation chip between two Nth generation chips, add the first generation chip head in the time of adding the Nth generation chip head in the message that forwards, wherein, source port is the message input port of source Nth generation chip in the Nth generation chip head, and the destination port is the message exit port of purpose Nth generation chip, and source port is the message input port of source Nth generation chip in the first generation chip head, and the destination port is the message exit port of the nearest chip of purpose Nth generation chip, and N is greater than M, and N is the integer that is greater than or equal to 3, and M is the integer that is greater than or equal to 1.
6. The chip of claim 5, wherein the chip is selected from one of an ASIC chip, an FPGA chip, and an NP chip.
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