CN114244742B - Link detection circuit, ethernet transceiver, control method and medium - Google Patents
Link detection circuit, ethernet transceiver, control method and medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
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- H—ELECTRICITY
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- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
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Abstract
The invention discloses a link detection circuit, an Ethernet transceiver and a control method. The link detection circuit comprises a signal input port, a link judgment circuit and a signal output port; the signal input port is connected with the LOS port of the optical port module and is used for receiving the LOS signal of the optical port module; the input end of the link decision circuit is connected with the signal input port, when LOS signals detected in a preset period are all high level, the link decision circuit outputs high level signals, and when the LOS signals detected in the preset period have low level, the link decision circuit outputs low level signals in a time period corresponding to a preset period from the time of detecting the low level; the signal output port is connected with the output end of the link decision circuit and used for outputting a high level signal or a low level signal output by the link decision circuit. By eliminating the jitter of the LOS signal, the problem caused by frequent switching of an optical interface and an electric interface is solved.
Description
Technical Field
The present invention relates to the field of ethernet transceivers, and in particular, to a link detection circuit, an ethernet transceiver, and a control method.
Background
The ethernet optical fiber transceiver generally has an ethernet optical port and an electrical port, and when the two interfaces are in a COMBO mode, only one interface normally works, and generally, the priority of the optical port is higher than that of the electrical port, that is, when the link detects an optical port link, the optical port is switched to optical port communication, and when the optical port link is disconnected, the optical port is switched back to electrical port communication.
However, in general, optical fiber communication is long-distance transmission, application scenarios are diversified, and the optical fiber communication is most likely to be applied to a severe environment, once jitter occurs in the severe environment, an optical fiber signal may be temporarily disconnected, and at this time, an electrical port communication state will be entered, and when the jitter disappears, after the optical fiber signal is restored to be connected, the optical fiber signal will be switched to optical port communication again, but if frequent switching is performed, user experience will be greatly affected.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a link detection circuit, an Ethernet transceiver and a control method, which are used for solving the problem caused by frequent switching of an optical interface and an electric interface.
According to a first aspect of the present invention, there is provided a link detection circuit for selection decision of an optical interface module and an electrical interface module of an ethernet transceiver, comprising a signal input port, a link decision circuit and a signal output port;
the signal input port is connected with an LOS port of the optical port module and is used for receiving an LOS signal of the optical port module, wherein the LOS signal is at a high level when the optical port module is in a disconnection state, and the LOS signal is at a low level when the optical port module is in a connection state;
the input end of the link decision circuit is connected with the signal input port, when LOS signals detected in a preset period are all high level, the link decision circuit outputs high level signals, and when the LOS signals detected in the preset period have low level, the link decision circuit outputs low level signals in a time period corresponding to a preset period from the time of detecting the low level;
the signal output port is connected with the output end of the link decision circuit and used for outputting a high level signal or a low level signal output by the link decision circuit.
In some embodiments, the link decision circuit comprises an and gate and no less than two flip-flops;
at least two triggers are connected in series, the series connection mode is that the input end of the next trigger is connected with the output end of the previous trigger, the clock ends of all the triggers are connected with the clock, and the input end of the first trigger is connected with the signal input port;
the AND gate comprises different input ends, each input end of the AND gate is respectively connected with the output ends of different triggers, and the output end of the AND gate is connected with the signal output port.
In some embodiments, a phase-locked loop is connected between the clock and the clock end of the flip-flop, and the phase-locked loop is used for clock frequency division.
In some embodiments, the flip-flop includes a plurality of flip-flops, and a switch is connected between an output of each flip-flop and an input of the and gate, and is configured such that at least two flip-flops have outputs that communicate with an input of the and gate.
According to a second aspect of the present invention, there is provided an ethernet transceiver comprising an ethernet communication module, an electrical port module, an optical port module and the above-mentioned link detection circuit;
the Ethernet communication module is used for converting the digital signal into an analog signal;
the input end of the electric port module is connected with the electric port output end of the Ethernet communication module, and the electric port module is used for electric port network mode communication;
the input end of the optical port module is connected with the optical port output end of the Ethernet communication module, and the optical port module is used for optical port network mode communication;
the signal input port of the link detection circuit is connected with the LOS port of the optical port module, and the signal output port of the link detection circuit is connected with the signal detection port of the Ethernet communication module.
In some embodiments, the ethernet communication device further comprises a CPU module, an output terminal of the CPU module is connected to an input terminal of the ethernet communication module, and the CPU module is configured to transmit communication data to the ethernet communication module.
According to a third aspect of the present invention, there is provided a method for controlling an ethernet transceiver, for selecting and deciding an optical interface module and an electrical interface module of the ethernet transceiver, comprising:
detecting an LOS signal of the optical interface module, wherein the LOS signal is at a high level when the optical interface module is in a disconnection state, and the LOS signal is at a low level when the optical interface module is in a connection state;
when the LOS signals detected in the preset period are all high level, high level signals are output to the Ethernet communication module, and when the LOS signals detected in the preset period have low level, low level signals are output to the Ethernet communication module in a time period corresponding to the preset period from the time when the low level is detected;
the Ethernet communication module is switched to the optical port module to carry out optical port network mode communication based on the received low level signal, or is switched to the electrical port module to carry out electrical port network mode communication based on the received high level signal.
In some embodiments, the time of the preset period is changed by dividing the clock.
According to a fourth aspect of the present invention, there is provided a storage medium including a stored program, wherein the program executes the control method of the ethernet transceiver of any one of the above.
According to a fifth aspect of the invention, there is provided a processor for running a program, wherein the program when running performs the method of controlling an ethernet transceiver of any of the above.
Compared with the prior art, the link detection circuit, the Ethernet transceiver and the control method of the invention carry out selection judgment on the optical interface module and the electrical interface module by introducing the link judgment circuit, when LOS signals are all high level, the link judgment circuit outputs high level signals, when LOS signals detected in a preset period have low level, the link judgment circuit outputs low level signals in a time period corresponding to the preset period from the time of detecting the low level, thereby achieving the purpose of eliminating jitter of the LOS signals and solving the problem caused by frequent switching of the optical interface and the electrical interface due to jitter in severe environment.
Drawings
FIG. 1 is a first schematic diagram of a link detection circuit according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a link detection circuit according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for controlling an ethernet transceiver according to an embodiment of the present invention.
The reference numbers illustrate: the system comprises a signal input port 100, a link decision circuit 200, an AND gate 210, a flip-flop 220, a clock 230, a signal output port 300, a CPU module 400, an Ethernet communication module 500, an electrical interface module 600 and an optical interface module 700.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example 1
Fig. 1 schematically shows a link detection circuit according to an embodiment of the present invention. As shown in fig. 1, the link detection circuit is used for selection and decision of an optical interface module and an electrical interface module of an ethernet transceiver, and specifically includes a signal input port 100, a link decision circuit 200, and a signal output port 300; the Signal input port 100 is connected to a LOS (LOSs of Signal) port of the optical port module, and the Signal input port 100 is configured to receive a LOS Signal of the optical port module, where the LOS Signal is at a high level when the optical port module is in a disconnection state, and the LOS Signal is at a low level when the optical port module is in a connection state; the input end of the link decision circuit 200 is connected to the signal input port 100, when all LOS signals detected in a preset period are at a high level, the link decision circuit 200 outputs a high level signal, and when all LOS signals detected in the preset period are at a low level, the link decision circuit 200 outputs a low level signal in a time period corresponding to a preset period from the time when the low level is detected; the signal output port 300 is connected to an output terminal of the link decision circuit 200, and the signal output port 300 is used for outputting a high level signal or a low level signal output by the link decision circuit 200.
The link decision circuit 200 includes an and gate 210 and at least two flip-flops 220; not less than two flip-flops 220 are connected in series, the series connection is that the input end of the next flip-flop 220 is connected with the output end of the previous flip-flop 220, the clock ends of all the flip-flops 220 are connected with the clock 230, and the input end of the first flip-flop 220 is connected with the signal input port 100 (the signal input port 100 may be the input end of the first flip-flop 220, that is, the input end of the link decision circuit 200); the and gate 210 includes different input terminals, each input terminal of the and gate 210 is connected to an output terminal of a different flip-flop 220, and an output terminal of the and gate 210 is connected to a signal output port 300 (which may be an output terminal of the and gate 210, i.e., an output terminal of the link decision circuit 200), wherein the flip-flop 220 is a D flip-flop, and the link decision circuit 200 may be integrated in an FPGA (field programmable gate array).
To illustrate the principle of the link decision circuit 200, the present embodiment is described with a limited number of flip-flops 220, specifically four flip-flops 220, as can be seen from fig. 1, the link decision circuit 200 is composed of four flip-flops 220 and a four-channel and gate 210, an LOS signal enters the four-channel and gate 210 after passing through the four flip-flops 220, when the LOS signal is in an unstable state and has jitter, for example, the LOS signal is high at the beginning (i.e., the optical port module is disconnected due to jitter), temporarily at the first clock latching time, the LOS signal is input from the input terminal (D) of the first flip-flop 220, the LOS signal is output from the output terminal (Q) after being latched by the first flip-flop 220 is high, the first input of the four-channel and gate 210 is also high, but due to signal jitter, when the LOS signal goes low (i.e., the optical port module is temporarily restored to be connected due to jitter) at the second clock latching time, the output of the output terminal of the first flip-flop 220 after latching becomes low, although the output of the second flip-flop 220 after the clock latching of the previous flip-flop 220 is high, the output of the second flip-flop 220 at the second clock latching time is also high, since the output terminal of the first flip-flop 220 has already become low, all the four-channel and gates 210 still output low, and the and gate 210 can output a high-level signal only when all four input signals of the and gate 210 are high, so as to achieve the purpose of removing jitter of the LOS signal, correspondingly, when one input signal of the and gate 210 is low, the and gate 210 outputs a low-level signal.
Example 2
As a second embodiment of the present invention, only the differences from the first embodiment will be described below. The difference is that a phase-locked loop is connected between the clock 230 and the clock end of the flip-flop 220, and the frequency of the clock 230 is divided by the phase-locked loop, so that the sampling period of the signal can be adjusted at will, the corresponding time of the preset period can be adjusted, the use is more flexible, and the existing phase-locked loop of the PLL can be adopted for the phase-locked loop.
Example 3
As a third embodiment of the present invention, only the differences from the first embodiment will be described below. The difference is that the number of the flip-flops 220 is multiple, a switch is connected between the output terminal of each flip-flop 220 and the input terminal of the and gate 210, and the output terminals of at least two flip-flops 220 are set to be communicated with the input terminal of the and gate 210, and for the adjustment of the time of the preset period, the number of the communicated flip-flops 220 and the and gate 210 can be adjusted, so that the flexibility of LOS signal jitter elimination is improved.
Example 4
Fig. 2 schematically shows an ethernet transceiver according to an embodiment of the present invention. As shown in fig. 3, the ethernet transceiver includes a CPU module 400, an ethernet communication module 500, an electrical interface module 600, an optical interface module 700, and the above-mentioned link detection circuit.
The CPU module 400 includes the minimum systems of the whole device, i.e., a CPU, a memory chip, and a FLASH chip, and is responsible for the operation and control of the whole device; the ethernet communication module 500 is a PHY (physical layer) chip AR8033, and includes interfaces of an electrical port module and an optical port module, which are respectively connected to the electrical port module 600 and the optical port module 700, and is responsible for implementing the ethernet communication function, an input end of a link decision circuit 200 in the link detection circuit is connected to an LOS port of the optical port module 700, an input end of the link decision circuit 200 is connected to a signal detection port (SD, signal detection) of the ethernet communication module 500, and an interface responsible for analyzing and determining whether the ethernet module finally implements communication is the electrical port module or the optical port module.
Specifically, the CPU module 400 of the ethernet transceiver sends data to be communicated to the ethernet communication module 500 through an RGMII (reduced gigabit media independent interface) interface; after receiving the data from RGMII, the ethernet communication module (chip AR 8033) 500 buffers the data, converts the buffered data into an analog signal through DAC, and the data converted into the analog signal is routed to the electrical interface module 600 through an MDI (media dependent interface) interface on one path and to the optical interface module 700 through an SERDES (parallel-serial-parallel converter) interface on the other path. In the prior art, if the optical fiber of the optical interface module 700 receives light through the optical fiber, an LOS signal is generated, and the signal is directly sent to the SD pin of the ethernet communication module 500 (chip AR 8033) for judgment, but the present invention will add the link judgment circuit 200, first extract and analyze the LOS signal of the optical interface module 700, the link judgment circuit 200 removes the LOS signal and outputs the LOS signal to the SD detection pin of the ethernet communication module 500 (chip AR 8033), and the ethernet communication module 500 (chip AR 8033) will finally determine whether the link is an electrical port or an optical port according to the signal.
Aiming at the condition that the Ethernet transceiver is possibly switched frequently to cause network blockage in a severe environment, the invention judges the optical interface module 700 by introducing a new circuit, if the optical interface module 700 only causes signal instability due to transient jitter, the switching to the electric interface module 600 is not triggered to communicate, thus solving the problem of network blockage caused by frequent link switching.
Example 5
Fig. 3 schematically shows a method of controlling an ethernet transceiver according to an embodiment of the present invention. As shown in fig. 3, the method for controlling an ethernet transceiver is used for controlling the ethernet transceiver, and is mainly used for selection and decision of an optical interface module and an electrical interface module of the ethernet transceiver, and includes:
s100, detecting an LOS signal of the optical port module, wherein the LOS signal is at a high level when the optical port module is in a disconnection state, and the LOS signal is at a low level when the optical port module is in a connection state;
s200, when the LOS signals detected in the preset period are all in high level, outputting high level signals to the Ethernet communication module, and when the LOS signals detected in the preset period have low level, outputting low level signals to the Ethernet communication module in a time period corresponding to the preset period from the time when the low level is detected;
wherein the time of the preset period can also be changed by dividing the clock.
And S300, the Ethernet communication module is switched to the optical port module to carry out optical port network mode communication based on the received low level signal or switched to the electrical port module to carry out electrical port network mode communication based on the received high level signal.
When the Ethernet communication module receives a high-level signal, if the Ethernet communication module uses the electric port module to carry out electric port network mode communication at the moment, the Ethernet communication module does not act, and if the Ethernet communication module uses the optical port module to carry out optical port network mode communication at the moment, the Ethernet communication module is switched to the electric port module to carry out electric port network mode communication; when the Ethernet communication module receives the low level signal, if the Ethernet communication module uses the electric port module to carry out electric port network mode communication, the Ethernet communication module is switched to the optical port module to carry out optical port network mode communication, and if the Ethernet communication module uses the optical port module to carry out communication, the Ethernet communication module does not act.
Example 5
There is provided a storage medium comprising a stored program, wherein the program executes the above-mentioned method of controlling an ethernet transceiver.
Example 6
A processor is provided, the processor is used for running a program, wherein the program executes the control method of the ethernet transceiver when running.
Compared with the prior art, the link detection circuit, the Ethernet transceiver and the control method solve the problem caused by frequent switching of an optical interface and an electric interface by eliminating the jitter of the LOS signal.
What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (8)
1. A link detection circuit for selection decision of an optical interface module and an electrical interface module of an ethernet transceiver, comprising:
the optical fiber interface module comprises a signal input port, a signal output port and a control module, wherein the signal input port is connected with an LOS port of the optical port module and is used for receiving an LOS signal of the optical port module, the LOS signal is at a high level when the optical port module is in a disconnection state, and the LOS signal is at a low level when the optical port module is in a connection state;
a link decision circuit, an input end of which is connected to the signal input port, and when the LOS signals detected in a preset period are all at a high level, the link decision circuit outputs a high-level signal, and when the LOS signals detected in the preset period have a low level, the link decision circuit outputs a low-level signal in a time period corresponding to a preset period from the time when the low level is detected; the link decision circuit includes:
the serial connection mode is that the input end of the next trigger is connected with the output end of the previous trigger, the clock ends of all the triggers are connected with a clock, and the input end of the first trigger is connected with a signal input port;
the AND gate comprises different input ends, each input end of the AND gate is respectively connected with the output ends of different triggers, and the output end of the AND gate is connected with the signal output port;
and the signal output port is connected with the output end of the link judgment circuit and is used for outputting the high-level signal or the low-level signal output by the link judgment circuit.
2. The link detection circuit according to claim 1, wherein a phase-locked loop is connected between the clock and a clock terminal of the flip-flop, the phase-locked loop being configured to divide the clock frequency.
3. The link detection circuit according to claim 1, wherein the flip-flop includes a plurality of flip-flops, and a switch is connected between an output terminal of each flip-flop and an input terminal of the and gate, and is configured such that output terminals of at least two flip-flops communicate with the input terminal of the and gate.
4. An ethernet transceiver, comprising:
an Ethernet communication module for converting a digital signal to an analog signal;
the input end of the electric port module is connected with the electric port output end of the Ethernet communication module, and the electric port module is used for electric port network mode communication;
an input end of the optical port module is connected with an optical port output end of the Ethernet communication module, and the optical port module is used for optical port network mode communication;
the link detection circuit of any one of claims 1 to 3, said signal input port being connected to a LOS port of said optical port module and said signal output port being connected to a signal detection port of said Ethernet communications module.
5. An ethernet transceiver in accordance with claim 4, further comprising a CPU module, wherein an output of said CPU module is connected to an input of said ethernet communication module, said CPU module is configured to transmit communication data to said ethernet communication module.
6. A method for controlling an ethernet transceiver, wherein the method is used for selection decision of an optical interface module and an electrical interface module of the ethernet transceiver, and comprises:
the optical interface module comprises a signal input port, a signal output port and an LOS (line of sight) port, wherein the signal input port is connected with the LOS port of the optical interface module and is used for receiving an LOS signal of the optical interface module, the LOS signal is at a high level when the optical interface module is in a disconnection state, and the LOS signal is at a low level when the optical interface module is in a connection state;
the input end of the link decision circuit is connected with the signal input port, when the LOS signals detected in the preset period are all high level, high level signals are output to the Ethernet communication module, and when the LOS signals detected in the preset period have low level, low level signals are output to the Ethernet communication module in a time period corresponding to the preset period from the time when the low level is detected; the link decision circuit includes:
the trigger circuit comprises at least two triggers, wherein the at least two triggers are connected in series, the series connection mode is that the input end of the next trigger is connected with the output end of the previous trigger, the clock ends of all the triggers are connected with a clock, and the input end of the first trigger is connected with a signal input port;
the AND gate comprises different input ends, each input end of the AND gate is respectively connected with the output ends of different triggers, and the output end of the AND gate is connected with the signal output port;
the Ethernet communication module is switched to the optical port module to carry out optical port network mode communication based on the received low level signal, or is switched to the electrical port module to carry out electrical port network mode communication based on the received high level signal.
7. The Ethernet transceiver control method of claim 6, wherein the time of the preset period is changed by dividing the clock frequency.
8. A storage medium characterized in that it comprises a stored program, wherein the program executes the method of controlling an ethernet transceiver of any one of claims 6 to 7.
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| CN1674547A (en) * | 2005-02-20 | 2005-09-28 | 黄炜 | Optical/electric interface module space multiplexing method and apparatus used for Ethernet SFP interface |
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| US6377082B1 (en) * | 2000-08-17 | 2002-04-23 | Agere Systems Guardian Corp. | Loss-of-signal detector for clock/data recovery circuits |
| CN102347992B (en) * | 2010-07-29 | 2015-02-04 | 研祥智能科技股份有限公司 | Network device and network server capable of supporting photoelectric switching |
| CN106101032B (en) * | 2016-08-11 | 2020-02-04 | 迈普通信技术股份有限公司 | Method and device for COMBO interface self-adaptive Ethernet interface |
| CN109217940A (en) * | 2018-10-08 | 2019-01-15 | 深圳市三旺通信技术有限公司 | A kind of Combo mouthfuls of switching circuit |
| CN111431604B (en) * | 2020-03-27 | 2023-03-14 | 青岛海信宽带多媒体技术有限公司 | Method for reporting LOS signal and optical module |
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| CN1674547A (en) * | 2005-02-20 | 2005-09-28 | 黄炜 | Optical/electric interface module space multiplexing method and apparatus used for Ethernet SFP interface |
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