CN114244109B

CN114244109B - Control circuit and method for DC-DC converter and DC-DC converter

Info

Publication number: CN114244109B
Application number: CN202111657414.8A
Authority: CN
Inventors: 陈登政; 苏咨云
Original assignee: Agco Microelectronics Shenzhen Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-08-12
Anticipated expiration: 2041-12-30
Also published as: CN114244109A

Abstract

The present disclosure provides a control circuit, a method and a DC-DC converter for a DC-DC converter, relating to the field of control of DC-DC converters, the DC-DC converter comprising a first switch and a second switch connected in series, the control circuit comprising: a pulse signal output circuit configured to output a pulse signal having a pulse of a preset level according to an output signal of the DC-DC converter; a PWM controller configured to control the first switch to be on for a first duration and to be off for at least a second duration in response to the pulse; controlling the second switch to be switched off when the first switch is switched on and to be switched on when the first switch is switched off; a monitoring circuit configured to transmit a one-time adjustment indication signal in a case where the pulse signal is monitored to be at a preset level at any one of a start time to an end time of the second duration; and an adjustment circuit configured to perform an adjustment operation including at least one of increasing the first duration and decreasing the second duration in response to the one-time adjustment instruction signal.

Description

Control circuit and method for DC-DC converter and DC-DC converter

Technical Field

The present disclosure relates to the field of control of DC-DC (direct current-direct current) converters, and in particular to a control circuit and method for a DC-DC converter and a DC-DC converter.

Background

The DC-DC converter is a voltage converter that converts an input voltage and outputs a fixed voltage. DC-DC converters are divided into three categories: a step-up DC-DC converter, a step-down DC-DC converter, and a step-up/step-down DC-DC converter.

The inventors are aware of a DC-DC converter comprising two switches connected in series between an input terminal and a ground terminal of the DC-DC converter. The two switches are controlled to operate in opposite directions, i.e. when one switch is on, the other switch is off.

Disclosure of Invention

According to an aspect of the embodiments of the present disclosure, there is provided a control circuit for a DC-DC converter, the DC-DC converter including a first switch and a second switch connected in series, the first switch being connected between an input terminal of the DC-DC converter and the second switch, the second switch being connected between the first switch and a ground terminal, the control circuit including: a pulse signal output circuit configured to output a pulse signal having a pulse of a preset level according to an output signal of the DC-DC converter; a Pulse Width Modulation (PWM) controller configured to control the first switch to be on for a first duration and to be off for at least a second duration after the first duration in response to the pulse; controlling the second switch to be switched off when the first switch is switched on and to be switched on when the first switch is switched off; a monitoring circuit configured to transmit a one-time adjustment indication signal when the pulse signal is monitored to be at the preset level at a specific time, wherein the specific time is any one of a start time to an end time of a second duration; and an adjustment circuit configured to perform an adjustment operation in response to the adjustment indication signal once, the adjustment operation including at least one of increasing the first duration and decreasing the second duration.

In some embodiments, the particular time is an end time of the second duration.

In some embodiments, the monitoring circuit is configured to sample the pulse signal at the specific time to obtain a sampled signal; and under the condition that the sampling signal is at the preset level, sending the adjustment indicating signal once.

In some embodiments, the first duration is a first value and a second value before and after the first adjustment operation is performed, and the second duration is a third value and a fourth value before and after the first adjustment operation is performed, wherein the second value is greater than the first value and/or the fourth value is less than the third value; the monitoring circuit is further configured to compare a preset time threshold with a third duration for which the first switch is turned off, in a case where the first duration is the second value or the second duration is the fourth value, wherein the preset time threshold is not less than the third value; sending a one-time reset indication signal under the condition that the preset time threshold is not more than the third duration; the adjustment circuit is further configured to perform a reset operation in response to the reset indication signal once, the reset operation including at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

In some embodiments, the monitoring circuit comprises: a sampling circuit configured to sample the pulse signal at the specific time to obtain the sampling signal; under the condition that the sampling signal is at the preset level, the adjustment indicating signal is sent once; a first comparator configured to compare the preset time threshold with a third duration in a case where the first duration is the second value or the second duration is the fourth value; sending a trigger signal once under the condition that the preset time threshold is not more than the third duration; a resetter configured to transmit the reset indication signal once in response to the trigger signal once.

In some embodiments, the adjustment circuit comprises: a storage circuit configured to store a first time parameter corresponding to a first duration and a second time parameter corresponding to a second duration; adjusting at least one of a first time parameter and a second time parameter in response to the adjustment indication signal at one time, so that the adjustment operation is performed at one time; resetting at least one of a first time parameter and a second time parameter in response to the reset indication signal at one time, so that the reset operation is performed at one time; a first timer configured to start timing in response to the pulse until the timing is a first duration corresponding to a first time parameter currently stored by the storage circuit; and the second timer is configured to start timing at the termination moment of the first duration until the timed time is a second duration corresponding to the second time parameter currently stored by the storage circuit.

In some embodiments, the preset time threshold is greater than the third value and less than 1.5 times the third value.

In some embodiments, the adjustment circuit comprises: a storage circuit configured to store a first time parameter corresponding to a first duration and a second time parameter corresponding to a second duration; adjusting at least one of a first time parameter and a second time parameter in response to the adjustment indication signal at one time, so that the adjustment operation is performed at one time; a first timer configured to start timing in response to the pulse until the timing is a first duration corresponding to a first time parameter currently stored by the storage circuit; and the second timer is configured to start timing at the termination moment of the first duration until the timed time is a second duration corresponding to the second time parameter currently stored by the storage circuit.

In some embodiments, the pulse signal output circuit includes: a sawtooth wave signal generator configured to generate a sawtooth wave signal; and an output sub-circuit configured to output the pulse signal according to the output signal, the sawtooth wave signal, and a reference signal.

In some embodiments, the output sub-circuit comprises: an arithmetic circuit configured to output an intermediate signal according to one of the sawtooth wave signal and the reference signal and the output signal; and a second comparator configured to output the pulse signal according to the other one of the sawtooth wave signal and the reference signal, and the intermediate signal.

In some embodiments, the operational circuit is a third comparator and the one signal is the reference signal.

In some embodiments, the arithmetic circuit is a multiplier and the one signal is the sawtooth signal.

In some embodiments, the adjusting is operative to decrease the second duration.

In some embodiments, the increase in the first duration is the same and/or the decrease in the second duration is the same in any two adjustment operations.

According to another aspect of the embodiments of the present disclosure, there is provided a control method for a DC-DC converter including a first switch and a second switch connected in series, the first switch being connected between an input terminal of the DC-DC converter and the second switch, the second switch being connected between the first switch and a ground terminal, the control method including: the pulse signal output circuit outputs a pulse signal according to an output signal of the DC-DC converter, wherein the pulse signal has a pulse with a preset level; the PWM controller responds to the pulse, and controls the first switch to be switched on for a first duration and to be switched off at least for a second duration after the first duration, wherein the second switch is controlled by the PWM controller to be switched off when the first switch is switched on and to be switched on when the first switch is switched off; the monitoring circuit sends a primary adjustment indicating signal under the condition that the pulse signal is monitored to be at the preset level at a specific moment, wherein the specific moment is any one moment from the starting moment to the ending moment of the second duration; the adjustment circuit performs an adjustment operation in response to the adjustment indication signal once, the adjustment operation including at least one of increasing the first duration and decreasing the second duration.

In some embodiments, the particular time is an end time of the second duration.

In some embodiments, the monitoring circuit, in case it is monitored that the pulse signal is at the preset level at a specific time, sending an adjustment indication signal comprises: the monitoring circuit samples the pulse signal at the specific moment to obtain a sampling signal; and the monitoring circuit sends the adjustment indicating signal once under the condition that the sampling signal is at the preset level.

In some embodiments, the first duration is a first value and a second value before and after the first adjustment operation is performed, and the second duration is a third value and a fourth value before and after the first adjustment operation is performed, wherein the second value is greater than the first value and/or the fourth value is less than the third value; the control method further comprises the following steps: the monitoring circuit compares a preset time threshold with a third duration of disconnection of the first switch under the condition that the first duration is a second value or the second duration is a fourth value, wherein the preset time threshold is not less than the third value; the monitoring circuit sends a one-time reset indicating signal under the condition that the preset time threshold is not more than the third duration; the adjustment circuit performs a reset operation in response to the reset indication signal once, the reset operation including at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

In some embodiments, the monitoring circuit includes a sampling circuit, a first comparator, and a resetter; wherein, the sending of the one-time adjustment indication signal by the monitoring circuit when monitoring that the pulse signal is at the preset level at a specific time comprises: the sampling circuit samples the pulse signal at the specific moment to obtain the sampling signal; the sampling circuit sends the adjustment indicating signal once under the condition that the sampling signal is at the preset level; the monitoring circuit compares the preset time threshold with a third duration for which the first switch is open, in the case where the first duration is the second value or the second duration is the fourth value, including: the first comparator compares the preset time threshold with a third duration under the condition that the first duration is a second value or the second duration is a fourth value; the monitoring circuit sends a one-time reset indication signal when the preset time threshold is not greater than the third duration, and the monitoring circuit comprises: the first comparator sends a trigger signal once under the condition that the preset time threshold is not more than the third duration; the resetter responds to the trigger signal once and sends the reset indication signal once.

In some embodiments, the adjustment circuit includes a storage circuit, a first timer, and a second timer, the storage circuit storing a first time parameter corresponding to the first duration and a second time parameter corresponding to the second duration; the adjusting circuit responds to the adjusting indication signal once, and the adjusting operation once comprises the following steps: the storage circuit responds to the adjustment indication signal once, and adjusts at least one of the first time parameter and the second time parameter so that the adjustment operation is executed once; the adjusting circuit responds to the reset indicating signal once, and the reset operation is executed once, and comprises the following steps: the storage circuit resets at least one of the first time parameter and the second time parameter in response to the reset indication signal once, so that the reset operation is performed once; the first timer starts to time in response to the pulse until the time is a first duration corresponding to a first time parameter currently stored by the storage circuit, and the second timer starts to time at the end moment of the first duration until the time is a second duration corresponding to a second time parameter currently stored by the storage circuit.

In some embodiments, the adjustment circuit includes a storage circuit, a first timer, and a second timer, the storage circuit storing a first time parameter corresponding to the first duration and a second time parameter corresponding to the second duration; the adjusting circuit responds to the adjusting indication signal once, and the adjusting operation once comprises the following steps: the storage circuit responds to the adjustment indication signal once, and adjusts at least one of the first time parameter and the second time parameter so that the adjustment operation is executed once; the first timer starts to time in response to the pulse until the time is a first duration corresponding to a first time parameter currently stored by the storage circuit, and the second timer starts to time at the end moment of the first duration until the time is a second duration corresponding to a second time parameter currently stored by the storage circuit.

In some embodiments, the pulse signal output circuit includes a sawtooth signal generator and an output sub-circuit; wherein the pulse signal output circuit outputting the pulse signal according to the output signal of the DC-DC converter includes: the sawtooth wave signal generator generates a sawtooth wave signal; the output sub-circuit outputs the pulse signal according to the output signal, the sawtooth wave signal and the reference signal.

In some embodiments, the output sub-circuit comprises an arithmetic circuit and a second comparator; wherein the outputting the pulse signal according to the output signal, the sawtooth wave signal and the reference signal by the output sub-circuit comprises: the arithmetic circuit outputs an intermediate signal according to one signal of the sawtooth wave signal and the reference signal and the output signal; the second comparator outputs the pulse signal according to the other one of the sawtooth wave signal and the reference signal and the intermediate signal.

According to still another aspect of the embodiments of the present disclosure, there is provided a DC-DC converter including: the control circuit for a DC-DC converter according to any one of the above embodiments; a first switch; and a second switch.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the DC-DC converter according to any of the above embodiments.

In the embodiment of the disclosure, whether the output power of the DC-DC converter is insufficient is judged by monitoring the pulse signal output by the pulse signal output circuit, and the maximum duty ratio of the operation of the DC-DC converter is increased under the condition of insufficient output power. Specifically, in the case where it is monitored that the pulse signal output by the pulse signal output circuit is at a preset level at a specific time, the monitoring circuit sends an adjustment instruction signal to the adjustment circuit once to increase the first duration and/or decrease the second duration. In this way, the maximum duty ratio of the operation of the DC-DC converter can be increased in time when the output power of the DC-DC converter is insufficient, so that the output voltage of the DC-DC converter can be increased, and the DC-DC converter can stably output the voltage. This improves the stability of the output voltage of the DC-DC converter.

The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic block diagram of a control circuit for a DC-DC converter according to some embodiments of the present disclosure;

FIG. 2 is a schematic block diagram of a control circuit for a DC-DC converter according to further embodiments of the present disclosure;

FIG. 3 is a timing diagram of signals according to some embodiments of the present disclosure;

FIG. 4 is a schematic block diagram of a control circuit for a DC-DC converter according to further embodiments of the present disclosure;

FIG. 5 is a timing diagram of signals according to further embodiments of the present disclosure;

FIG. 6 is a schematic diagram of a pulsed signal output circuit, according to some embodiments of the present disclosure;

FIG. 7A is a schematic diagram of a pulsed signal output circuit according to further embodiments of the present disclosure;

FIG. 7B is a schematic diagram of a pulsed signal output circuit according to further embodiments of the present disclosure;

fig. 8 is a flow diagram of a control method for a DC-DC converter according to some embodiments of the present disclosure;

fig. 9 is a flow chart schematic of a control method for a DC-DC converter according to further embodiments of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not necessarily drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be intervening components between the specific component and the first component or the second component. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without having an intervening component, or may be directly connected to the other components without having an intervening component.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

One control method of the above DC-DC converter is a variable frequency control method. In this manner, one of the two switches connected to the input terminal is controlled to be turned on for a predetermined period of time and turned off for at least another predetermined period of time after the end. The actual duration of the disconnection can be adjusted as desired. And under the condition that the actual time length of the disconnection is equal to the preset time length of the disconnection, the DC-DC converter works at the preset maximum duty ratio.

However, the inventors have noted that in some cases, the output voltage of the DC-DC converter is unstable. By analysis, the inventors found that in these cases, the load of the DC-DC converter is excessive, that is, the output power of the DC-DC converter is insufficient. Even if the DC-DC converter operates in a state of maximum duty ratio, the output voltage of the DC-DC converter is still significantly reduced. This causes the output voltage of the DC-DC converter to be unstable.

In view of this, the present disclosure proposes a solution that can improve the stability of the output voltage of the DC-DC converter.

Fig. 1 is a schematic diagram of a control circuit for a DC-DC converter according to some embodiments of the present disclosure.

As shown in fig. 1, a control circuit 100 for a DC-DC converter includes a Pulse signal output circuit 110, a Pulse Width Modulation (PWM) controller 120, an adjustment circuit 130, and a monitoring circuit 140.

For convenience of explanation, a first switch 210 and a second switch 220 connected in series included in the DC-DC converter are also illustrated in fig. 1. The first switch 210 is connected between the input 201 of the DC-DC converter and the second switch 220. The second switch 220 is connected between the first switch 210 and the ground terminal 203. In some embodiments, the first switch 210 and the second switch 220 may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as N-type MOSFETs or P-type MOSFETs.

The first switch 210 and the second switch 220 are respectively connected to the PWM controller 120, so that the PWM controller 120 controls the first switch 210 and the second switch 220 to be respectively turned on or off. Specifically, the PWM controller 120 is configured to control the second switch 220 to be turned off when the first switch 210 is turned on, and to be turned on when the first switch 210 is turned off.

The PWM controller 120 may control the first switch 210 to be turned on or off according to the pulse signal output from the pulse signal output circuit 110. This will be explained below.

Referring to fig. 1, the pulse signal output circuit 110 is connected to an output terminal 202 of the DC-DC converter. The pulse signal output circuit 110 is configured to output a pulse signal having a pulse of a preset level according to an output signal of the DC-DC converter. For example, the preset level is a high level. For another example, the preset level is a low level. In some embodiments, the pulse signal output circuit 110 is configured to output a pulse signal according to the sawtooth wave signal, the reference signal, and an output signal of the DC-DC converter. This will be described later in connection with some embodiments.

The PWM controller 120 is connected to the pulse signal output circuit 110. The PWM controller 120 is configured to control the first switch 210 to be turned on for a first duration and turned off for at least a second duration after the first duration in response to a pulse in the pulse signal output by the pulse signal output circuit 110. In other words, the first duration is the length of time that the first switch 210 is turned on in one cycle; the second duration is the Minimum length of time (i.e., Minimum Off-time) that the first switch 210 is open within one period.

Referring to fig. 1, the monitoring circuit 140 is connected to the pulse signal output circuit 110. The monitoring circuit 140 is configured to transmit the one-time adjustment indication signal in a case where it is monitored that the pulse signal is at a preset level at a specific time.

Here, the specific time is any one of the start time to the end time of the second duration.

If the monitoring circuit 140 monitors that the pulse signal is at a preset level at a specific time, it indicates that the pulse signal output circuit 110 is continuously outputting a pulse. In this case, the monitoring circuit 140 transmits a primary adjustment instruction signal to the adjustment circuit 130.

As some implementations, the monitoring circuit 140 may sample the pulse signal at a particular time to obtain a sampled signal. Then, in a case where the sampling signal is at a preset level, an adjustment instruction signal is transmitted once.

The adjustment circuit 130 is configured to perform an adjustment operation in response to an adjustment instruction signal. Here, the adjusting operation includes at least one of increasing the first duration and decreasing the second duration.

For example, each adjustment operation is to decrease the current second duration by 20 μ s. The second duration is 200 mus before the first adjustment operation is performed. After receiving the adjustment indication signal once, an adjustment operation is performed so that the second duration is reduced from the current 200 μ s to 180 μ s. Thereafter, if the adjustment instruction signal is received once more, the adjustment operation is performed once more so that the second duration is reduced from the current 180 μ s to 160 μ s. The subsequent cases can be analogized, and are not detailed here. It is understood that 200 mus, 180 mus and 160 mus are all second durations.

It should be understood that after the adjusting circuit 130 performs the adjusting operation, the PWM controller 120 subsequently controls the first switch 210 to be on according to the current first duration, and controls the first switch 210 to be off according to the current second duration.

In the above embodiment, whether the output power of the DC-DC converter is insufficient is determined by monitoring the pulse signal output from the pulse signal output circuit 110, and the maximum duty ratio at which the DC-DC converter operates is increased in the case where the output power is insufficient. Specifically, in a case where it is monitored that the pulse signal output from the pulse signal output circuit 110 is at a preset level at a specific time, the monitoring circuit 140 transmits an adjustment instruction signal to the adjustment circuit 130 once to increase the first duration and/or decrease the second duration. In this way, the maximum duty ratio of the operation of the DC-DC converter can be increased in time when the output power of the DC-DC converter is insufficient, so that the output voltage of the DC-DC converter can be increased, and the DC-DC converter can stably output the voltage. This improves the stability of the output voltage of the DC-DC converter.

In some embodiments, referring to fig. 1, the DC-DC converter further comprises an energy storage element 230. The energy storage element 230 may be, for example, an inductor. For one of the first switch 210 and the second switch 220, the other of the first switch 210 and the second switch 220 and the energy storage element 230 are connected in parallel, and the energy storage element 230 is connected to the output 202 of the DC-DC converter. The energy storage element 230 may store energy when the first switch 210 is turned on and the second switch 220 is turned off, and release energy when the first switch 210 is turned off and the second switch 220 is turned on.

The first duration is set to 250 μ s and the second duration is set to 200 μ s. The pulse signal output circuit 110 outputs a pulse at the beginning of the operation of the DC-DC converter. The pulse will drive the PWM controller 120 to control the first switch 210 to conduct for 250 μ s, during which the energy storage element 230 stores energy and the output voltage of the DC-DC converter increases. Immediately afterwards, the PWM controller 120 controls the first switch 210 to be turned off for 200 μ s, during which the energy storage element 230 releases energy and the output voltage of the DC-DC converter decreases.

For example, the pulse signal output circuit 110 may operate the output signal of the DC-DC converter and the sawtooth wave signal to obtain an operation value, and output a pulse when the operation value is lower than a preset threshold value to drive the PWM controller 120 to control the first switch 210 to be turned on for 250 μ s, so that the output voltage of the DC-DC converter may be increased.

If the calculated value is lower than the preset threshold value after the first switch 210 is turned off for 200 μ s, this indicates that the DC-DC converter operates at a duty ratio not exceeding the current maximum duty ratio, so that the output voltage is stabilized within the preset range. In this case, the adjustment operation need not be performed. I.e. a first duration of 250 mus and a second duration of 200 mus.

However, if the calculated value is lower than the preset threshold value before the first switch 210 is turned off for 200 μ s, this means that the output voltage of the DC-DC converter cannot be stabilized within the preset range even if it is operated at the present maximum duty ratio. In this case, an adjustment operation needs to be performed. For example, the first duration is maintained at 250 μ s and the second duration is reduced to 180 μ s. This makes it possible to increase the output voltage of the DC-DC converter earlier, thereby stabilizing the output voltage of the DC-DC converter within the preset range.

The inventors have noted that, in case the output power of the DC-DC converter is sufficient, the output voltage of the DC-DC converter can be stabilized within the preset range after the first switch 210 is turned off for the second duration. This may result in the interval between the occurrence instants of two adjacent pulses in the pulse signal being greater than or equal to the second duration. However, in the case where the output power of the DC-DC converter is insufficient, the output voltage of the DC-DC converter cannot be stabilized within the preset range until the first switch 210 is turned off for the second duration. This causes the pulse signal output circuit 110 to continuously output one pulse. Accordingly, the present disclosure may determine whether the output power of the DC-DC converter is sufficient by monitoring the pulse signal output by the pulse signal output circuit 110 in the above-described manner.

Fig. 2 is a schematic block diagram of a control circuit for a DC-DC converter according to further embodiments of the present disclosure. Some implementations of the adjustment circuit 130 and the monitoring circuit 140 are described below in conjunction with fig. 2.

As shown in fig. 2, in some implementations, the adjustment circuit 130 includes a storage circuit 131, a first timer 132, and a second timer 133. In some implementations, the monitoring circuit 140 includes a sampling circuit 141. The direction of the respective signal flows is indicated in fig. 2 by arrows.

The sampling circuit 141 is configured to sample the pulse signal S at a specific timing _p Sampling is carried out to obtain a sampling signal S _s . In sampling signal S _s When the pulse signal output circuit 110 outputs a pulse at a predetermined level, the primary adjustment instruction signal S is transmitted to the storage circuit 131 _a . The sampling circuit 141 may be, for example, a flip-flop.

The storage circuit 131 is configured to store a first time parameter corresponding to the first duration and a second time parameter corresponding to the second duration. In response to a one-time adjustment indicating signal S from the monitoring circuit 140 _a The memory circuit 131 adjusts at least one of the first time parameter and the second time parameter so that one adjustment operation is performed. The storage circuit 131 is, for example, an accumulation register.

The first timer 132 is configured to respond to the pulse signal S _p Until the timed time is the first duration corresponding to the first time parameter currently stored in the memory circuit 131.

The second timer 133 is configured to start counting at the end time of the first duration until the counted time is a second duration corresponding to the second time parameter currently stored by the storage circuit 131. For example, the first timer 132 may send a signal S to the second timer 133 _T1 To trigger the second timer 133 to start counting when the first timer 132 stops counting (i.e., the termination time of the first duration). It should be understood that the PWM controller 120 is at the end of the first durationThe first switch 210 starts to be controlled to be turned off.

The first timer 132 and the second timer 133 are, for example, multi-step timers, with different steps corresponding to different values of duration.

The following description will be given taking, as an example, an initial value of the first duration time as 250 μ s, an initial value of the second duration time as 200 μ s, and the first time parameter and the second time parameter as the gear. The memory circuit 131 starts storing the shift position corresponding to 250 μ s and the shift position corresponding to 200 μ s. Assuming that the adjusting operation is to reduce the current second duration by 20 μ s, the storage circuit 131 may adjust the second time parameter corresponding to the second duration, for example, the gear corresponding to 200 μ s to the gear corresponding to 180 μ s, after receiving one adjustment indication signal.

When the first timer 132 starts to count, the storage circuit 131 may send a signal S to the first timer 132 _g1 Signal S _g1 Information indicating the current gear is carried such that the time counted by the first timer 132 is the first duration corresponding to the current gear. The first timer 132 may send a signal S to the PWM controller 120 _T1 To trigger the PWM controller 120 to start controlling the first switch 210 to be turned on when the first timer 132 starts to count, and to start controlling the first switch 210 to be turned off when the first timer 132 stops counting. For example, the PWM controller 120 may send an and signal S to the first switch 210 _T1 The same or complementary control signals to control the turning on and off of the first switch 210.

Similarly, when the second timer 133 starts to count, the storage circuit 131 may send a signal S to the second timer 133 _g2 Signal S _g2 Information indicating the current gear is also carried such that the time counted by the second timer 133 is the second duration corresponding to the current gear. The second timer 133 may send a signal S to the first timer 132 _T2 The first timer 132 is instructed to start counting when the second timer 133 stops counting and receives a pulse. The second timer 133 may also send a signal S to the sampling circuit 141 _T2 To trigger the sampling circuit141 at a specific time _p Sampling is performed. In some embodiments, the second timer 133 may also send a signal S to the PWM controller 120 _T2 。

The following description will be made with reference to the timing chart of each signal shown in fig. 3. Fig. 3 is a timing diagram of signals according to some embodiments of the present disclosure. In the timing chart, the horizontal axis represents time, and the vertical axis represents voltage.

As shown in fig. 3, the pulse signal output circuit 110 outputs a pulse signal S _p . In response to the pulse, the first timer 132 starts counting to a first duration (i.e., T1), during which the PWM controller 120 controls the first switch 210 to be turned on and the second switch 220 to be turned off. When the first timer 132 stops counting, the second timer 133 starts counting to a second duration (i.e., T2, T2', and T2 "), during which the PWM controller 120 controls the first switch 210 to be turned off and the second switch 220 to be turned on until the first timer 132 starts counting again in response to the pulse. During the second duration (i.e., signal S shown in FIG. 3) _T2 Duration at low level) of the first and second signals _s (e.g., t) _s1 ～t _s6 ) Sampling circuit 141 for pulse signal S _p Sampling to obtain a sampled signal S _s . If the signal S is sampled _s At the preset level that the pulse has, the sampling circuit 141 sends a one-time adjustment instruction signal to the memory circuit 131.

Hereinafter, for convenience of explanation, the signal S will be described _T1 A duration at high level and signal S after the duration _T1 One duration at the low level is referred to as one period.

As shown in fig. 3, the pulse signal S is generated in the first period and the second period _p The time interval between two adjacent pulses is short (i.e., the duration of the first switch 210 being turned off is short), which indicates that the power consumed by the load of the DC-DC converter is gradually increased, but the output power of the DC-DC converter is still sufficient. At this time, the output voltage of the DC-DC converter is still stabilized within the preset range, and the pulse signal S _p A brief pulse occurs. In this situationIn the case, no adjustment operation needs to be performed. In particular, at a first instant t _s1 And a second time t _s2 Sampling signal S obtained by sampling circuit 141 _s Not at the preset level that the pulse has. In this case, the adjusting circuit 130 is in the first mode, i.e., no adjusting operation is performed. In other words, the PWM controller 120 controls the first switch 210 according to the initial first duration T1 and the initial second duration T2.

In the third period, the power consumed by the load of the DC-DC converter continues to increase, and the output power of the DC-DC converter is insufficient. This results in the output voltage of the DC-DC converter not being stabilized within a preset range. At this time, the duration of time that the first switch 210 is actually turned off (i.e., the signal S) _T1 Duration at low level) is equal to the second duration (i.e., signal S) _T2 Duration at low level), the pulse signal S _p A continuous pulse occurs. In this case, an adjustment operation needs to be performed. In particular, at a third instant t _s3 Sampling signal S obtained by sampling circuit 141 _s At a preset level that the pulse has (i.e., high level as shown in fig. 3). In this case, the sampling circuit 141 transmits the adjustment instruction signal once to cause the adjustment circuit 130 to be in the second mode, that is, the adjustment operation is performed. The adjustment operation to reduce the second duration is schematically shown in fig. 3. After the first adjustment operation is performed, the second duration is reduced from T2 to T2'. At this time, the PWM controller 120 controls the first switch 210 according to the initial first duration T1 and the adjusted second duration T2'.

Similarly, in the fourth cycle, although the second duration has been reduced to T2', the output voltage of the DC-DC converter still cannot be stabilized within the preset range. At this time, the pulse signal S _p A continuous pulse still occurs and the adjustment operation still needs to be performed. In particular, at a fourth instant t _s4 Sampling signal S obtained by sampling circuit 141 _s Still at the preset level (i.e., high as shown in fig. 3). In this case, the sampling circuit 141 sends the adjustment instruction signal once more so that the second duration time isFrom T2' to T2 ". At this time, the PWM controller 120 controls the first switch 210 according to the initial first duration T1 and the adjusted second duration T2 ″.

Thereafter, at a fifth time t _s5 And a sixth time t _s6 Sampling signal S obtained by sampling circuit 141 _s Not at the preset level that the pulse has (i.e., low level as shown in fig. 3). In this case, the adjusting circuit 130 does not need to continue to perform the adjusting operation to reduce the current second duration T2 ″. The PWM controller 120 may continue to control the first switch 210 for the initial first duration T1 and the adjusted second duration T2 ".

The control circuit 100 is further described below in connection with some embodiments.

In some embodiments, the specific time is set to a time that is not a termination time of the second duration (e.g., the start time t of the second duration schematically illustrated in fig. 3) _s3’ ). The pulse signal output circuit 110 may start to continuously output one pulse after the timing. The inventors have noted that in this case, the sampling circuit 141 is to be at the next particular time (e.g., time t schematically shown in fig. 3) _s4’ ) Can the sampling signal be sampled at a preset level.

In other embodiments, the particular time is the termination time of the second duration (i.e., signal S shown in FIG. 3) _T2 Rising edge of). In this way, the monitoring circuit 140 can send the adjustment indication signal to the adjustment circuit 130 more timely, so that the maximum duty ratio of the DC-DC converter can be increased more timely when the output power of the DC-DC converter is insufficient. This can make the voltage output by the DC-DC converter more quickly stabilize.

In some embodiments, the increase in the first duration is the same and/or the decrease in the second duration is the same in any two adjustment operations. Thus, the simplicity of circuit design can be improved.

In some embodiments, the adjusting operation is to increase the first duration or decrease the second duration. Thus, the simplicity of circuit design can be improved.

In some embodiments, the adjusting operates to decrease the second duration. Since the maximum duty cycle at which the DC-DC converter operates is equal to the first duration and the sum of the first duration and the second duration. Therefore, in the case where the amount of change is the same, decreasing the second duration may increase the maximum duty ratio when the DC-DC converter operates more.

Thus, the maximum duty ratio of the DC-DC converter after one adjustment operation can be greatly increased while the simplicity of circuit design is improved, so that the voltage output by the DC-DC converter is more quickly stabilized.

As described above, after the adjusting circuit 130 performs the adjusting operation, the maximum duty ratio at which the DC-DC converter operates is increased. However, it is desirable to be able to reduce the maximum duty cycle of the DC-DC converter to a more suitable maximum duty cycle that was originally designed when the output power of the DC-DC converter is sufficient (e.g., the input power of the DC-DC converter is increased, or the power that the load of the DC-DC converter needs to consume is reduced). In view of this, the present disclosure also provides the following embodiments.

In some embodiments, the first duration is a first value and a second value before and after the first adjustment operation is performed. The second duration is a third value and a fourth value before and after the first adjustment operation is performed, respectively.

It will be appreciated that the second value is greater than the first value and/or the fourth value is less than the third value. For example, in the case where each of the adjustment operations is to increase the first duration, the second value is greater than the first value, and the third value is equal to the fourth value. For another example, in the case where each of the adjustment operations is to decrease the second duration, the first value is equal to the second value, and the fourth value is smaller than the third value. For another example, in a case where each of the adjustment operations is to increase the first duration and decrease the second duration, the second value is larger than the first value, and the fourth value is smaller than the third value.

In other words, the first value refers to the initial value of the first duration in the first mode, and the third value refers to the initial value of the second duration in the first mode.

Still based on the above examples. In an example, the second duration is 200 μ s before the first adjustment operation is performed, i.e. 200 μ s is the third value. Thereafter, the second duration is reduced from 200 μ s to 180 μ s, and then from 180 μ s to 160 μ s. In this case, 180 μ s and 160 μ s are both the fourth value.

In these embodiments, the monitoring circuit 140 is further configured to compare the preset time threshold with a third duration for which the first switch 210 is actually open, in case the first duration is the second value or the second duration is the fourth value. Here, the preset time threshold is not less than the third value.

As some implementations, referring to fig. 1, the monitoring circuit 140 is further connected to the PWM controller 120 to compare the preset time threshold with the third duration of time that the first switch 210 is turned off according to the control signal sent by the PWM controller 120 to the first switch 210. As other implementations, the monitoring circuit 140 may be coupled to the first timer 132 to provide a signal S based on the signal S _T1 The preset time threshold is compared with the third duration.

In the case where the preset time threshold is not greater than the third duration, that is, in the case where the third duration in which the first switch 210 is actually turned off is greater than or equal to the preset time threshold, the monitoring circuit 140 transmits a one-time reset indication signal to the adjustment circuit 130.

It can be understood that if the interval between the occurrence moments of two adjacent pulses is gradually increased, so that the third duration of the actual opening of the first switch 210 is greater than or equal to the initial value of the originally designed second duration, this indicates that the output power of the DC-DC converter is sufficient. In this case, the monitoring circuit 140 transmits a one-time reset instruction signal.

The adjusting circuit 130 is further configured to perform a one-time reset operation in response to a one-time reset instruction signal. Here, the reset operation includes at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

It should be understood that the reset operation corresponds to the adjustment operation. For example, in the case where the adjustment operation is to increase the first duration, the reset operation is to decrease the first duration to a first value. For another example, in the case where the adjustment operation is to decrease the second duration, the reset operation is to increase the second duration to a third value. For another example, in the case where the adjusting operation is to increase the first duration and decrease the second duration, the resetting operation is to decrease the first duration to a first value and increase the second duration to a third value.

It is understood that the first adjustment operation refers to an adjustment operation corresponding to the first adjustment instruction signal being sent immediately after the DC-DC converter starts to operate, or an adjustment operation corresponding to the first adjustment instruction signal being sent after each reset operation.

In the above embodiment, the monitoring circuit 140 compares the preset time threshold with the third duration of time for which the first switch 210 is turned off in the case that the first duration is the second value or the second duration is the fourth value, so as to determine whether the output power of the DC-DC converter is sufficient. In case it is confirmed that the output power of the DC-DC converter is sufficient, the monitoring circuit 140 sends a one-time reset indication signal to the adjusting circuit 130 to decrease the first duration to the first value and/or to increase the second duration to the third value. In this way, the maximum duty cycle of the DC-DC converter can be reduced to a more suitable maximum duty cycle in time if the output power of the DC-DC converter is sufficient.

In some embodiments, the preset time threshold is greater than the third value and less than 1.5 times the third value. For example, the preset time threshold may be 1.2 times, 1.25 times, or 1.3 times the third value. Taking the third value of the first duration as 200 mus for example, the preset time threshold may be 240 mus, 250 mus, or 260 mus. In this way, it is possible to avoid a situation where the adjustment operation needs to be performed again because the output power of the DC-DC converter is short-term and insufficient after the reset operation is performed.

Further implementations of the monitoring circuit 140 are described below in conjunction with fig. 4.

Fig. 4 is a schematic diagram of a control circuit for a DC-DC converter according to still further embodiments of the present disclosure.

As shown in fig. 4, the monitoring circuit 140 includes a first comparator 142 and a resetter 143 in addition to the sampling circuit 141. The direction of the respective signal flows is indicated in fig. 4 by arrows.

The first comparator 142 is configured to compare the preset time threshold with a third duration for which the first switch 210 is actually turned off, in case the first duration is the second value or the second duration is the fourth value. In case that the preset time threshold is not greater than the third duration, the first comparator 142 transmits the trigger signal S to the resetter 143 once _t 。

The resetter 143 is configured to respond to a trigger signal S _t Sending a one-time reset indication signal S _r 。

For example, in sampling the signal S _s In the case where the pulse has a preset level, the sampling circuit 141 also sends an indication signal S to the first comparator 142 _i So that the first comparator 142 knows that the first duration or the second duration has been adjusted. In this case, the first comparator 142 starts to compare the preset time threshold with the third duration. In case the preset time threshold is not greater than the third duration, the first comparator 142 sends a trigger signal S once _t And stops comparing the preset time threshold with the third duration until receiving the indication signal S from the sampling circuit 141 again _i . The resetter 143 upon receiving a trigger signal S _t Thereafter, for example, the one-time reset instruction signal S is sent to the memory circuit 131 _r 。

In these embodiments, the storage circuit 131 is further configured to respond to a one-time reset indication signal S _r And resetting at least one of the first time parameter and the second time parameter so that one reset operation is performed.

The following description will be made with reference to the timing chart of each signal shown in fig. 5. FIG. 5 is a timing diagram of signals according to further embodiments of the present disclosure.

As shown in fig. 5, at a third time t _s3 After sending the adjustment indication signal once, the first comparator 142 starts to compare the preset time threshold with the third duration (i.e., T3, T3' and T3) for which the first switch 210 is turned off"). In the event that it is confirmed that the preset time threshold is not greater than the third duration (e.g., 260 μ S), the first comparator 142 sends a trigger signal S _t To trigger the resetter 143 to send a one-time reset indication signal S _r . Then, the storage circuit 131 adjusts the second time parameter to a second time parameter corresponding to the second duration T2 (e.g., 200 μ s) of the initial value, i.e., returns to the first mode in which the adjustment operation is not performed. At the same time, the sampling circuit 141 is still at each particular time (e.g., t) _s7 ～t _s9 ) For pulse signal S _p Sampling is performed. Subsequent processes are similar and will not be described in detail here.

The pulse signal output circuit 110 is explained below with reference to fig. 6, 7A, and 7B.

Fig. 6 is a schematic diagram of a structure of a pulse signal output circuit according to some embodiments of the present disclosure.

As shown in fig. 6, the pulse signal output circuit 110 includes a sawtooth signal generator 111 and an output sub-circuit 112. The sawtooth signal generator 111 is configured to generate a sawtooth signal S _w . The output sub-circuit 112 is configured to output a signal V according to the DC-DC converter _o Sawtooth wave signal S _w And a reference signal R to output a pulse signal S _p 。

As some implementations, the sawtooth signal generator 111 may be connected to the node 204 (see FIG. 1) to generate the sawtooth signal S _w . As other implementations, the sawtooth signal generator 111 may be connected with the PWM controller 120 to generate the sawtooth signal S _w 。

FIG. 7A is a schematic diagram of a pulsed signal output circuit according to further embodiments of the present disclosure; fig. 7B is a schematic diagram of a pulsed signal output circuit, according to still further embodiments of the present disclosure.

As shown in fig. 7A and 7B, the output sub-circuit 112 includes an arithmetic circuit 1121 and a second comparator 1122.

The operation circuit 1121 is configured to operate according to a sawtooth wave signal S _w And one of the reference signals R, and the output signal V of the DC-DC converter _o Output intermediate signal S _m . The second comparator 1122 is configured to output a sawtooth wave signal S _w And the other of the reference signal R, and the intermediate signal S _m Output pulse signal S _p 。

In some embodiments, referring to fig. 7A, the operational circuitry 1121 is a comparator (i.e., a third comparator). In this case, the arithmetic circuit 1121 is based on the reference signal R and the intermediate signal S _m Output pulse signal S _p 。

In other embodiments, referring to fig. 7B, the arithmetic circuit 1121 is a multiplier. In this case, the arithmetic circuit 1121 outputs the sawtooth wave signal S _w And intermediate signal S _m Output pulse signal S _p 。

It should be understood that the control circuit 100 may be implemented as a digital circuit in the various implementations described above.

Fig. 8 is a flow diagram of a control method for a DC-DC converter according to some embodiments of the present disclosure.

As shown in fig. 8, the control method for the DC-DC converter includes steps 802 to 808.

In step 802, the pulse signal output circuit 110 outputs a pulse signal according to the output signal of the DC-DC converter. The output pulse signal has pulses of a preset level.

In some embodiments, the pulse signal output circuit 110 includes a sawtooth signal generator 111 and an output sub-circuit 112. The sawtooth signal generator 111 may generate a sawtooth signal. The output sub-circuit 112 may output a pulse signal according to the sawtooth wave signal, the reference signal, and the output signal of the DC-DC converter.

As some implementations, the output sub-circuit 112 includes an arithmetic circuit 1121 and a second comparator 1122. In these implementations, the arithmetic circuit 1121 outputs an intermediate signal from one of the sawtooth wave signal and the reference signal and the output signal of the DC-DC converter. The second comparator 1122 may output a pulse signal according to the other one of the sawtooth wave signal and the reference signal, and the intermediate signal.

In some embodiments, the operational circuitry 1121 is a comparator and one signal is a reference signal. In other embodiments, the arithmetic circuit 1121 is a multiplier and one of the signals is a sawtooth signal.

At step 804, the PWM controller 120 controls the first switch 210 to be turned on for a first duration and to be turned off for at least a second duration after the first duration in response to a pulse in the pulse signal. Here, the second switch 220 is controlled by the PWM controller 120 to be turned off when the first switch 210 is turned on, and to be turned on when the first switch 210 is turned off.

In step 806, the monitoring circuit 140 transmits a primary adjustment indication signal when it is monitored that the pulse signal is at a preset level at a specific time. Here, the specific time is any one of the start time to the end time of the second duration.

As some implementations, the monitoring circuit 140 (e.g., the sampling circuit 141 in the monitoring circuit 140) samples the pulse signal at a particular time to obtain a sampled signal. Then, the monitoring circuit 140 transmits a one-time adjustment instruction signal in a case where the sampling signal is at a preset level.

In step 808, the adjusting circuit 130 performs an adjusting operation in response to the one-time adjustment instruction signal. Here, the adjusting operation includes at least one of increasing the first duration and decreasing the second duration.

For example, the adjusting circuit 130 includes a storage circuit 131, and the storage circuit 131 stores a first time parameter corresponding to a first duration and stores a second time parameter corresponding to a second duration. The storage circuit 131 may adjust at least one of the first time parameter and the second time parameter in response to the one-time adjustment instruction signal so that one-time adjustment operation is performed.

The adjusting circuit 130 may further include a first timer 132 and a second timer 133. The first timer 132 may start timing in response to the pulse until the timed time is a first duration corresponding to a first time parameter currently stored by the storage circuit 131. The second timer 133 may start counting at the end time of the first duration until the counted time is the second duration corresponding to the second time parameter currently stored in the storage circuit 131.

The first timer 132 may send a timing condition to the PWM controller 120, so that the PWM controller 120 controls the first switch 210 and the second switch 220 according to a duration corresponding to the time parameter currently stored in the storage circuit 131.

In the above embodiment, in the case where it is monitored that the pulse signal output from the pulse signal output circuit 110 is at the preset level at a specific time, the monitoring circuit 140 sends the adjustment instruction signal to the adjustment circuit 130 once to increase the first duration and/or decrease the second duration. In this way, the maximum duty ratio of the DC-DC converter during operation can be increased in time when the output power of the DC-DC converter is insufficient, so that the output voltage of the DC-DC converter can be increased, and the DC-DC converter can stably output the voltage. This improves the stability of the output voltage of the DC-DC converter.

As shown in fig. 9, the control method for the DC-DC converter includes steps 902 to 906 in addition to steps 802 to 808.

In step 902, the monitoring circuit 140 compares the preset time threshold with a third duration for which the first switch 210 is turned off, in case the first duration is the second value or the second duration is the fourth value. Here, the preset time threshold is not less than the third value.

In step 904, the monitoring circuit 140 sends a reset indication signal when the preset time threshold is not greater than the third duration.

As some implementations, the first comparator 142 in the monitoring circuit 140 compares the preset time threshold with the third duration when the first duration is the second value or the second duration is the fourth value. In the case where the preset time threshold is not greater than the third duration, the first comparator 142 transmits a trigger signal once to the resetter 143 in the monitoring circuit 140. The resetter 143 may transmit a reset indication signal in response to a trigger signal.

In step 906, the adjusting circuit 130 performs a reset operation in response to a reset indication signal. Here, the reset operation includes at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

For example, the memory circuit 131 may reset at least one of the first time parameter and the second time parameter in response to a one-time reset instruction signal, so that a one-time reset operation is performed.

The embodiment of the disclosure also provides a DC-DC converter. Referring to fig. 1, 2 and 4, the DC-DC converter includes the control circuit 100 for the DC-DC converter of any one of the above embodiments, the first switch 210, and the second switch 220.

An embodiment of the present disclosure also provides an electronic device including the DC-DC converter of any one of the above embodiments.

The electronic device may be, for example, a mobile phone, a notebook computer, an electric vehicle, or the like.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. As for the method, DC-DC converter and electronic device embodiments, since they substantially correspond to the control circuit embodiments for the DC-DC converter, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the control circuit embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a DC-DC converter, the DC-DC converter comprising a first switch and a second switch connected in series, the first switch being connected between an input of the DC-DC converter and the second switch, the second switch being connected between the first switch and ground, the control circuit comprising:

a pulse signal output circuit configured to output a pulse signal having a pulse of a preset level according to an output signal of the DC-DC converter;

a Pulse Width Modulation (PWM) controller configured to control the first switch to be on for a first duration and to be off for at least a second duration after the first duration in response to the pulse; controlling the second switch to be switched off when the first switch is switched on and to be switched on when the first switch is switched off;

a monitoring circuit configured to transmit a one-time adjustment indication signal when the pulse signal is monitored to be at the preset level at a specific time, wherein the specific time is any one of a start time to an end time of a second duration; and

an adjustment circuit configured to perform an adjustment operation in response to the adjustment indication signal once, the adjustment operation including at least one of increasing a first duration and decreasing a second duration.

2. The control circuit of claim 1, wherein the particular time is an end time of the second duration.

3. The control circuit of claim 1, wherein the monitoring circuit is configured to sample the pulse signal at the particular time to obtain a sampled signal; and under the condition that the sampling signal is at the preset level, sending the adjustment indicating signal once.

4. The control circuit of claim 3, wherein the first duration is a first value and a second value before and after the first adjustment operation is performed, and the second duration is a third value and a fourth value before and after the first adjustment operation is performed, wherein the second value is greater than the first value and/or the fourth value is less than the third value;

the monitoring circuit is further configured to compare a preset time threshold with a third duration of time for which the first switch is turned off, in a case where the first duration is a second value or the second duration is a fourth value, wherein the preset time threshold is not less than the third value; sending a one-time reset indication signal under the condition that the preset time threshold is not more than the third duration;

the adjustment circuit is further configured to perform a reset operation in response to the reset indication signal once, the reset operation including at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

5. The control circuit of claim 4, wherein the monitoring circuit comprises:

a sampling circuit configured to sample the pulse signal at the specific time to obtain the sampling signal; under the condition that the sampling signal is at the preset level, the adjustment indicating signal is sent once;

a first comparator configured to compare the preset time threshold with a third duration in a case where the first duration is the second value or the second duration is the fourth value; sending a trigger signal once under the condition that the preset time threshold is not more than the third duration;

a resetter configured to transmit the reset indication signal once in response to the trigger signal once.

6. The control circuit of claim 4, wherein the adjustment circuit comprises:

a storage circuit configured to store a first time parameter corresponding to a first duration and a second time parameter corresponding to a second duration; adjusting at least one of a first time parameter and a second time parameter in response to the adjustment indication signal at one time, so that the adjustment operation is performed at one time; resetting at least one of a first time parameter and a second time parameter in response to the reset indication signal at one time, so that the reset operation is performed at one time;

a first timer configured to start timing in response to the pulse until the timing is a first duration corresponding to a first time parameter currently stored by the storage circuit;

and the second timer is configured to start timing at the termination moment of the first duration until the timed time is a second duration corresponding to the second time parameter currently stored by the storage circuit.

7. The control circuit of claim 4, wherein the preset time threshold is greater than the third value and less than 1.5 times the third value.

8. The control circuit of claim 1, wherein the adjustment circuit comprises:

a storage circuit configured to store a first time parameter corresponding to a first duration and a second time parameter corresponding to a second duration; adjusting at least one of a first time parameter and a second time parameter in response to the adjustment indication signal at one time, so that the adjustment operation is performed at one time;

9. The control circuit according to any one of claims 1 to 8, wherein the pulse signal output circuit includes:

a sawtooth wave signal generator configured to generate a sawtooth wave signal; and

an output sub-circuit configured to output the pulse signal according to the output signal, the sawtooth wave signal, and a reference signal.

10. The control circuit of claim 9, wherein the output sub-circuit comprises:

an arithmetic circuit configured to output an intermediate signal according to one of the sawtooth wave signal and the reference signal and the output signal; and

a second comparator configured to output the pulse signal according to the other one of the sawtooth wave signal and the reference signal, and the intermediate signal.

11. The control circuit of claim 10, wherein the operational circuit is a third comparator and the one signal is the reference signal.

12. The control circuit of claim 10, wherein the arithmetic circuit is a multiplier and the one signal is the sawtooth signal.

13. The control circuit of any of claims 1-8, wherein the adjusting operates to decrease the second duration.

14. The control circuit according to any of claims 1-8, wherein the first duration is increased by the same amount and/or the second duration is decreased by the same amount in any two adjustment operations.

15. A control method for a DC-DC converter including a first switch and a second switch connected in series, the first switch being connected between an input terminal of the DC-DC converter and the second switch, the second switch being connected between the first switch and a ground terminal, the control method comprising:

the pulse signal output circuit outputs a pulse signal according to an output signal of the DC-DC converter, wherein the pulse signal has a pulse with a preset level;

a Pulse Width Modulation (PWM) controller responds to the pulse and controls the first switch to be switched on for a first duration and switched off at least for a second duration after the first duration, wherein the second switch is controlled by the PWM controller to be switched off when the first switch is switched on and switched on when the first switch is switched off;

the monitoring circuit sends a primary adjustment indicating signal under the condition that the pulse signal is monitored to be at the preset level at a specific moment, wherein the specific moment is any one moment from the starting moment to the ending moment of the second duration;

the adjustment circuit performs an adjustment operation in response to the adjustment indication signal once, the adjustment operation including at least one of increasing the first duration and decreasing the second duration.

16. The control method according to claim 15, wherein the specific timing is an end timing of the second duration.

17. The control method of claim 15, wherein the monitoring circuit, in a case where it is monitored that the pulse signal is at the preset level at a specific time, transmitting an adjustment indication signal once comprises:

the monitoring circuit samples the pulse signal at the specific moment to obtain a sampling signal;

and the monitoring circuit sends the adjustment indicating signal once under the condition that the sampling signal is at the preset level.

18. The control method according to claim 17, wherein the first duration is a first value and a second value before and after the first adjustment operation is performed, and the second duration is a third value and a fourth value before and after the first adjustment operation is performed, wherein the second value is greater than the first value and/or the fourth value is less than the third value;

the control method further comprises the following steps:

the monitoring circuit compares a preset time threshold with a third duration of disconnection of the first switch under the condition that the first duration is a second value or the second duration is a fourth value, wherein the preset time threshold is not less than the third value;

the monitoring circuit sends a one-time reset indicating signal under the condition that the preset time threshold is not more than the third duration;

the adjustment circuit performs a reset operation in response to the reset indication signal once, the reset operation including at least one of decreasing the first duration to a first value and increasing the second duration to a third value.

19. The control method according to claim 18, wherein the monitoring circuit includes a sampling circuit, a first comparator, and a resetter;

wherein, the sending of the one-time adjustment indication signal by the monitoring circuit when monitoring that the pulse signal is at the preset level at a specific time comprises:

the sampling circuit samples the pulse signal at the specific moment to obtain the sampling signal;

the sampling circuit sends the adjustment indicating signal once under the condition that the sampling signal is at the preset level;

the monitoring circuit compares the preset time threshold with a third duration for which the first switch is open, in the case where the first duration is the second value or the second duration is the fourth value, including:

the first comparator compares the preset time threshold with a third duration under the condition that the first duration is a second value or the second duration is a fourth value;

the monitoring circuit sends a one-time reset indication signal when the preset time threshold is not greater than the third duration, and the monitoring circuit comprises:

the first comparator sends a trigger signal once under the condition that the preset time threshold is not more than the third duration;

the resetter responds to the trigger signal once and sends the reset indication signal once.

20. The control method of claim 18, wherein the adjustment circuit includes a storage circuit, a first timer, and a second timer, the storage circuit storing a first time parameter corresponding to the first duration and a second time parameter corresponding to the second duration;

the adjusting circuit responds to the adjusting indication signal once, and the adjusting operation once comprises the following steps:

the storage circuit responds to the adjustment indication signal once, and adjusts at least one of the first time parameter and the second time parameter so that the adjustment operation is executed once;

the adjusting circuit responds to the reset indicating signal once, and the reset operation is executed once, and comprises the following steps:

the storage circuit resets at least one of the first time parameter and the second time parameter in response to the reset indication signal once, so that the reset operation is performed once;

the first timer starts to time in response to the pulse until the time is a first duration corresponding to a first time parameter currently stored by the storage circuit, and the second timer starts to time at the end of the first duration until the time is a second duration corresponding to a second time parameter currently stored by the storage circuit.

21. The control method according to claim 18, wherein the preset time threshold is greater than the third value and less than 1.5 times the third value.

22. The control method of claim 15, wherein the adjustment circuit includes a storage circuit, a first timer, and a second timer, the storage circuit storing a first time parameter corresponding to the first duration and a second time parameter corresponding to the second duration;

the first timer starts to time in response to the pulse until the time is a first duration corresponding to a first time parameter currently stored by the storage circuit, and the second timer starts to time at the end moment of the first duration until the time is a second duration corresponding to a second time parameter currently stored by the storage circuit.

23. The control method according to any one of claims 15 to 22, wherein the pulse signal output circuit includes a sawtooth wave signal generator and an output sub-circuit;

wherein the pulse signal output circuit outputting the pulse signal according to the output signal of the DC-DC converter includes:

the sawtooth wave signal generator generates a sawtooth wave signal;

the output sub-circuit outputs the pulse signal according to the output signal, the sawtooth wave signal and the reference signal.

24. The control method of claim 23, wherein the output sub-circuit comprises an arithmetic circuit and a second comparator;

wherein the outputting the pulse signal according to the output signal, the sawtooth wave signal and the reference signal by the output sub-circuit comprises:

the arithmetic circuit outputs an intermediate signal according to one signal of the sawtooth wave signal and the reference signal and the output signal;

the second comparator outputs the pulse signal according to the other one of the sawtooth wave signal and the reference signal and the intermediate signal.

25. The control method according to claim 24, wherein the arithmetic circuit is a third comparator, and the one signal is the reference signal.

26. The control method according to claim 24, wherein the arithmetic circuit is a multiplier, and the one signal is the sawtooth signal.

27. A control method according to any one of claims 15 to 22, wherein the adjustment operation is a reduction of the second duration.

28. A control method according to any one of claims 15 to 22, wherein the increase in the first duration is the same and/or the decrease in the second duration is the same in any two adjustment operations.

29. A DC-DC converter comprising:

a control circuit for a DC-DC converter as claimed in any one of claims 1 to 14;

a first switch; and

a second switch.

30. An electronic device, comprising:

the DC-DC converter of claim 29.