CN114242860A - LED chip and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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Abstract
The invention discloses an LED chip and a preparation method thereof, wherein the preparation method of the LED chip comprises the following steps: providing a substrate; providing a substrate; forming an epitaxial structure and an annealing layer; the epitaxial structure is positioned on the upper surface of the substrate, the annealing layer is positioned on the upper surface of the epitaxial structure, and the annealing layer is exposed out of the epitaxial structure; the first electrode is formed on the upper surface of the annealing layer and the exposed epitaxial structure, electrons are injected into the epitaxial structure by the annealing layer during annealing treatment, so that the hole concentration in the epitaxial structure is improved, the uneven distribution of the electrons and the holes is improved, the problem that the electrons overflow and scatter into the epitaxial structure due to high electron concentration and fast migration is avoided, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to an LED chip and a preparation method thereof.
Background
The GaN-based light emitting diode LED is a semiconductor light emitting device, has the advantages of long service life, low energy consumption, small volume, high reliability and the like, becomes the most promising illumination light source at present, and is an important trend of a pilot illumination technology; however, the problems of low luminous intensity and low efficiency still exist, and further improvement of the luminous intensity and the luminous efficiency of the LED is the goal of development of LED lighting technology.
The traditional GaN-based LED chip has the advantages that the mobility of electrons is faster than that of holes, the concentration of free electrons is higher than that of the holes, the p-type layer positioned on the top layer of the chip is doped, the high hole concentration is difficult to obtain due to the passivation effect of hydrogen atoms, the electrons and holes in a multi-quantum well light-emitting layer (MQW) are easily distributed unevenly, the holes are concentrated in the MQW layer close to the p-type layer, the holes are gradually attenuated towards the n-type direction, the recombination of the electrons and the holes is not facilitated, and the light-emitting efficiency of the LED chip is reduced.
Disclosure of Invention
In view of the above, it is necessary to provide an LED chip and a method for manufacturing the LED chip, in which an annealing layer is formed on an epitaxial structure, and during an annealing process, the annealing layer injects electrons into the epitaxial structure to increase a hole concentration in the epitaxial structure.
In order to solve the above technical problem, a first aspect of the present application provides a method for manufacturing an LED chip, including:
providing a substrate;
forming an epitaxial structure and an annealing layer, wherein the epitaxial structure is positioned on the upper surface of the substrate, the annealing layer is positioned on the upper surface of the epitaxial structure, and the annealing layer is exposed out of the epitaxial structure; injecting electrons into the epitaxial structure during annealing treatment of the annealing layer so as to improve the concentration of holes in the epitaxial structure;
and forming a first electrode on the upper surface of the annealing layer and the exposed epitaxial structure.
In the preparation method of the LED chip provided in the above embodiment, the substrate, the epitaxial structure, the annealing layer, and the first electrode are sequentially disposed from bottom to top, and the first electrode is located on the upper surface of the annealing layer and the exposed epitaxial structure; annealing treatment is carried out on the formed structure, so that electrons are injected into the epitaxial structure through the annealing layer, the hole concentration in the epitaxial structure is improved, the uneven distribution of the electrons and the holes is improved, the problem that the electrons overflow and scatter to the epitaxial structure due to high electron concentration and fast migration is avoided, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
In one embodiment, after forming the first electrode on the upper surface of the annealed layer and the exposed epitaxial structure, the method further includes:
applying a current to the first electrode and performing the annealing treatment on the resulting structure;
wherein the applied current is 1mA-40 mA; the temperature of the annealing treatment is 150-450 ℃, the time of the annealing treatment is 5-50 min, and the atmosphere of the annealing treatment comprises nitrogen atmosphere and/or oxygen atmosphere.
In one embodiment, the substrate comprises a substrate, a buffer layer, a non-doping layer and an N-type semiconductor layer which are sequentially stacked from bottom to top; the epitaxial structure and the annealing layer are formed, and the method comprises the following steps:
forming a luminescent material layer on the upper surface of the substrate;
forming a P-type nitride laminated material layer on the upper surface of the light-emitting material layer;
forming an annealing material layer on the upper surface of the P-type nitride laminated material layer;
sequentially etching and removing part of the annealing material layer, part of the P-type nitride laminated material layer and part of the light-emitting material layer to expose the N-type semiconductor layer and form a light-emitting layer, a P-type nitride laminated layer and an annealing layer which are sequentially overlapped from bottom to top, wherein the light-emitting layer and the P-type nitride laminated layer jointly form the epitaxial structure;
after the annealing layer is formed, the method further comprises the following steps: and forming a second electrode on the exposed upper surface of the N-type semiconductor layer.
In one embodiment, the forming a P-type nitride stack material layer on the upper surface of the light emitting material layer includes:
forming a first P-type nitride material layer on the upper surface of the light-emitting material layer;
forming a P-type nitride blocking material layer on the upper surface of the first P-type nitride material layer;
forming a non-doped nitride material layer on the upper surface of the P-type nitride barrier material layer;
forming a second P-type nitride material layer on the upper surface of the undoped nitride material layer;
and after etching the part of the P-type nitride laminated material layer, forming a first P-type nitride layer, a P-type nitride barrier layer, a non-doped nitride layer and a second P-type nitride layer which are sequentially laminated from bottom to top, wherein the first P-type nitride layer, the P-type nitride barrier layer, the non-doped nitride layer and the second P-type nitride layer jointly form the P-type nitride laminated layer.
In one embodiment, the second P-type nitride layer has a magnesium-hydrogen complex therein; and the annealing layer injects electrons into the second P-type nitride layer, and the electrons capture magnesium-hydrogen bonds to decompose to form hydrogen ions so as to improve the hole concentration in the second P-type nitride layer.
In one embodiment, after the forming the annealed layer, the method further includes:
and etching the annealing layer to form an opening in the annealing layer, wherein the opening exposes the upper surface of the epitaxial structure.
Wherein, the annealing layer includes N type nitride layer, it includes to form first electrode on the upper surface of annealing layer and the epitaxial structure that exposes:
and forming a first N-type electrode on the upper surface of the annealing layer, and forming a first P-type electrode in the opening, wherein the first P-type electrode and the first N-type electrode jointly form the first electrode.
A second aspect of the present application provides an LED chip, including:
a substrate;
the epitaxial structure is positioned on the upper surface of the substrate;
the annealing layer is positioned on the upper surface of the epitaxial structure and exposes out of the epitaxial structure; injecting electrons into the epitaxial structure during annealing treatment of the annealing layer so as to improve the concentration of holes in the epitaxial structure;
and the first electrode is positioned on the upper surface of the annealing layer and the exposed epitaxial structure.
In one embodiment, the epitaxial structure comprises a light-emitting layer and a P-type nitride lamination layer which are sequentially stacked from bottom to top; the P-type nitride lamination layer comprises a first P-type nitride layer, a P-type nitride barrier layer, a non-doped nitride layer and a second P-type nitride layer which are sequentially stacked from bottom to top.
In one embodiment, the second P-type nitride layer has a magnesium-hydrogen complex therein; and the annealing layer injects electrons into the second P-type nitride layer, and the electrons capture magnesium-hydrogen bonds to decompose to form hydrogen ions so as to improve the hole concentration in the second P-type nitride layer.
In one embodiment, the first electrode comprises a first N-type electrode and a first P-type electrode, and the first N-type electrode is positioned on the upper surface of the annealing layer; the annealing layer is internally provided with an opening which exposes the second insertion layer; the first P-type electrode is positioned in the opening;
the substrate comprises a substrate, a buffer layer, a non-doping layer and an N-type semiconductor layer which are sequentially stacked from bottom to top;
the LED chip further includes: and the second electrode is positioned on the upper surface of the N-type semiconductor layer.
In the LED chip provided in the above embodiment, the substrate, the epitaxial structure, the annealing layer, and the first electrode are sequentially disposed, and the first electrode is located on the upper surface of the annealing layer and the exposed epitaxial structure; annealing treatment is carried out on the formed structure, so that electrons are injected into the epitaxial structure through the annealing layer, the hole concentration in the epitaxial structure is improved, the uneven distribution of the electrons and the holes is improved, the problem that the electrons overflow and scatter to the epitaxial structure due to high electron concentration and fast migration is avoided, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a schematic flow chart of a method for fabricating a semiconductor structure provided in an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a substrate, a plurality of material layers forming an epitaxial structure, and an annealing material layer according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a structure obtained after forming an epitaxial structure and an anneal layer provided in an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a structure obtained by forming an opening according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a structure obtained after forming a first electrode and a second electrode provided in an embodiment of the present application;
FIG. 6 is a schematic structural diagram of a substrate, multiple material layers forming an epitaxial structure, and an annealing material layer provided in another embodiment of the present application;
fig. 7 is a schematic structural view of a structure obtained after formation of an epitaxial structure and an annealed layer as provided in another embodiment of the present application;
fig. 8 is a schematic structural view of a structure obtained after forming a first electrode and a second electrode provided in another embodiment of the present application;
FIG. 9 is a schematic structural diagram of a substrate, multiple material layers forming an epitaxial structure, and an annealing material layer provided in yet another embodiment of the present application;
fig. 10 is a schematic structural view of a resulting structure after formation of an epitaxial structure and an anneal layer as provided in yet another embodiment of the present application;
fig. 11 is a schematic structural diagram of a structure obtained after forming a first electrode and a second electrode provided in still another embodiment of the present application. Description of reference numerals: 10. a substrate; 11. a substrate; 12. a buffer layer; 13. a non-doped layer; 14. an N-type semiconductor layer;
20. an epitaxial structure; 21. a light emitting layer; 211. a light emitting material layer; 22. a first P-type nitride layer; 221. a first P-type nitride material layer; 23. a P-type nitride barrier layer; 231. a P-type nitride barrier material layer; 24. a non-doped nitride layer; 241. a non-doped nitride layer; 25. a second P-type nitride layer; 251. a second P-type nitride material layer; 26. a P-type nitride stack; 261. a P-type nitride stacked material layer;
30. an annealing layer; 31. annealing the material layer; 311. an opening;
40. a first electrode; 41. a first N-type electrode; 42. a first P-type electrode;
50. a second electrode;
60. a transparent conductive layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The conventional LED chip structure generally includes a buffer layer, an undoped GaN layer, an n-type doping layer, a multi-quantum well layer light-emitting layer (MQW), an electron blocking layer, and a p-type layer. There are two problems: 1. because the mobility of electrons is faster than that of holes, the concentration of free electrons is higher than that of holes, and the doping of a p-type layer is difficult to obtain high hole concentration due to the passivation effect of H atoms, the electrons and holes in the MQW are easily distributed unevenly, the holes are concentrated in the MQW close to the p-type layer, and the holes are gradually attenuated towards the n-type direction to be not beneficial to the recombination of the electrons and the holes; 2. due to high electron concentration and fast migration, electrons easily overflow into the p-type layer and are combined with ionized holes in the p-type layer, so that the ionization efficiency of the holes is reduced, non-radiative recombination is generated, the injection efficiency of the holes is reduced, the luminous efficiency is caused to drop suddenly, and the operation under high current is more serious.
In one embodiment of the present application, as shown in fig. 1, there is provided a method for manufacturing an LED chip, including the steps of:
step S10: providing a substrate;
step S20: forming an epitaxial structure and an annealing layer, wherein the epitaxial structure is positioned on the upper surface of the substrate, the annealing layer is positioned on the upper surface of the epitaxial structure, and the annealing layer exposes the epitaxial structure; injecting electrons into the epitaxial structure during annealing treatment of the annealing layer so as to improve the concentration of holes in the epitaxial structure;
step S30: and forming a first electrode on the upper surface of the annealing layer and the exposed epitaxial structure.
In the preparation method of the LED chip provided in the above embodiment, the substrate, the epitaxial structure, the annealing layer, and the first electrode are sequentially disposed from bottom to top, and the first electrode is located on the upper surface of the annealing layer and the exposed epitaxial structure; annealing treatment is carried out on the formed structure, so that electrons are injected into the epitaxial structure through the annealing layer, the hole concentration in the epitaxial structure is improved, the uneven distribution of the electrons and the holes is improved, the problem that the electrons overflow and scatter to the epitaxial structure due to high electron concentration and fast migration is avoided, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
The substrate, the epitaxial structure, and the annealing layer provided in the embodiments of the present application may all adopt a Metal-organic Chemical Vapor Deposition (MOCVD) technique, which is not limited to this, and may also be other techniques for depositing a thin film.
In one embodiment, as shown in fig. 2, the substrate 10 provided in step S10 includes a substrate 11, a buffer layer 12, an undoped layer 13, and an N-type semiconductor layer 14 stacked in this order from bottom to top.
In one embodiment, the epitaxial structure 20 and the substrate 10 are in a mesa structure, and the epitaxial structure 20 exposes the substrate 10 (as shown in fig. 3).
By way of example, the substrate 11 includes, but is not limited to, any one or a combination of more of a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, a zinc oxide substrate, or an aluminum nitride substrate; after the substrate 11 is formed, the substrate 11 is subjected to a surface cleaning treatment of the substrate 11 in a hydrogen atmosphere at a temperature of 1200 ℃, and the cleaning treatment time may be 5 minutes.
As an example, the buffer layer 12 includes a nitride layer grown at a low temperature, and the buffer layer 12 has a thickness of 10nm to 100 nm; for example, the buffer layer 12 has a thickness of 10nm, 50nm, 80nm, or 100nm, etc. Specifically, the buffer layer 12 may be an undoped GaN layer, the Ga source required for growth is a trimethyl gallium (TMG) source, and the growth atmosphere is H2Atmosphere, growth temperature of 600 ℃ and growth pressure of 650 mbar.
As an example, undoped layer 13 comprises undoped materialThe thickness of the nitride layer and the undoped layer 13 is 1-5 um; for example, the thickness of undoped layer 13 is 1um, 2um, 3um, or 5um, etc. The undoped layer 13 may be an undoped GaN layer, the Ga source required for growth is TMG source, and the growth atmosphere is H2Atmosphere, growth temperature 1215 ℃, growth pressure 300 mbar.
As an example, the N-type semiconductor layer 14 includes an N-type nitride layer, the N-type semiconductor layer 14 having a thickness of 2.0 μm-5 um; for example, the thickness of the N-type semiconductor layer 14 is 2.0 μm, 2.5 μm, or 5.0 μm, etc. The N-type semiconductor layer 14 may be an N-type doped GaN layer, the dopant may be Si, and the doping concentration of Si is 5 × 1018cm-3The Ga source required by the growth is TMG source, and the growth atmosphere is H2Atmosphere, growth temperature of 1210 deg.C, growth pressure of 150 mbar.
In one embodiment, step S30: after forming the first electrode on the upper surface of the annealing layer and the exposed epitaxial structure, the method further includes:
step S40: applying a current to the first electrode, and annealing the resulting structure;
wherein the applied current is 1mA-40 mA; the temperature of the annealing treatment is 150-450 ℃, the time of the annealing treatment is 5-50 min, and the atmosphere of the annealing treatment comprises nitrogen atmosphere and/or oxygen atmosphere.
It should be noted that the resulting structure mentioned in step S40 may include a substrate, an epitaxial structure, an annealing layer, a first electrode, and a second electrode.
As an example, to ensure that the resulting structure is processed in a pure nitrogen and/or pure oxygen atmosphere, the resulting structure is placed on a heated platen inside a glove box for annealing. Optionally, the applied current is 1mA, 10mA, 20mA, or 40mA, etc.; the temperature of the annealing treatment is 150 ℃, 300 ℃ or 450 ℃ and the like; the time of the annealing treatment is 5min, 25min or 50min, etc.
Regarding the formation of the epitaxial structure, the annealing layer and the first electrode, the following three embodiments are described:
in one embodiment, step S20: forming an epitaxial structure and an annealing layer, comprising the following steps:
step S21: forming a light emitting material layer 211 on the upper surface of the substrate 10;
step S22: forming a P-type nitride stacked material layer 261 on the upper surface of the light emitting material layer 211;
step S23: forming an annealing material layer 31 on the upper surface of the P-type nitride stack material layer 261, as shown in fig. 2;
step S24: and sequentially etching and removing part of the annealing material layer 31, part of the P-type nitride laminated material layer 261 and part of the light-emitting material layer 211 to expose the N-type semiconductor layer 14, and forming a light-emitting layer 21, a P-type nitride laminated layer 26 and an annealing layer 30 which are sequentially laminated from bottom to top, wherein the light-emitting layer and the P-type nitride laminated layer 26 jointly form the epitaxial structure 20, as shown in fig. 3.
In one embodiment, as shown in fig. 2, step S22: forming a P-type nitride stacked material layer on the upper surface of the light-emitting material layer, comprising the steps of:
step S221 a: forming a first P-type nitride material layer 221 on the top surface of the light emitting material layer 211;
step S222 a: forming a P-type nitride blocking material layer 231 on the upper surface of the first P-type nitride material layer 221;
step S223 a: forming an undoped nitride material layer 241 on the upper surface of the P-type nitride barrier material layer 231;
step S224 a: a second P-type nitride material layer 251 is formed on the upper surface of the undoped nitride material layer 241.
Specifically, after a part of the P-type nitride stacked material layer 261 is etched, a first P-type nitride layer 22, a P-type nitride barrier layer 23, an undoped nitride layer 24 and a second P-type nitride layer 25 are formed, which are stacked in sequence from bottom to top, and the first P-type nitride layer 22, the P-type nitride barrier layer 23, the undoped nitride layer 24 and the second P-type nitride layer 25 together form a P-type nitride stacked layer 26.
As an example, an Inductively Coupled Plasma (ICP) technique may be used to etch a portion of the annealed material layer 31, a portion of the second P-type nitride material layer 251, a portion of the undoped nitride material layer 241, a portion of the P-type nitride blocking material layer 231, a portion of the first P-type nitride material layer 221, and a portion of the light emitting material layer 211.
As an example, the light emitting material layer 211 is a nitride quantum well layer having a thickness of 1 to 15nm and a nitride quantum barrier layer having a thickness of 3 to 20nm, and has 1 to 30 periodic cycle repeating structures; for example, the thickness of the nitride quantum well layer is 1nm, 3nm, 15nm, or the like; the thickness of the quantum barrier layer is 3nm, 11nm or 20nm and the like. The nitride quantum well layer comprises an InGaN layer, the growth temperature is 850 ℃, the growth pressure is 300mbar, a Ga source required by growth is a TEGa source, and an In source required by growth is a TMIn source; the nitride quantum barrier layer comprises a GaN layer, the growth temperature is 950 ℃, the growth pressure is 400mbar, and the Ga source required by growth is a TEGa source.
Optionally, the nitride quantum well layer and the nitride quantum barrier layer total 10 pairs.
Alternatively, the In composition In the light emitting layer 21 may be changed to realize that the light emitting band of the LED chip is In the ultraviolet to green wavelength range.
As an example, the first P-type nitride material layer 221 includes a low-temperature grown P-type GaN layer having a thickness of 20nm to 200 nm; for example, the thickness of the P-type GaN layer is 20nm, 50nm, or 200nm, etc. The P-type doping material is magnesium, and the doping concentration of the magnesium is 2 multiplied by 1019cm-3The Ga source required by the growth is TMG source, and the growth atmosphere is switched to H2Atmosphere, growth temperature 1100 ℃.
As an example, the P-type nitride blocking material layer 231 includes a P-type doped AlGaN layer, and the thickness of the P-type nitride blocking material layer 231 is 10nm to 150 nm; for example, the P-type nitride barrier material layer 231 has a thickness of 10nm, 100nm, 150nm, or the like. The Ga source required by growth is TMG source, the Al source is TMAl source, and the growth atmosphere is N2Atmosphere, growth temperature of 1000 ℃ and growth pressure of 150 mbar.
As an example, the undoped nitride material layer 241 includes an undoped GaN layer, and the thickness of the undoped nitride material layer 241 is 10nm-100nm, such as 10nm, 15nm or 100nm, etc. of the undoped nitride material layer 241. The Ga source required for growth is TMG source, and the growth is carried outAtmosphere is switched to H2Atmosphere, growth temperature 1100 deg.C, growth pressure 500 mbar.
In one embodiment, the second P-type nitride layer 25 has a magnesium-hydrogen complex therein; the annealing layer 30 injects electrons into the second P-type nitride layer 25, the electrons capture magnesium-hydrogen bonds to decompose and form hydrogen ions, the P-type nitride doping activation efficiency is improved, the hole concentration of the second P-type nitride layer 25 is greatly improved, and the hole injection of the LED chip is improved, so that the problem that the electrons and holes are unevenly distributed is solved, the problem that the electrons overflow to an epitaxial structure due to high electron concentration and fast migration is solved, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
As an example, the thickness of the second P-type nitride layer 25 is 30nm to 300 nm; such as a thickness of 30nm, 45nm, 300nm, etc., for the second P-type nitride layer 25. The second P-type nitride layer 25 may be a P-type GaN layer, the P-type doping material is magnesium, and the magnesium doping concentration is 5 × 1019cm-3The Ga source required by the growth is TMG source, and the growth atmosphere is switched to H2Atmosphere, growth temperature 1100 deg.C, growth pressure 500 mbar.
As an example, the thickness of the annealing material layer 31 is 1nm-150nm, such as the thickness of the annealing material layer 31 is 1nm, 50nm or 150nm, etc. The annealed material layer 31 includes an N-type GaN layer, the dopant is Si, and the doping concentration of Si is 5 × 1018cm-3The Ga source required by the growth is TMG source, and the growth atmosphere is H2Atmosphere, growth temperature of 1210 deg.C, growth pressure of 150 mbar.
In one embodiment, step S20: after forming the annealed layer 30, the method further includes:
step S201: the annealed layer 30 is etched to have an opening 311 in the annealed layer 30, and the opening 311 exposes the upper surface of the epitaxial structure 20, as shown in fig. 4.
In one embodiment, as shown in fig. 5, the annealing layer includes an N-type nitride layer, and the step S30: forming the first electrode 40 on the upper surface of the annealed layer 30 and the exposed epitaxial structure 20 includes:
step S31 a: a first N-type electrode 41 is formed on the upper surface of the anneal layer 30, and a first P-type electrode 42 is formed in the opening 311, wherein the first P-type electrode 42 and the first N-type electrode 41 together form a first electrode 40.
Specifically, the opening 311 exposes the upper surface of the second P-type nitride layer 25, and the first P-type electrode 42 is formed on the upper surface of the portion of the second P-type nitride layer 25 exposed by the opening 311.
In an embodiment, please continue to refer to fig. 5, fig. 8, and fig. 11, step S20: after forming the annealed layer 30, the method further includes:
step S202: a second electrode 50 is formed on the exposed upper surface of the N-type semiconductor layer 14.
As an example, the second electrode 50 includes an N-type electrode; the first electrode 40 and the second electrode 50 may be prepared simultaneously or in separate steps; the material of the first electrode 40 comprises a single layer or a multi-layer combination of metal Cr, Al, Au, Pt, Pd, Ti, Ta and Ni; the material of the second electrode 50 comprises a single layer or a multi-layer combination of metal Cr, Al, Au, Pt, Pd, Ti, Ta and Ni; the material of the first electrode 40 and the material of the second electrode 50 may be the same or different.
In one embodiment, as shown in fig. 5, 8 and 11, a step of forming a transparent conductive layer 60 is further included before forming the first electrode 40 and the second electrode 50, and the first electrode 40 is located on an upper surface of the transparent conductive layer 60.
As an example, the transparent conductive layer 60 includes an indium tin oxide material (ITO), and the thickness of the transparent conductive layer 60 is 50nm to 250 nm; for example, the thickness of the transparent conductive layer 60 is 50nm, 150nm, 250nm, or the like.
In another embodiment, as shown in fig. 6, step S22: forming a P-type nitride stacked material layer on the upper surface of the light-emitting material layer, comprising the steps of:
step S221 b: forming a first P-type nitride material layer 221 on the top surface of the light emitting material layer 211;
step S222 b: forming an undoped nitride material layer 241 on the upper surface of the first P-type nitride material layer 221;
step S223 b: forming a P-type nitride blocking material layer 231 on the upper surface of the first P-type nitride material layer 221;
step S224 b: a second P-type nitride material layer 251 is formed on the upper surface of the P-type nitride barrier material layer 231.
Specifically, after etching a part of the P-type nitride stacked material layer 261, the annealing material layer 31 and the second P-type nitride material layer 251 are etched to expose the P-type nitride blocking material layer 231, and a first P-type nitride layer 22, an undoped nitride layer 24, a P-type nitride blocking layer 23 and a second P-type nitride layer 25 are formed, which are sequentially stacked from bottom to top, and the first P-type nitride layer 22, the undoped nitride layer 24, the P-type nitride blocking layer 23 and the second P-type nitride layer 25 together form a P-type nitride stacked layer 26, as shown in fig. 7.
Please refer to the foregoing paragraphs for the methods for fabricating the light emitting material layer 211, the first P-type nitride material layer 221, the undoped nitride material layer 241, the P-type nitride blocking material layer 231, the second P-type nitride material layer 251 and the annealing material layer 31, which will not be described herein again.
In another embodiment, as shown in fig. 8, step S30: forming a first electrode 40 on the upper surface of the annealed layer 30 and the exposed epitaxial structure 20, includes:
step S31 b: forming a first N-type electrode 41 on the upper surface of the annealing layer, and forming a first P-type electrode 42 on the upper surface of the P-type nitride barrier layer 23, wherein the first P-type electrode 42 is located on two opposite sides of the second P-type nitride layer 25 and the annealing layer 30; the first N-type electrode 41 and the first P-type electrode 42 together constitute a first electrode 40.
In yet another embodiment, as shown in fig. 9, step S22: forming a P-type nitride stacked material layer on the upper surface of the light-emitting material layer, comprising the steps of:
step S221 c: forming an undoped nitride material layer 241 on the upper surface of the light emitting material layer 211;
step S222 c: forming a first P-type nitride material layer 221 on the upper surface of the undoped nitride material layer 241;
step S223 c: forming a P-type nitride blocking material layer 231 on the upper surface of the first P-type nitride material layer 221;
step S224 c: a second P-type nitride material layer 251 is formed on the upper surface of the P-type nitride barrier material layer 231.
Specifically, after etching a part of the P-type nitride stacked material layer 261, the annealing material layer 31, the second P-type nitride material layer 251 and the P-type nitride blocking material layer 231 are etched to expose the first P-type nitride material layer 221, and the undoped nitride layer 24, the first P-type nitride layer 22, the P-type nitride blocking layer 23 and the second P-type nitride layer 25 are formed, which are sequentially stacked from bottom to top, wherein the undoped nitride layer 24, the first P-type nitride layer 22, the P-type nitride blocking layer 23 and the second P-type nitride layer 25 together form the P-type nitride stacked layer 26, as shown in fig. 10.
For details of the preparation methods of the light emitting material layer 211, the undoped nitride material layer 241, the first P-type nitride material layer 221, the P-type nitride blocking material layer 231, the second P-type nitride material layer 251 and the annealing material layer, please refer to the foregoing, and further description thereof is omitted.
In yet another embodiment, as shown in fig. 11, step S30: forming a first electrode 40 on the upper surface of the annealed layer 30 and the exposed epitaxial structure 20, includes:
step S31 c: forming a first N-type electrode 41 on the upper surface of the anneal layer 30, and forming a first P-type electrode 42 on the upper surface of the first P-type nitride layer 22, wherein the first P-type electrode 42 is located on two opposite sides of the anneal layer 30, the second P-type nitride layer 25, and the P-type nitride barrier layer 23; the first N-type electrode 41 and the first P-type electrode 42 together constitute a first electrode 40.
In an embodiment of the present application, there is also provided an LED chip including: a substrate 10; an epitaxial structure 20 on the upper surface of the substrate 10; an annealing layer 30 located on the upper surface of the epitaxial structure 20, wherein the annealing layer 30 exposes the epitaxial structure 20; the annealed layer 30 injects electrons into the epitaxial structure 20 during the annealing process to increase the hole concentration in the epitaxial structure 20; a first electrode 40 is disposed on the upper surface of the anneal layer 30 and the exposed epitaxial structure 20.
In the LED chip provided in the above embodiment, the substrate, the epitaxial structure, the annealing layer, and the first electrode are sequentially disposed, and the first electrode is located on the upper surface of the annealing layer and the exposed epitaxial structure; annealing treatment is carried out on the formed structure, so that electrons are injected into the epitaxial structure through the annealing layer, the hole concentration in the epitaxial structure is improved, the uneven distribution of the electrons and the holes is improved, the problem that the electrons overflow and scatter to the epitaxial structure due to high electron concentration and fast migration is avoided, the ionization efficiency and the radiation recombination efficiency of the holes are improved, and the efficiency dip effect under high current is improved.
In one embodiment, the substrate 10 includes a substrate 11, a buffer layer 12, an undoped layer 13, and an N-type semiconductor layer 14, which are sequentially stacked from bottom to top.
In one embodiment, the first electrode 40 includes a first P-type electrode 42 and a first N-type electrode 41; the first N-type electrode 41 is located on the upper surface of the annealed layer 30.
In one embodiment, the epitaxial structure 20 includes a light emitting layer 21 and a P-type nitride layer 26 stacked in sequence from bottom to top; the P-type nitride layer 26 includes a first P-type nitride layer 22, a P-type nitride barrier layer 23, an undoped nitride layer 24, and a second P-type nitride layer 25 stacked in sequence from bottom to top.
Specifically, the annealing layer 30 has an opening 311 therein, and the opening 311 exposes the second P-type nitride layer 25; the first P-type electrode 42 is located in the opening 311.
In another embodiment, the epitaxial structure 20 includes a light emitting layer 21 and a P-type nitride layer 26 stacked in this order from bottom to top; the P-type nitride layer 26 includes a first P-type nitride layer 22, an undoped nitride layer 24, a P-type nitride barrier layer 23, and a second P-type nitride layer 25 stacked in sequence from bottom to top.
Specifically, the first P-type electrode 42 is located on the upper surface of the P-type nitride barrier layer 23 and located on two opposite sides of the second P-type nitride layer 25 and the annealing layer 30.
In a further embodiment, the epitaxial structure 20 includes a light-emitting layer 21 and a P-type nitride layer 26 stacked in this order from bottom to top; the P-type nitride layer 26 includes an undoped nitride layer 24, a first P-type nitride layer 22, a P-type nitride barrier layer 23, and a second P-type nitride layer 25 stacked in sequence from bottom to top.
As an example, the first P-type electrode 42 is located on the upper surface of the first P-type nitride layer 22 and on two opposite sides of the anneal layer 30, the second P-type nitride layer 25, and the P-type nitride barrier layer 23.
In one embodiment, the second P-type nitride layer 25 has a magnesium-hydrogen complex therein; the annealed layer 30 injects electrons into the second P-type nitride layer 25, and the electrons trap magnesium-hydrogen bonds and decompose to form hydrogen ions, so as to increase the hole concentration in the second P-type nitride layer 25.
In one embodiment, the semiconductor structure further includes a second electrode 50, the second electrode 50 being located on an upper surface of the N-type semiconductor layer 14.
In one embodiment, the semiconductor structure further comprises a transparent conductive layer 60; the first electrode 40 is located on the upper surface of the transparent conductive layer 60.
The following specific examples were prepared using the fabrication method of the present invention as shown in FIG. 5, chip size 1530; wherein the substrate 11 is a sapphire substrate; the buffer layer 12 is undoped gallium nitride with the thickness of 20 nm; the undoped layer 13 is undoped GaN with a thickness of 2 μm; the N-type semiconductor layer is an N-type doped GaN layer, and the doping concentration of Si is 5 multiplied by 1018cm-3(ii) a The light emitting material layer 211 is an InGaN quantum well layer and a GaN quantum barrier layer with 10 cycles and repeats, the thickness of the InGaN quantum well is 3nm, and the thickness of the GaN quantum barrier is 11 nm; the first P-type nitride material layer 221 is a P-type GaN layer with a thickness of 50nm and a Mg doping concentration of 2 × 1019cm-3(ii) a The P-type nitride barrier material layer 231 is a P-type doped AlGaN layer with a thickness of 100nm and a Mg doping concentration of 6 × 1019cm-3(ii) a The undoped nitride material layer 241 is an undoped GaN layer with a thickness of 15nm, the second P-type nitride layer 25 is a P-type GaN layer with a thickness of 45nm, and the Mg doping concentration is 5 × 1019cm-3(ii) a The annealed material layer 31 was an N-type GaN layer with a thickness of 50nm and a doping concentration of Si of 5X 1018cm-3。
Example 1
As with the above structure, the annealing layer has a thickness of 50nm and is annealed at 300 deg.C for 20min under the condition of 20mA current.
Comparative example 1
Unlike example 1, comparative example 1, in which the annealing material layer 31 and the first electrode 40 were not provided, was annealed at a temperature of 300 ℃ using a conventional furnace tube for 20 min.
Comparative example 2
Unlike example 1, comparative example 2, in which the annealing material layer 31 and the first electrode 40 were not provided, was annealed at a temperature of 100 ℃ using a conventional furnace tube for 20 min.
Comparative example 3
Unlike example 1, comparative example 3, in which the annealing material layer 31 and the first electrode 40 were not provided, was annealed at a temperature of 450 ℃ using a conventional furnace tube for 20 min.
Comparative example 4
Unlike example 1, comparative example 4, in which the annealing material layer 31 and the first electrode 40 were not provided, was annealed at a temperature of 750 ℃ using a conventional furnace tube for 20 min.
Comparative example 5
Comparative example 5 differs from example 1 in that: the annealed material layer 31 was a p-type GaN layer with a thickness of 50 nm.
Comparative example 6
The differences with respect to example 1 are: the annealed material layer 31 is an undoped GaN layer with a thickness of 50 nm.
Comparative example 7
Comparative example 7 differs from comparative example 5 in that the annealing temperature is 450 ℃.
Comparative example 8
Comparative example 8 differs from comparative example 5 in that the annealing temperature is 750 ℃.
The test data for example 1 and comparative examples 1-8 are given in the following table:
compared with the conventional chip adopting the conventional high-temperature annealing furnace for annealing, the chip disclosed by the embodiment 1 of the invention has higher brightness and lower voltage, so that the test data show that the chip disclosed by the embodiment of the invention improves the hole concentration in the epitaxial structure 20 by injecting electrons into the epitaxial structure 20 through the annealing layer 30 during annealing treatment, thereby improving the uneven distribution of the electrons and the holes, avoiding the problem that the electrons overflow and scatter into the epitaxial structure due to high electron concentration and fast migration, improving the ionization efficiency and radiation recombination efficiency of the holes and improving the efficiency dip effect under high current.
In addition, as seen from the data, the annealing material layer 31 and the first electrode 40 are not arranged, and the chip does not emit light at the conventional chip annealing temperature lower than 450 ℃, and the P-type doping in the epitaxial structure can be activated only by annealing the chip at high temperature (not less than 450 ℃), so that compared with the conventional chip process, the annealing temperature of the second P-type nitride layer 25 is greatly reduced, the quality damage of the high-temperature annealing to a light emitting region is reduced, and the photoelectric property of the LED chip is improved.
Moreover, it can be seen from the data that the effect of the embodiment of the present invention is not achieved by using the p-type GaN layer or the undoped GaN layer as the annealing layer 30, and the performance of the embodiment 7 and the embodiment 8 that the annealing temperature of the annealing layer 30 is increased can only reach the performance basically equivalent to that of the conventional chip process, so that the concentration of holes in the epitaxial structure 20 is increased by injecting electrons into the epitaxial structure 20 through the annealing layer 30 during annealing treatment, thereby improving the non-uniform distribution of electrons and holes, avoiding the problem that electrons overflow to the epitaxial structure due to high electron concentration and fast migration, improving the ionization efficiency and radiation recombination efficiency of holes, and improving the efficiency dip effect under a large current.
Example 2
Example 2 differs from example 1 in that the annealing time was 5 min.
Example 3
Example 3 differs from example 1 in that the annealing time was 50 min.
Example 4
Example 4 differs from example 1 in that the annealing time was 60 min.
Example 5
Example 5 differs from example 1 in that the annealing time was 1 min.
The annealing temperature was kept constant at 300 ℃ and the annealing time was varied, and the test data for example 2, example 3, example 4 and example 5 are given in the following table:
| annealing at 300 deg.C | Annealing time (min) | Voltage (VF) | Luminance (mW) | droop(％) |
| Example 1 | 20min | 3.10 | 242 | 40.1％ |
| Example 2 | 5min | 3.12 | 238 | 43.4％ |
| Example 3 | 50min | 3.11 | 240 | 42.2％ |
| Example 4 | 60min | 3.13 | 235 | 46.2％ |
| Example 5 | 1min | 3.14 | 232 | 46.9％ |
Within the annealing time range of 5min-60min, the test voltage, brightness and efficiency drop droop performance of the LED chip of the present invention are all improved, and it can be found that the optimal performance is obtained by annealing at 300 ℃ for 20min in the present embodiment 1, the electron injected into the epitaxial structure 20 cannot be effectively formed to increase the hole concentration in the epitaxial structure 20 if the annealing time is too low, and the performance of the electron injected into the epitaxial structure 20 if the annealing time is too long shows a downward trend, possibly because the electron injected into the epitaxial structure 20 for forming a new donor structure compensates the hole concentration if the annealing time is too long.
Example 6
The difference with respect to example 1 is that the annealing temperature was 150 ℃.
Example 7
The difference with respect to example 1 is that the annealing temperature was 450 ℃.
Example 8
The difference with respect to example 1 is that the annealing temperature was 500 ℃.
Example 9
The difference with respect to example 1 is that the annealing temperature was 100 ℃.
The test data for example 6, example 7, example 8 and example 9 are given in the following table:
| annealing for 20min | Annealing temperature (. degree.C.) | Voltage (VF) | Luminance (mW) | droop(％) |
| Example 1 | 300 | 3.10 | 242 | 40.1％ |
| Example 6 | 150 | 3.12 | 239 | 40.9％ |
| Example 7 | 450 | 3.11 | 240 | 41.2％ |
| Example 8 | 500 | 3.13 | 235 | 46.7％ |
| Example 9 | 100 | 3.14 | 232 | 47.0％ |
From the data, it can be seen that, in the annealing temperature range of 150 ℃ to 300 ℃, the test voltage, brightness and efficiency drop performance of the LED chip of the present invention are all improved, and it can be found that in this embodiment 1, the optimal performance is obtained by annealing at 300 ℃ for 20min, the electron injection into the epitaxial structure 20 cannot be effectively formed at too low an annealing temperature to increase the hole concentration in the epitaxial structure 20, and the performances show a decreasing trend at too high an annealing temperature, possibly because the electron injection into the epitaxial structure 20 takes too long to form a new donor structure to compensate the hole concentration.
Example 10
Example 10 differs from example 1 in that the annealing temperature and annealing time are 450 ℃ and 5min, respectively.
Example 11
Example 11 differs from example 1 in that the annealing temperature and annealing time are 150 ℃ and 50min, respectively.
The test data for example 10 and example 11 are as follows:
| annealing time (min)&Temperature (. degree.C.) | Voltage (VF) | Luminance (mW) | droop(％) | |
| Example 1 | 20min&300℃ | 3.10 | 242 | 40.1％ |
| Example 10 | 5min&450℃ | 3.11 | 241 | 40.9％ |
| Example 11 | 50min％150℃ | 3.11 | 243 | 40.2％ |
It can be seen from the data that compared with example 1, the performance substantially equivalent to that of example 1 can be obtained under the conditions of 450 ℃ and 150 ℃ for 5min annealing and 50min annealing respectively, namely, the annealing time is inversely related to the annealing temperature, the annealing temperature is increased while the annealing time is reduced, and the performance equivalent to that of example 1 can be achieved. Therefore, the invention can match the annealing time and the annealing temperature, effectively form electrons injected into the epitaxial structure 20 and improve the hole concentration in the epitaxial structure 20, thereby improving the uneven distribution of the electrons and the holes, avoiding the problem that the electrons overflow into the epitaxial structure due to high electron concentration and fast migration, improving the ionization efficiency and the radiation recombination efficiency of the holes and improving the efficiency dip effect under large current.
Example 12
Example 12 differs from example 1 in that the annealing layer thickness is 1 nm.
Example 13
Example 13 differs from example 1 in that the annealed layer had a thickness of 150 nm.
Example 14
Example 14 differs from example 1 in the thickness of the annealing layer being 1nm and the annealing temperature being 100 ℃.
Example 15
Example 15 differs from example 1 in the annealed layer thickness of 1nm and the annealing time of 5 min.
Example 16
Example 16 differs from example 1 in the annealed layer thickness of 150nm, the annealing time of 5min and the annealing temperature of 450 ℃.
Example 17
Example 17 differs from example 1 in the annealed layer thickness 150nm, annealing time 50min and annealing temperature 150 ℃.
Example 12, example 13, example 14, example 15, example 16 and example 17 were compared mainly for differences in annealed layer thickness, annealing time and annealing temperature, and the test data for example 12, example 13, example 14, example 15, example 16 and example 17 are as follows:
| annealing layer thickness (nm) | Annealing time (min)&Temperature (. degree.C.) | Voltage (VF) | Luminance (mW) | droop(％) | |
| Example 1 | 50 | 20min&300℃ | 3.10 | 242 | 40.1％ |
| Example 12 | 1 | 20min&300℃ | 3.13 | 238 | 43.9％ |
| Example 13 | 150 | 20min&300℃ | 3.13 | 239 | 42.5％ |
| Example 14 | 1 | 20min&100℃ | 3.11 | 243 | 40.8％ |
| Example 15 | 1 | 5min&300℃ | 3.10 | 243 | 40.6％ |
| Example 16 | 150 | 5min&450℃ | 3.10 | 241 | 40.5％ |
| Example 17 | 150 | 50min&150℃ | 3.11 | 243 | 40.2％ |
As can be seen from the data, the annealed layer 30 is relatively thin, and the annealing temperature or annealing time can be decreased to substantially the same effect as in example 1, and the annealed layer 30 is relatively thick, and the annealing temperature or annealing time can be increased to substantially the same effect as in example 1.
The excessively increased annealing time and annealing temperature test data are relatively poor when the annealed layer 30 is relatively thin, possibly due to compensation of new donor structure formed by injection of electrons into the epitaxial structure 20 in the annealed layer 30, and relatively poor when the annealed layer 30 is relatively thick, the hole concentration is increased by the annealing time or the annealing temperature is not of sufficient magnitude, possibly due to relatively poor injection of electrons into the epitaxial structure 20 in the annealed layer 30.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application, and it should be noted that, for chips smaller or larger than the chips of the present embodiment in size, matching of the annealing time and the annealing temperature can also be performed according to the actual process to obtain LED chips with excellent performance.
It should be understood that the steps described are not to be performed in the exact order recited, and that the steps may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps described may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the sub-steps or stages of other steps.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A preparation method of an LED chip is characterized by comprising the following steps:
providing a substrate;
forming an epitaxial structure and an annealing layer, wherein the epitaxial structure is positioned on the upper surface of the substrate, the annealing layer is positioned on the upper surface of the epitaxial structure, and the annealing layer is exposed out of the epitaxial structure; injecting electrons into the epitaxial structure during annealing treatment of the annealing layer so as to improve the concentration of holes in the epitaxial structure;
and forming a first electrode on the upper surface of the annealing layer and the exposed epitaxial structure.
2. The method of claim 1, wherein after forming the first electrode on the upper surface of the annealed layer and the exposed epitaxial structure, further comprising:
applying a current to the first electrode and performing the annealing treatment on the resulting structure;
wherein the applied current is 1mA-40 mA; the temperature of the annealing treatment is 150-450 ℃, the time of the annealing treatment is 5-50 min, and the atmosphere of the annealing treatment comprises nitrogen atmosphere and/or oxygen atmosphere.
3. The method according to claim 1, wherein the substrate comprises a substrate, a buffer layer, a non-doped layer and an N-type semiconductor layer which are sequentially stacked from bottom to top; the epitaxial structure and the annealing layer are formed, and the method comprises the following steps:
forming a luminescent material layer on the upper surface of the substrate;
forming a P-type nitride laminated material layer on the upper surface of the light-emitting material layer;
forming an annealing material layer on the upper surface of the P-type nitride laminated material layer;
sequentially etching and removing part of the annealing material layer, part of the P-type nitride laminated material layer and part of the light-emitting material layer to expose the N-type semiconductor layer and form a light-emitting layer, a P-type nitride laminated layer and an annealing layer which are sequentially overlapped from bottom to top, wherein the light-emitting layer and the P-type nitride laminated layer jointly form the epitaxial structure;
after the annealing layer is formed, the method further comprises the following steps: and forming a second electrode on the exposed upper surface of the N-type semiconductor layer.
4. The method according to claim 3, wherein forming a P-type nitride stack material layer on the top surface of the light-emitting material layer comprises:
forming a first P-type nitride material layer on the upper surface of the light-emitting material layer;
forming a P-type nitride blocking material layer on the upper surface of the first P-type nitride material layer;
forming a non-doped nitride material layer on the upper surface of the P-type nitride barrier material layer;
forming a second P-type nitride material layer on the upper surface of the undoped nitride material layer;
and after etching the part of the P-type nitride laminated material layer, forming a first P-type nitride layer, a P-type nitride barrier layer, a non-doped nitride layer and a second P-type nitride layer which are sequentially laminated from bottom to top, wherein the first P-type nitride layer, the P-type nitride barrier layer, the non-doped nitride layer and the second P-type nitride layer jointly form the P-type nitride laminated layer.
5. The method for manufacturing an LED chip according to claim 4, wherein the second P-type nitride layer has a magnesium-hydrogen complex therein; and the annealing layer injects electrons into the second P-type nitride layer, and the electrons capture magnesium-hydrogen bonds to decompose to form hydrogen ions so as to improve the hole concentration in the second P-type nitride layer.
6. The method for manufacturing an LED chip according to claim 1, wherein after the forming the annealing layer, the method further comprises:
etching the annealing layer to form an opening in the annealing layer, wherein the opening exposes the upper surface of the epitaxial structure;
wherein, the annealing layer includes N type nitride layer, it includes to form first electrode on the upper surface of annealing layer and the epitaxial structure that exposes:
and forming a first N-type electrode on the upper surface of the annealing layer, and forming a first P-type electrode in the opening, wherein the first P-type electrode and the first N-type electrode jointly form the first electrode.
7. An LED chip, comprising:
a substrate;
the epitaxial structure is positioned on the upper surface of the substrate;
the annealing layer is positioned on the upper surface of the epitaxial structure and exposes out of the epitaxial structure; injecting electrons into the epitaxial structure during annealing treatment of the annealing layer so as to improve the concentration of holes in the epitaxial structure;
and the first electrode is positioned on the upper surface of the annealing layer and the exposed epitaxial structure.
8. The LED chip of claim 7, wherein the epitaxial structure comprises a light-emitting layer and a P-type nitride stack layer which are stacked in sequence from bottom to top; the P-type nitride lamination layer comprises a first P-type nitride layer, a P-type nitride barrier layer, a non-doped nitride layer and a second P-type nitride layer which are sequentially stacked from bottom to top.
9. The LED chip of claim 8, wherein said second P-type nitride layer has a magnesium-hydrogen complex therein; and the annealing layer injects electrons into the second P-type nitride layer, and the electrons capture magnesium-hydrogen bonds to decompose to form hydrogen ions so as to improve the hole concentration in the second P-type nitride layer.
10. The LED chip of claim 8, wherein said first electrode comprises a first N-type electrode and a first P-type electrode, said first N-type electrode being located on an upper surface of said annealed layer; the annealing layer is internally provided with an opening which exposes the second insertion layer; the first P-type electrode is positioned in the opening;
the substrate comprises a substrate, a buffer layer, a non-doping layer and an N-type semiconductor layer which are sequentially stacked from bottom to top;
the LED chip further includes: and the second electrode is positioned on the upper surface of the N-type semiconductor layer.
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