CN217239491U

CN217239491U - Nitride light emitting diode

Info

Publication number: CN217239491U
Application number: CN202123384539.6U
Authority: CN
Inventors: 闫其昂; 王国斌
Original assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Current assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-08-19
Anticipated expiration: 2031-12-29

Abstract

The present application relates to a nitride light emitting diode including a substrate; the epitaxial structure is positioned on the surface of the substrate; the epitaxial structure comprises a light-emitting layer, a first type nitride lamination layer and a first type nitride contact layer; wherein the first type nitride lamination is positioned on the surface of the light-emitting layer, which is far away from the substrate; the first type nitride contact layer is positioned on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer; the orthographic projection of the first type nitride contact layer on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer, is positioned in the surface of the first type nitride lamination layer, and the edge of the first type nitride contact layer is spaced from the edge of the first type nitride lamination layer; and the transparent conducting layer is positioned on one side of the first type nitride lamination layer, which is far away from the light-emitting layer. The first type nitride contact layer in the nitride light-emitting diode can reduce the absorption of the first type nitride contact layer on the light emitted by the nitride light-emitting diode, and the light-emitting efficiency of the device is improved.

Description

Nitride light emitting diode

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a nitride light emitting diode.

Background

With the wide application of the high-power LED chip in the illumination field, it is a goal of the development of the LED illumination technology to further improve the luminous intensity and luminous efficiency of the LED, and on one hand, the brightness of the high-power LED chip should be improved, and on the other hand, the working voltage of the LED chip should be reduced.

At present, most of the LED chips form ohmic contact with the conductive layer by disposing a contact layer, so as to reduce the operating voltage; however, the contact layer absorbs light seriously, which affects the brightness of the chip.

SUMMERY OF THE UTILITY MODEL

In view of the above, there is a need to provide a nitride light emitting diode that addresses the above-mentioned shortcomings in the prior art.

To achieve the above and other objects, the present application provides a nitride light emitting diode according to some embodiments, including a substrate and an epitaxial structure on a surface of the substrate;

the epitaxial structure comprises a light emitting layer, a first type nitride lamination layer and a first type nitride contact layer; wherein the first type nitride stack layer is located on a surface of the light-emitting layer facing away from the substrate; the first type nitride contact layer is positioned on the surface of the first type nitride lamination layer, which faces away from the light-emitting layer; the orthographic projection of the first type nitride contact layer on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer, is positioned in the surface of the first type nitride lamination layer, and the edge of the first type nitride contact layer is spaced from the edge of the first type nitride lamination layer;

the nitride light emitting diode further includes:

and the transparent conducting layer is positioned on one side of the first type nitride lamination layer, which is far away from the light-emitting layer, and covers part of the surface of the first type nitride contact layer, which is far away from the first type nitride lamination layer.

The first type nitride contact layer in the nitride light-emitting diode provided by the embodiment can form good ohmic contact with the transparent conducting layer, so that the ohmic contact resistance is reduced, and the working voltage of the nitride light-emitting diode is reduced; meanwhile, the orthographic projection of the first type nitride contact layer on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer, is positioned in the surface of the first type nitride lamination layer, namely the contact area between the first type nitride contact layer and the first type nitride lamination layer is smaller, so that the absorption of the first type nitride contact layer on the light emitted by the nitride light-emitting diode can be reduced, and the light-emitting efficiency of the device is improved.

In one embodiment, the substrate comprises a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, a gallium oxide substrate, or a gallium nitride substrate.

In one embodiment, the transparent conductive layer comprises an indium tin oxide thin film layer.

In one embodiment, the thickness of the transparent conductive layer is 50nm to 250 nm.

In one embodiment, the first type nitride stack comprises:

the first P-type nitride layer is positioned on the surface, away from the substrate, of the light-emitting layer;

the P-type nitride electron blocking layer is positioned on the surface of the first P-type nitride layer, which is far away from the light-emitting layer;

and the second P-type nitride layer is positioned on the surface of the P-type nitride electron blocking layer, which is far away from the first P-type nitride layer.

In one embodiment, the epitaxial structure further comprises:

the nitride buffer layer is positioned on the surface of the substrate;

the undoped nitride layer is positioned on the surface of the nitride buffer layer, which faces away from the substrate;

a second type nitride layer located on a surface of the undoped nitride layer facing away from the nitride buffer layer; the light emitting layer is located on the surface of the second type nitride layer, which faces away from the undoped nitride layer.

In one embodiment, the nitride buffer layer comprises an undoped gallium nitride buffer layer; the undoped nitride layer comprises an undoped gallium nitride layer; the second type nitride layer comprises an N type gallium nitride layer; the light emitting layer includes a plurality of pairs of nitride quantum wells; the first P-type nitride layer comprises a P-type gallium nitride layer; the P-type nitride electronic barrier layer comprises a P-type doped aluminum gallium nitride layer; the second P-type nitride layer comprises a P-type gallium nitride layer; the first type nitride contact layer comprises a P-type indium gallium nitride layer; the transparent conductive layer comprises an indium tin oxide thin film layer.

The first type nitride contact layer in the nitride light-emitting diode provided by the embodiment comprises the P-type indium gallium nitride layer, so that the absorption of the first type nitride contact layer on the light emitted by the nitride light-emitting diode can be reduced, and the light-emitting efficiency of the device is improved; the P-type indium gallium nitride layer can form good ohmic contact with the electrode, and ohmic contact resistance is reduced, so that working voltage of the nitride light-emitting diode is reduced, and power conversion efficiency and reliability of the nitride light-emitting diode are improved.

In one embodiment, the thickness of the nitride buffer layer is 20nm to 60 nm; the thickness of the non-doped nitride layer is 1-3 mu m; the thickness of the second type nitride layer is 1-3 mu m; the thickness of the first P type nitride layer is 15 nm-100 nm; the thickness of the P-type nitride electron blocking layer is 15 nm-100 nm; the thickness of the second P-type nitride layer is 50 nm-200 nm; the first type nitride contact layer has a thickness of 1nm to 10 nm.

In one embodiment, the epitaxial structure further has a groove therein, the groove penetrates through the first type nitride contact layer, the second P-type nitride layer, the P-type nitride electron blocking layer, the first P-type nitride layer and the light emitting layer, and extends into the second type nitride layer to expose a portion of the second type nitride layer; the nitride light emitting diode further includes:

a P electrode located on a surface of the transparent conductive layer facing away from the first type nitride stack;

and the N electrode is positioned on the surface of the second type nitride layer exposed by the groove.

In one embodiment, the P-electrode comprises a nickel/gold P-type electrode; the N electrode comprises a titanium/aluminum/titanium/gold N-type electrode.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a method for fabricating a nitride light emitting diode according to an embodiment of the present disclosure;

fig. 2 is a flowchart of step S2 in a method for manufacturing a nitride light emitting diode according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step S1 in the method for manufacturing a nitride light emitting diode according to an embodiment of the present disclosure;

fig. 4 is a flowchart of step S2 in a method for manufacturing a nitride light emitting diode according to another embodiment of the present application;

fig. 5 is a flowchart of step S25 in a method for manufacturing a nitride light emitting diode according to another embodiment of the present application;

fig. 6 is a schematic cross-sectional structure view of a structure obtained by forming a first-type nitride contact material layer on a side of the first-type nitride stack layer away from the light-emitting layer in a method for manufacturing a nitride light-emitting diode according to an embodiment of the present disclosure;

fig. 7 to 9 are schematic cross-sectional structure diagrams of structures obtained in the steps of removing a portion of the first type nitride contact material layer in the method for manufacturing a nitride light emitting diode according to an embodiment of the present application;

fig. 10 is a schematic cross-sectional structure view of the structure obtained in step S4 in the method for manufacturing a nitride light emitting diode according to an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure view of the structure obtained in step S6 in the method for manufacturing a nitride light emitting diode according to an embodiment of the present disclosure; fig. 11 is a schematic cross-sectional view of a nitride light emitting diode according to an embodiment of the present disclosure.

Description of reference numerals:

10. a substrate; 20. an epitaxial structure; 201. a nitride buffer layer; 202. a non-doped nitride layer; 203. a second type nitride layer; 204. a light emitting layer; 205. a first type nitride stack; 215. a first P-type nitride layer; 225. a P-type nitride electron blocking layer; 235. a second P-type nitride layer; 206. a first type nitride contact layer; 216. a first type of nitride contact material layer; 30. a groove; 40. a transparent conductive layer; 501. an opening; 502. a P electrode; 601. an N electrode; 70. and patterning the photoresist layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on" a surface of another element or layer, it can be directly on the surface of the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first or second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first P-type nitride layer may be referred to as a second P-type nitride layer, and similarly, the second P-type nitride layer may be referred to as a first P-type nitride layer; the first P-type nitride layer and the second P-type nitride layer are different P-type nitride layers.

In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing techniques; the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

A light-emitting diode (LED) is a semiconductor light-emitting device, has the advantages of long service life, low energy consumption, small size, high reliability and the like, and plays an increasingly important role in the fields of large-screen color display, traffic signal lamps and illumination; among them, gallium nitride (GaN) -based leds are one of the most promising illumination sources at present, and are an important trend in the leading illumination technology.

With the wide application of the high-power LED chip in the illumination field, it is a goal of the development of the LED illumination technology to further improve the luminous intensity and luminous efficiency of the LED, and on one hand, the brightness of the high-power LED chip should be improved, and on the other hand, the working voltage of the LED chip should be reduced. At present, most of the LED chips form ohmic contact with the conductive layer by disposing a contact layer, so as to reduce the operating voltage; however, the contact layer absorbs light seriously, which affects the brightness of the chip.

In view of this, it is desirable to provide a solution to the above-mentioned deficiencies in the prior art, the details of which will be set forth in the following examples.

Referring to fig. 1 and 2, a method for fabricating a nitride light emitting diode is provided according to some embodiments; specifically, the preparation method can comprise the following steps:

s1: providing a substrate;

s2: forming an epitaxial structure on the surface of the substrate;

s4: and forming a transparent conductive layer on the side of the first type nitride lamination layer, which is far away from the light-emitting layer, wherein the transparent conductive layer also covers part of the surface of the first type nitride contact layer, which is far away from the first type nitride lamination layer.

As shown in fig. 2, step S2 may specifically include the following steps:

s24: forming a light emitting layer on a substrate;

s25: forming a first type nitride lamination on the surface of the light-emitting layer, which is far away from the substrate;

s26: and forming a first type nitride contact layer on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer, wherein the orthographic projection of the first type nitride contact layer on the surface of the first type nitride lamination layer, which is far away from the light-emitting layer, is positioned in the surface of the first type nitride lamination layer, and the edge of the first type nitride contact layer is spaced from the edge of the first type nitride lamination layer.

The first type nitride contact layer in the nitride light-emitting diode provided by the embodiment can form good ohmic contact with the transparent conducting layer, so that the ohmic contact resistance is reduced, and the working voltage of the nitride light-emitting diode is reduced; meanwhile, the orthographic projection of the first type nitride contact layer on the surface, away from the light emitting layer, of the first type nitride lamination layer is located in the surface of the first type nitride lamination layer, namely the contact area between the first type nitride contact layer and the first type nitride lamination layer is small, so that the absorption of the first type nitride contact layer on the light emitting of the nitride light emitting diode can be reduced, and the light emitting efficiency of the device is improved.

The method for manufacturing the nitride light emitting diode provided in the embodiments of the present application is described in more detail below.

Referring to fig. 3 in conjunction with S1 of fig. 1, a substrate 10 is provided for step S1.

It is to be understood that the material of the substrate 10 is not particularly limited in the present application; specifically, the substrate 10 may include, but is not limited to, any one or more of a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, a gallium nitride substrate, and the like.

In one embodiment, the method may further include cleaning the substrate 10 before forming the epitaxial structure 20 in step S2. The manner of performing the cleaning process is not particularly limited, and in one embodiment, the substrate 10 may be cleaned under a reducing atmosphere; the temperature of the cleaning treatment can be 1000-1500 ℃, and the time of the cleaning treatment can be 1-10 min.

It is to be understood that the above data are only examples, and the temperature and time of the cleaning process are not limited to the above data in the practical embodiment.

For step S2, please refer to fig. 3 and fig. 4 in conjunction with S2 of fig. 1; specifically, in one embodiment, step S24 may further include the following steps before:

s21: forming a nitride buffer layer 201 on the surface of the substrate 10;

s22: forming a non-doped nitride layer 202 on the surface of the nitride buffer layer 201 away from the substrate 10;

s23: a second type nitride layer 203 is formed on the surface of the undoped nitride layer 202 away from the nitride buffer layer 201.

The nitride buffer layer 201 referred to in the present application may include, but is not limited to, a low temperature nitride buffer layer; in one embodiment, the nitride buffer layer 201 includes an undoped gallium nitride buffer layer; the thickness of the nitride buffer layer 201 is not particularly limited, and in one embodiment, the thickness of the nitride buffer layer 201 is 20nm to 60nm, for example, the thickness of the nitride buffer layer 201 may be 20nm, 25nm, 35nm, 45nm, 60nm, or the like; the process for forming the buffer layer 201 is not particularly limited in this application; the gallium (Ga) source required to grow buffer layer 201 may be from, but is not limited to, trimethyl gallium (TM G); the growth atmosphere may include, but is not limited to, hydrogen (H) ₂ ) An atmosphere; the growth temperature may be 500 ℃ to 700 ℃, for example, the growth temperature may be 500 ℃, 550 ℃, 600 ℃, 650 ℃, 700 ℃, or the like; the growth pressure may be 550mbar to 750mbar, for example, the growth pressure may be 550mbar, 600mbar, 650mbar, 700mbar, or 750mbar, and so on.

The undoped nitride layer 202 referred to in the present application may include, but is not limited to, an undoped gallium nitride layer; in one embodiment, the undoped nitride layer 202 comprises an undoped gallium nitride layer; the thickness of the undoped nitride layer 202 is not particularly limited, and in one embodiment, the thickness of the undoped nitride layer 202 is 1 μm to 3 μm, for example, the thickness of the undoped nitride layer 202 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm, etc.; the present application is not limited to the process of forming the undoped nitride layer 202; the gallium source required to grow the undoped nitride layer 202 may be from, but is not limited to, trimethylgallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature may be 1115 to 1315 deg.C, for example, the growth temperature may be 1115, 1165, 1215, 1265, 1315 deg.C, etc.; the growth pressure may be 200mbar to 400mbar, for example, the growth pressure may be 200mbar, 250mbar, 300mbar, 350mbar, or 400mbar, and so forth.

The second type nitride layer 203 referred to in the present application may include, but is not limited to, an N-type nitride layer; in one embodiment, the second-type nitride layer 203 comprises an N-type gallium nitride layer; the thickness of the second type nitride layer 203 is not particularly limited, and in one embodiment, the thickness of the second type nitride layer 203 is 1 μm to 3 μm, for example, the thickness of the second type nitride layer 203 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, or the like; the process for forming the second type nitride layer 203 is not particularly limited; the second type nitride layer 203 may be formed by, but not limited to, doping silicon, and in the embodiment of doping silicon, the doping concentration of silicon may be 1 × 10 ¹⁸ cm ^-3 ～1×10 ²⁰ cm ^-3 For example, the doping concentration of silicon may be 1 × 10 ¹⁸ cm ^-3 、2.5×10 ¹⁸ cm ^-3 、5×10 ¹⁸ cm ^-3 、1×10 ¹⁹ cm ^-3 Or 1X 10 ²⁰ cm ^-3 And the like; the gallium source required to grow the second-type nitride layer 203 may be from, but is not limited to, trimethylgallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature may be 1110 ℃ to 1310 ℃, for example, the growth temperature may be 1110 ℃, 1160 ℃, 1210 ℃, 1260 ℃, 1310 ℃ or the like; the growth pressure may be 50mbar to 250mbar, for example, the growth pressure may be 50mbar, 100mbar, 150mbar, 200mbar, or 250mbar, and so on.

The light emitting layer 204 referred to in this application may include, but is not limited to, pairs of nitride quantum wells; in one embodiment, the nitride quantum well may comprise an indium gallium nitride (InGaN)/gallium nitride (GaN) quantum well structure comprising an indium gallium nitride (InGaN) quantum well and a gallium nitride (GaN) quantum barrier; the present application does not specifically limit the number of pairs of the gan in/gan quantum well structures in the light emitting layer 204, and in some examples, the light emitting layer 204 may include 3 to 20 pairs of nitride quantum wells, for example, the light emitting layer 204 may include 3, 5, 10, 15, or 20 pairs of nitride quantum wells.

In one embodiment, the light emitting layer 204 includes 10 pairs of indium gallium nitride/gallium nitride quantum well structures; the thicknesses of the gan-in quantum well and the gan quantum barrier are not particularly limited in the present application, and in one embodiment, the thickness of the gan-in quantum well is 2nm to 8nm, for example, the thickness of the gan-in quantum well may be 2nm, 3nm, 4nm, 6nm, or 8nm, etc.; the thickness of the gan quantum barrier is not limited in any way, and in one embodiment, the thickness of the gan quantum barrier is 3nm to 20nm, for example, the thickness of the gan quantum barrier may be 3nm, 7nm, 11nm, 15nm, or 20 nm; the present application does not specifically limit the process for forming the light-emitting layer 204; the gallium source required to grow the light-emitting layer 204 may be from, but is not limited to, triethylgallium (TEGa), and the indium source required may be from, but is not limited to, trimethylindium (TMIn); the growth atmosphere may include, but is not limited to, nitrogen (N) ₂ ) An atmosphere; specifically, the growth temperature of the gallium indium nitride quantum well may be 750 ℃ to 950 ℃, for example, the growth temperature of the gallium indium nitride quantum well may be 750 ℃, 800 ℃, 850 ℃, 900 ℃ or 950 ℃, and the like; the growth pressure of the gallium indium nitride quantum well can be 200 mbar-400 mbar, for example, the growth pressure of the gallium indium nitride quantum well can be 200mbar, 250mbar, 300mbar, 350mbar or 400mbar, etc.; the growth temperature of the gallium nitride quantum barrier may be 850-1050 ℃, for example, the growth temperature may be 850 ℃, 900 ℃, 950 ℃, 1000 ℃ or 1050 ℃, etc.; the growth pressure may be 300mbar to 500mbar, for example, the growth pressure may be 300mbar, 350mbar, 400mbar, 450mbar, or 500mbar, and so forth.

Referring to fig. 5, in one embodiment, the step S25 may specifically include the following steps:

s251: forming a first P-type nitride layer 215 on the surface of the light-emitting layer 204 away from the substrate 10;

s252: forming a P-type nitride electron blocking layer 225 on a surface of the first P-type nitride layer 215 away from the light-emitting layer 204;

s253: a second P-type nitride layer 235 is formed on the surface of P-type nitride electron blocking layer 225 facing away from first P-type nitride layer 215.

The first P-type nitride layer 215 referred to in this application may include, but is not limited to, a low temperature P-type nitride layer; in one embodiment, the first P-type nitride layer 215 comprises a P-type gallium nitride layer; the thickness of the first P-type nitride layer 215 is not particularly limited, and in one embodiment, the thickness of the first P-type semiconductor layer 205 is 15nm to 100nm, for example, the thickness of the first P-type nitride layer 215 may be 15nm, 35nm, 50nm, 75nm, 100nm, or the like; the process for forming the first P-type nitride layer 215 is not particularly limited; the gallium source required to grow the first P-type nitride layer 215 may be from, but is not limited to, trimethyl gallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature may be 820 ℃ to 1020 ℃, for example, the growth temperature may be 820 ℃, 870 ℃, 920 ℃, 970 ℃, or 1020 ℃ and the like; magnesium (Mg) doping may be used in the process of forming the first P-type nitride layer 215, but is not limited thereto, and in the embodiment of magnesium doping, the doping concentration of Mg may be 1 × 10 ¹⁹ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、2×10 ¹⁹ cm ^-3 、2.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

P-type nitride electron blocking layer 225 as referred to herein may include, but is not limited to, a low temperature P-type nitride electron blocking layer; in one embodiment, the P-type nitride electron blocking layer 225 comprises a P-type doped aluminum gallium nitride (AlGaN) layer; the thickness of the P-type nitride electron blocking layer 225 is not particularly limited, and in one embodiment, the thickness of the P-type nitride electron blocking layer 225 is 15nm to 100nm, for example, the thickness of the P-type nitride electron blocking layer 225 may be 15nm, 25nm, 50nm, 75nm, 100nm, or the like; the process for forming the P-type nitride electron blocking layer 225 is not particularly limited, and the gallium source required for growing the P-type nitride electron blocking layer 225 may be from, but not limited to, trimethylgallium, and the aluminum source may be requiredFrom trimethylaluminum (TMAl), the growth atmosphere may include, but is not limited to, a nitrogen atmosphere; the growth temperature may be 900 ℃ to 1100 ℃, for example, the growth temperature may be 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, or the like; the growth pressure may be 50mbar to 250mb ar, for example, the growth pressure may be 50mbar, 100mbar, 150mbar, 200mbar, or 250mbar, and so on; magnesium (Mg) doping may be used in the process of forming the P-type nitride electron blocking layer 225, but is not limited thereto, and in the embodiment using Mg doping, the Mg doping concentration may be 1 × 10 ¹⁹ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、2×10 ¹⁹ cm ^-3 、2.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

The second P-type nitride layer 235 referred to in the present application may include, but is not limited to, a P-type gallium nitride layer; in one embodiment, the second P-type nitride layer 235 comprises a P-type gallium nitride layer; the thickness of the second P-type nitride layer 235 is not particularly limited, and in one embodiment, the thickness of the second P-type nitride layer 235 is 50nm to 200nm, for example, the thickness of the second P-type nitride layer 235 may be 50nm, 80nm, 120nm, 150nm, 200nm, or the like; the process for forming the second P-type nitride layer 235 is not particularly limited, the gallium source required for growing the second P-type nitride layer 235 may be from, but not limited to, trimethyl gallium, and the growth atmosphere may include, but not limited to, a hydrogen atmosphere; the growth temperature may be 1040 ℃ to 1160 ℃, for example, the growth temperature may be 1040 ℃, 1070 ℃, 1100 ℃, 1130 ℃, 1160 ℃, or the like; the growth pressure may be 400mbar to 600mbar, for example, the growth pressure may be 400mbar, 450mbar, 500mbar, 550mbar, 600mbar, or the like; the second P-type nitride layer 235 may be formed by, but not limited to, mg doping, and in an embodiment of mg doping, the mg doping concentration may be 1 × 10 ¹⁹ cm ^-3 ～1×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、2.5×10 ¹⁹ cm ^-3 、5×10 ¹⁹ cm ^-3 、7.5×10 ¹⁹ cm ^-3 Or 1X 10 ²⁰ cm ^-3 And so on.

In step S26, referring to fig. 6, in one embodiment, the first-type nitride contact material layer 216 may be formed before the first-type nitride stack 205 on the side away from the light-emitting layer 204; in subsequent processes, a portion of the first type nitride contact material layer 216 is etched away, and the remaining first type nitride contact material layer 216 is the first type nitride contact layer 206.

Specifically, as shown in fig. 7 to 9, a portion of the first type nitride contact material layer 216 may be removed by, but not limited to, photolithography; in one embodiment, as shown in fig. 7, a patterned photoresist layer 70 is formed on a surface of the first type nitride contact material layer 216 facing away from the first type nitride stack 205, and the first type nitride contact material layer 216 is etched based on the patterned photoresist layer 70 to form a first type nitride contact layer 206, as shown in fig. 8; patterned photoresist layer 70 is removed as shown in fig. 9.

The first type of nitride contact layer 206 referred to in this application may include, but is not limited to, a P-type nitride contact layer; in one embodiment, the first-type nitride contact layer 206 comprises a P-type indium gallium nitride layer; the thickness of the first type nitride contact layer 206 is not particularly limited, and in one embodiment, the thickness of the first type nitride contact layer 206 is 1nm to 10nm, for example, the thickness of the first type nitride contact layer 206 may be 1nm, 2.5nm, 5nm, 7.5nm, 10nm, or the like; the process for forming the first-type nitride contact layer 206 is not particularly limited, the gallium source required for growing the first-type nitride contact layer 206 may be from, but not limited to, trimethylgallium, and the growth atmosphere may include, but not limited to, a hydrogen atmosphere; the growth temperature can be 680 deg.C to 880 deg.C, such as 680 deg.C, 730 deg.C, 780 deg.C, 830 deg.C or 880 deg.C; the growth pressure may be 300mbar to 500mbar, for example, the growth pressure may be 300mbar, 350mbar, 400mbar, 450mbar, or 500mb ar, and the like; forming nitrogen of the first typeThe compound contact layer 206 may be doped with magnesium, but not limited to magnesium, and in the embodiment of magnesium doping, the doping concentration of magnesium may be 1 × 10 ²⁰ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ²⁰ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、3×10 ²⁰ cm ^-3 、4.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

Referring to fig. 6 in conjunction with fig. 1, in one embodiment, the preparation method may further include the following steps:

s3: the first type nitride contact layer 206, the second P-type nitride layer 235, the P-type nitride electron blocking layer 225, the first P-type nitride layer 215, the light emitting layer 204 and the second type nitride layer 203 are etched to form a recess 30, as shown in fig. 6, wherein the recess 30 penetrates through the first type nitride contact layer 206, the second P-type nitride layer 235, the P-type nitride electron blocking layer 225, the first P-type nitride layer 215 and the light emitting layer 204, extends into the second type nitride layer 203, and exposes a portion of the second type nitride layer 203.

It should be noted that, in the present application, there is no sequential limitation in the steps S4 and S3, that is, either one of the steps performed before or simultaneously is allowed; the execution sequence of steps S4 and S3 can be adjusted according to actual requirements.

In one embodiment, step S3 is performed to etch the first type nitride contact layer 206, the second P-type nitride layer 235, the P-type nitride electron-blocking layer 225, the first P-type nitride layer 215, the light-emitting layer 204 and the second type nitride layer 203 to form the recess 30; then, etching to remove part of the first type nitride contact material layer 216, and the remaining first type nitride contact material layer 216 is the first type nitride contact layer 206; the manner of removing portions of the first type of nitride contact material layer 216 has been described in some of the embodiments above and will not be further described herein.

Referring to step S4, referring to fig. 10 in combination with S4 shown in fig. 1, a transparent conductive layer 40 is formed on a side of the first-type nitride stack 205 facing away from the light-emitting layer 204, and the transparent conductive layer 40 also covers at least a portion of a surface of the first-type nitride contact layer 206 facing away from the first-type nitride stack 205.

The material of the transparent conductive layer 40 is not particularly limited, and in one embodiment, the transparent conductive layer 40 includes an Indium Tin Oxide (ITO) thin film layer; the thickness of the transparent conductive layer 40 is not limited in the present application, and in one embodiment, the thickness of the transparent conductive layer 40 is 50nm to 250nm, for example, the thickness of the transparent conductive layer 40 may be 50nm, 100nm, 150nm, 200nm, or 250nm, etc. The indium tin oxide has excellent photoelectric performance and higher carrier concentration, and the resistance of the indium tin oxide thin film layer can reach 10 ^-4 Ω·cm。

Referring to fig. 11 in conjunction with fig. 1, in one embodiment, the preparation method may further include the following steps:

s5: forming an opening 501 in the transparent conductive layer 40, wherein the opening 501 exposes a portion of the first type nitride contact layer 206, and forming a P-electrode 502 in the opening 501;

s6: an N-electrode 601 is formed on the surface of the second-type nitride layer 203 exposed by the recess 30.

The material and thickness of the P electrode 502 and the N electrode 601 are not specifically limited in the present application; the P-electrode 502 and the N-electrode 601 may each be a single-layer electrode including a chromium (Cr) layer, an aluminum (Al) layer, a gold (Au) layer, a platinum (Pt) layer, a palladium (Pd) layer, a titanium (Ti) layer, a tantalum (Ta) layer, or a nickel (Ni) layer, or may be a multilayer electrode including at least two layers of a chromium layer, an aluminum layer, a gold layer, a platinum layer, a palladium layer, a titanium layer, a tantalum layer, and a nickel layer. In one embodiment, the P-electrode 502 comprises a nickel/gold P-type electrode, i.e., the P-electrode 502 comprises stacked nickel and gold layers, wherein the nickel layer may have a thickness of 8nm to 12nm, such as 8nm, 10nm, 12nm, etc., and the gold layer may have a thickness of 100nm to 300nm, such as 100nm, 150nm, 200nm, 250nm, 300nm, etc.; in one embodiment, the N-electrode 601 includes a ti/al/ti/au N-type electrode, that is, the N-electrode 601 includes a first ti layer, an al layer, a second ti layer and a au layer stacked in sequence, wherein the first ti layer may have a thickness of 11nm to 17nm, such as 11nm, 13nm, 15nm, 17nm or 19nm, etc., the al layer may have a thickness of 21nm to 29nm, such as 21nm, 23nm, 25nm, 27nm or 29nm, etc., the second ti layer may have a thickness of 51nm to 59nm, such as 51nm, 53nm, 55nm, 57nm or 59nm, etc., the au layer may have a thickness of 100nm to 300nm, such as 100nm, 150nm, 200nm, 250nm or 300nm, etc.

It should be understood that the above data are only examples, and the thickness of the material of the P-electrode 502 and the N-electrode 601 is not limited by the above data in the practical embodiment.

Since the N-electrode 601 is generally to be in contact with the underlying grown second type nitride layer 203, the second type nitride layer 203 needs to be exposed by means of etching, and thus the N-electrode 601 is located lower than the P-electrode 502, which forms a relatively low mesa.

With continued reference to fig. 11, in one embodiment, the P electrode 502 further covers a portion of the transparent conductive layer 40.

It should be understood that, although the steps in the flowcharts of fig. 1, 2, 4 and 5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1, 2, 4, and 5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least some of the other steps.

With continued reference to fig. 11, the present application further provides a nitride light emitting diode according to some embodiments, which may include a substrate 10, an epitaxial structure 20, and a transparent conductive layer 40.

Specifically, the epitaxial structure 20 is located on the surface of the substrate 10. The epitaxial structure 20 may include a light emitting layer 204, a first-type nitride stack 205, and a first-type nitride contact layer 206; wherein the first type nitride stack 205 is located on a surface of the light-emitting layer 204 facing away from the substrate 10; a first-type nitride contact layer 206 is located at a surface of the first-type nitride stack 205 facing away from the light-emitting layer 204; the orthographic projection of the first-type nitride contact layer 206 on the surface of the first-type nitride stack 205 facing away from the light-emitting layer 204 is located within the surface of the first-type nitride stack 205, and the edge of the first-type nitride contact layer 206 is spaced from the edge of the first-type nitride stack 205. The transparent conductive layer 40 is located on the side of the first-type nitride stack 205 facing away from the light-emitting layer 204 and covers a portion of the surface of the first-type nitride contact layer 206 facing away from the first-type nitride stack 205.

The first type nitride contact layer 206 in the nitride light emitting diode provided by the above embodiment can form a good ohmic contact with the transparent conductive layer 40, so that ohmic contact resistance is reduced, and the operating voltage of the nitride light emitting diode is reduced; meanwhile, the orthographic projection of the first-type nitride contact layer 206 on the surface of the first-type nitride lamination layer 205, which is away from the light-emitting layer 204, is located in the surface of the first-type nitride lamination layer 205, that is, the contact area between the first-type nitride contact layer 206 and the first-type nitride lamination layer 205 is small, so that the absorption of the first-type nitride contact layer 206 on the light emitted by the nitride light-emitting diode can be reduced, and the light-emitting efficiency of the device can be improved.

In the nitride light emitting diode to which the present application relates, the substrate 10 may include, but is not limited to, any one or more of a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, a gallium nitride substrate, or the like.

In the nitride light emitting diode to which the present application relates, the light emitting layer 204 may include, but is not limited to, pairs of nitride quantum wells; in one embodiment, the nitride quantum well may include an indium gallium nitride (InGaN)/gallium nitride (GaN) quantum well structure including an indium gallium nitride (InGaN) quantum well and a gallium nitride (GaN) quantum barrier; the present application does not specifically limit the number of pairs of the gan in/gan quantum well structures in the light emitting layer 204, and in some examples, the light emitting layer 204 may include 3 to 20 pairs of nitride quantum wells, for example, the light emitting layer 204 may include 3, 5, 10, 15, or 20 pairs of nitride quantum wells.

In one embodiment, the light emitting layer 204 includes 10 pairs of indium gallium nitride/gallium nitride quantum well structures; the thicknesses of the gan-in quantum well and the gan quantum barrier are not particularly limited in the present application, and in one embodiment, the thickness of the gan-in quantum well is 2nm to 8nm, for example, the thickness of the gan-in quantum well may be 2nm, 3nm, 4nm, 6nm, or 8nm, etc.; the thickness of the gan quantum barrier is not limited in any way, and in one embodiment, the thickness of the gan quantum barrier is 3nm to 20nm, for example, the thickness of the gan quantum barrier may be 3nm, 7nm, 11nm, 15nm or 20 nm; the present application is not limited to the process for forming the light-emitting layer 204; the gallium source required to grow the light-emitting layer 204 may be from, but is not limited to, triethylgallium (TEGa), and the indium source required may be from, but is not limited to, trimethylindium (TMIn); the growth atmosphere may include, but is not limited to, nitrogen (N) ₂ ) An atmosphere; specifically, the growth temperature of the gallium indium nitride quantum well may be 750 ℃ to 950 ℃, for example, the growth temperature of the gallium indium nitride quantum well may be 750 ℃, 800 ℃, 850 ℃, 900 ℃ or 950 ℃, and the like; the growth pressure of the gallium indium nitride quantum well can be 200 mbar-400 mbar, for example, the growth pressure of the gallium indium nitride quantum well can be 200mbar, 250mbar, 300mbar, 350mbar or 400mbar, etc.; the growth temperature of the gallium nitride quantum barrier can be 850-1050 ℃, for example, the growth temperature can be 850 ℃, 900 ℃, 950 ℃, 1000 ℃ or 1050 ℃ and the like; the growth pressure may be 300mbar to 500mbar, for example, the growth pressure may be 300mbar, 350mbar, 400mbar, 450mbar, or 500mbar, and so forth.

In the nitride light emitting diode to which the present application relates, the first type nitride contact layer 206 may include, but is not limited to, a P-type nitride contact layer; in one embodiment, the first type nitride contact layer 206 comprises P-type nitrideAn indium gallium layer; the thickness of the first type nitride contact layer 206 is not particularly limited, and in one embodiment, the thickness of the first type nitride contact layer 206 is 1nm to 10nm, for example, the thickness of the first type nitride contact layer 206 may be 1nm, 2.5nm, 5nm, 7.5nm, 10nm, or the like; the process for forming the first type nitride contact layer 206 is not particularly limited, the gallium source required for growing the first type nitride contact layer 206 may be from, but is not limited to, trimethylgallium, and the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature can be 680 ℃ to 880 ℃, for example, the growth temperature can be 680 ℃, 730 ℃, 780 ℃, 830 ℃ or 880 ℃, and the like; the growth pressure can be 300mbar to 500mbar, for example, the growth pressure can be 300mbar, 350mbar, 400mbar, 450mbar, or 500mbar, and so on; the first type nitride contact layer 206 may be formed by, but not limited to, mg doping, and in an embodiment using mg doping, the mg doping concentration may be 1 × 10 ²⁰ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ²⁰ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、3×10 ²⁰ cm ^-3 、4.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

Meanwhile, in the nitride light emitting diode to which the present application relates, the transparent conductive layer 40 may include, but is not limited to, an Indium Tin Oxide (ITO) thin film layer; the thickness of the transparent conductive layer 40 is not limited in the present application, and in one embodiment, the thickness of the transparent conductive layer 40 is 50nm to 250nm, for example, the thickness of the transparent conductive layer 40 may be 50nm, 100nm, 150nm, 200nm, or 250nm, etc. The indium tin oxide has excellent photoelectric performance and higher carrier concentration, and the resistance of the indium tin oxide thin film layer can reach 10 ^-4 Ω·cm。

Continuing to refer to fig. 11, in one embodiment, first type nitride stack 205 may include a first P-type nitride layer 215, a P-type nitride electron blocking layer 225, and a second P-type nitride layer 235.

Specifically, the first P-type nitride layer 215 is located on the surface of the light-emitting layer 204 facing away from the substrate 10; a P-type nitride electron blocking layer 225 is positioned on the surface of the first P-type nitride layer 215 facing away from the light-emitting layer 204; second P-type nitride layer 235 is located on the surface of P-type nitride electron blocking layer 225 facing away from first P-type nitride layer 215.

In the nitride light emitting diode to which the present application relates, the first P-type nitride layer 215 may include, but is not limited to, a low temperature P-type nitride layer; in one embodiment, the first P-type nitride layer 215 comprises a P-type gallium nitride layer; the thickness of the first P-type nitride layer 215 is not particularly limited, and in one embodiment, the thickness of the first P-type semiconductor layer 205 is 15nm to 100nm, for example, the thickness of the first P-type nitride layer 215 may be 15nm, 35nm, 50nm, 75nm, 100nm, or the like; the process for forming the first P-type nitride layer 215 is not particularly limited; the gallium source required to grow the first P-type nitride layer 215 may be from, but is not limited to, trimethyl gallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature may be 820 ℃ to 1020 ℃, for example, the growth temperature may be 820 ℃, 870 ℃, 920 ℃, 970 ℃, or 1020 ℃ and the like; magnesium (Mg) doping may be used in the process of forming the first P-type nitride layer 215, but is not limited thereto, and in the embodiment of magnesium doping, the doping concentration of Mg may be 1 × 10 ¹⁹ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、2×10 ¹⁹ cm ^-3 、2.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

In the nitride light emitting diode to which the present application relates, the P-type nitride electron blocking layer 225 may include, but is not limited to, a low temperature P-type nitride electron blocking layer; in one embodiment, the P-type nitride electron blocking layer 225 comprises a P-type doped aluminum gallium nitride (AlGaN) layer; the thickness of the P-type nitride electron blocking layer 225 is not particularly limited, but in one embodiment, the thickness of the P-type nitride electron blocking layer 225 is 15nm to 100nm, for example, the thickness of the P-type nitride electron blocking layer 225 may be 15nm, 25nm, 50nm, 75nm or more100nm, etc.; the process for forming the P-type nitride electron blocking layer 225 is not specifically limited in the present application, the gallium source required for growing the P-type nitride electron blocking layer 225 may be from, but is not limited to, trimethyl gallium, the required aluminum source may be from trimethyl aluminum (TMAl), and the growth atmosphere may include, but is not limited to, a nitrogen atmosphere; the growth temperature may be 900 ℃ to 1100 ℃, for example, the growth temperature may be 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, or the like; the growth pressure may be 50mbar to 250mbar, for example, the growth pressure may be 50mbar, 100mbar, 150mbar, 200mbar, or 250mbar, and so on; magnesium (Mg) doping may be used in the process of forming the P-type nitride electron blocking layer 225, but is not limited thereto, and in the embodiment using Mg doping, the Mg doping concentration may be 1 × 10 ¹⁹ cm ^-3 ～5×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、1.5×10 ¹⁹ cm ^-3 、2×10 ¹⁹ cm ^-3 、2.5×10 ²⁰ cm ^-3 Or 5X 10 ²⁰ cm ^-3 And so on.

In the nitride light emitting diode to which the present application relates, the second P-type nitride layer 235 may include, but is not limited to, a P-type gallium nitride layer; in one embodiment, the second P-type nitride layer 235 comprises a P-type gallium nitride layer; the thickness of the second P-type nitride layer 235 is not particularly limited, and in one embodiment, the thickness of the second P-type nitride layer 235 is 50nm to 200nm, for example, the thickness of the second P-type nitride layer 235 may be 50nm, 80nm, 120nm, 150nm, 200nm, or the like; the process for forming the second P-type nitride layer 235 is not particularly limited, the gallium source required for growing the second P-type nitride layer 235 may be from, but not limited to, trimethyl gallium, and the growth atmosphere may include, but not limited to, a hydrogen atmosphere; the growth temperature may be 1040 ℃ to 1160 ℃, for example, the growth temperature may be 1040 ℃, 1070 ℃, 1100 ℃, 1130 ℃, 1160 ℃, or the like; the growth pressure may be 400mbar to 600mbar, for example, the growth pressure may be 400mbar, 450mbar, 500mbar, 550mbar, 600mbar, or the like; the second P-type nitride layer 235 may be formed by, but not limited to, Mg dopingIn the embodiment doped with magnesium, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 ～1×10 ²⁰ cm ^-3 For example, the doping concentration of magnesium may be 1 × 10 ¹⁹ cm ^-3 、2.5×10 ¹⁹ cm ^-3 、5×10 ¹⁹ cm ^-3 、7.5×10 ¹⁹ cm ^-3 Or 1X 10 ²⁰ cm ^-3 And so on.

With continued reference to fig. 11, in one embodiment, the epitaxial structure 20 may further include a nitride buffer layer 201, an undoped nitride layer 202, and a second-type nitride layer 203.

Specifically, the nitride buffer layer 201 is located on the surface of the substrate 10; the undoped nitride layer 202 is positioned on the surface of the nitride buffer layer 201 facing away from the substrate 10; the second-type nitride layer 203 is located on a surface of the undoped nitride layer 202 facing away from the nitride buffer layer 201.

On the basis of the above embodiment, the light emitting layer 204 is located on the surface of the second type nitride layer 203 facing away from the undoped nitride layer 202.

In the nitride light emitting diode to which the present application relates, the nitride buffer layer 201 may include, but is not limited to, a low temperature nitride buffer layer; in one embodiment, the nitride buffer layer 201 includes an undoped gallium nitride buffer layer; the thickness of the nitride buffer layer 201 is not particularly limited, and in one embodiment, the thickness of the nitride buffer layer 201 is 20nm to 60nm, for example, the thickness of the nitride buffer layer 201 may be 20nm, 25nm, 35nm, 45nm, 60nm, or the like; the process for forming the buffer layer 201 is not particularly limited in this application; the gallium (Ga) source required to grow buffer layer 201 may be from, but is not limited to, Trimethylgallium (TMG); the growth atmosphere may include, but is not limited to, hydrogen (H) ₂ ) An atmosphere; the growth temperature may be 500 ℃ to 700 ℃, for example, the growth temperature may be 500 ℃, 550 ℃, 600 ℃, 650 ℃, 700 ℃, or the like; the growth pressure may be 550mbar to 750mbar, for example, the growth pressure may be 550mbar, 600mbar, 650mbar, 700mbar, or 750mbar, and so on.

In the nitride light emitting diode to which the present application relates, the undoped nitride layer 202 may include, but is not limited to, an undoped gallium nitride layer; in one embodiment, the undoped nitride layer 202 comprises an undoped gallium nitride layer; the thickness of the undoped nitride layer 202 is not particularly limited, and in one embodiment, the thickness of the undoped nitride layer 202 is 1 μm to 3 μm, for example, the thickness of the undoped nitride layer 202 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm, etc.; the present application is not limited to the process of forming the undoped nitride layer 202; the gallium source required to grow the undoped nitride layer 202 may be from, but is not limited to, trimethylgallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature may be 1115 to 1315 deg.C, for example, the growth temperature may be 1115, 1165, 1215, 1265, 1315 deg.C, etc.; the growth pressure may be 200mbar to 400mbar, for example, the growth pressure may be 200mbar, 250mbar, 300mbar, 350mbar, or 400mbar, and so forth.

In the nitride light emitting diode to which the present application relates, the second type nitride layer 203 may include, but is not limited to, an N-type nitride layer; in one embodiment, the second-type nitride layer 203 comprises an N-type gallium nitride layer; the thickness of the second type nitride layer 203 is not particularly limited, and in one embodiment, the thickness of the second type nitride layer 203 is 1 μm to 3 μm, for example, the thickness of the second type nitride layer 203 may be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, or the like; the process for forming the second type nitride layer 203 is not particularly limited; the second type nitride layer 203 may be formed by, but not limited to, doping silicon, and in the embodiment of doping silicon, the doping concentration of silicon may be 1 × 10 ¹⁸ cm ^-3 ～1×10 ²⁰ cm ^-3 For example, the doping concentration of silicon may be 1 × 10 ¹⁸ cm ^-3 、2.5×10 ¹⁸ cm ^-3 、5×10 ¹⁸ cm ^-3 、1×10 ¹⁹ cm ^-3 Or 1X 10 ²⁰ cm ^-3 And the like; the gallium source required to grow the second-type nitride layer 203 may be from, but is not limited to, trimethylgallium; the growth atmosphere may include, but is not limited to, a hydrogen atmosphere; the growth temperature can be 1110-131 DEG0 deg.C, for example, the growth temperature can be 1110 deg.C, 1160 deg.C, 1210 deg.C, 1260 deg.C, 1310 deg.C, etc.; the growth pressure may be 50mbar to 250mbar, for example, the growth pressure may be 50mbar, 100mbar, 150mbar, 200mbar, or 250mbar, and so on.

With continued reference to fig. 11, the epitaxial structure 20 further has a recess 30 therein, the recess 30 penetrating the first type nitride contact layer 206, the second P-type nitride layer 235, the P-type nitride electron blocking layer 225, the first P-type nitride layer 215 and the light emitting layer 204 and extending into the second type nitride layer 203 to expose a portion of the second type nitride layer 203; in addition to the above embodiments, the nitride light emitting diode further includes a P electrode 502 and an N electrode 601.

Specifically, the P-electrode 502 is located on the surface of the transparent conductive layer 40 facing away from the first-type nitride stack 205; the N-electrode 601 is located on the surface of the second-type nitride layer 203 exposed by the recess 30.

In the nitride light emitting diode related to the present application, the materials and thicknesses of the P electrode 502 and the N electrode 601 are not particularly limited; the P-electrode 502 and the N-electrode 601 may each be a single-layer electrode including a chromium (Cr) layer, an aluminum (Al) layer, a gold (Au) layer, a platinum (Pt) layer, a palladium (Pd) layer, a titanium (Ti) layer, a tantalum (Ta) layer, or a nickel (Ni) layer, or may be a multilayer electrode including at least two layers of a chromium layer, an aluminum layer, a gold layer, a platinum layer, a palladium layer, a titanium layer, a tantalum layer, and a nickel layer. In one embodiment, the P-electrode 502 comprises a nickel/gold P-type electrode, i.e., the P-electrode 502 comprises stacked nickel and gold layers, wherein the nickel layer may have a thickness of 8nm to 12nm, such as 8nm, 10nm, 12nm, etc., and the gold layer may have a thickness of 100nm to 300nm, such as 100nm, 150nm, 200nm, 250nm, 300nm, etc.; in one embodiment, the N-electrode 601 includes a ti/al/ti/au N-type electrode, that is, the N-electrode 601 includes a first ti layer, an al layer, a second ti layer and a au layer stacked in sequence, wherein the first ti layer may have a thickness of 11nm to 17nm, such as 11nm, 13nm, 15nm, 17nm or 19nm, etc., the al layer may have a thickness of 21nm to 29nm, such as 21nm, 23nm, 25nm, 27nm or 29nm, etc., the second ti layer may have a thickness of 51nm to 59nm, such as 51nm, 53nm, 55nm, 57nm or 59nm, etc., the au layer may have a thickness of 100nm to 300nm, such as 100nm, 150nm, 200nm, 250nm or 300nm, etc.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. The nitride light-emitting diode is characterized by comprising a substrate and an epitaxial structure positioned on the surface of the substrate;

the epitaxial structure comprises a light emitting layer, a first type nitride lamination layer and a first type nitride contact layer; wherein the first type nitride stack layer is located on a surface of the light emitting layer facing away from the substrate; the first type nitride contact layer is positioned on the surface of the first type nitride lamination layer, which faces away from the light-emitting layer; the orthographic projection of the first type nitride contact layer on the surface of the first type nitride lamination layer, which faces away from the light-emitting layer, is positioned in the surface of the first type nitride lamination layer, and the edge of the first type nitride contact layer is spaced from the edge of the first type nitride lamination layer;

the nitride light emitting diode further includes:

2. The nitride light-emitting diode according to claim 1, wherein the substrate comprises a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, a gallium oxide substrate, or a gallium nitride substrate.

3. The nitride light emitting diode of claim 1, wherein the transparent conductive layer comprises an indium tin oxide thin film layer.

4. The nitride light emitting diode according to claim 3, wherein the thickness of the transparent conductive layer is 50nm to 250 nm.

5. The nitride light emitting diode of claim 1, wherein the first type of nitride stack comprises:

6. The nitride light emitting diode of claim 5, wherein the epitaxial structure further comprises:

the nitride buffer layer is positioned on the surface of the substrate;

7. The nitride light emitting diode of claim 6, wherein the nitride buffer layer comprises an undoped gallium nitride buffer layer; the undoped nitride layer comprises an undoped gallium nitride layer; the second type nitride layer comprises an N type gallium nitride layer; the light emitting layer includes a plurality of pairs of nitride quantum wells; the first P-type nitride layer comprises a P-type gallium nitride layer; the P-type nitride electronic barrier layer comprises a P-type doped aluminum gallium nitride layer; the second P-type nitride layer comprises a P-type gallium nitride layer; the first type nitride contact layer includes a P-type indium gallium nitride layer.

8. The nitride light emitting diode according to claim 7, wherein the nitride buffer layer has a thickness of 20nm to 60 nm; the thickness of the non-doped nitride layer is 1-3 mu m; the thickness of the second type nitride layer is 1-3 mu m; the thickness of the first P-type nitride layer is 15 nm-100 nm; the thickness of the P-type nitride electron blocking layer is 15 nm-100 nm; the thickness of the second P-type nitride layer is 50 nm-200 nm; the thickness of the first type nitride contact layer is 1 nm-10 nm.

9. The nitride light emitting diode of claim 6, wherein the epitaxial structure further has a recess therein, the recess extending through the first type nitride contact layer, the second P-type nitride layer, the P-type nitride electron blocking layer, the first P-type nitride layer, and the light emitting layer and into the second type nitride layer to expose a portion of the second type nitride layer; the nitride light emitting diode further includes:

10. The nitride light emitting diode of claim 9, wherein the P-electrode comprises a nickel/gold P-type electrode; the N electrode comprises a titanium/aluminum/titanium/gold N-type electrode.