CN114242742A - Method for manufacturing CMOS image sensor - Google Patents
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- CN114242742A CN114242742A CN202111541258.9A CN202111541258A CN114242742A CN 114242742 A CN114242742 A CN 114242742A CN 202111541258 A CN202111541258 A CN 202111541258A CN 114242742 A CN114242742 A CN 114242742A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
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- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 23
- 239000007924 injection Substances 0.000 claims abstract description 23
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
Abstract
The invention discloses a manufacturing method of a CMOS image sensor, which comprises the following steps: step one, forming a side wall on the side surface of the grid structure, comprising: depositing a first dielectric layer; performing a side wall etching process on the first dielectric layer, and forming side walls by self-aligning the first dielectric layers reserved on the side surfaces of the gate structures; a first dielectric layer with a first thickness is reserved outside the side wall; performing second conductive type heavily doped ion implantation in a forming region of the photodiode to form an acupuncture layer, wherein the ion implantation of the acupuncture layer can penetrate through the first dielectric layer, and the ion implantation of the acupuncture layer is prevented from damaging the surface of the semiconductor substrate by utilizing the first thickness; step three, performing a cleaning process after side wall etching, wherein the first dielectric layer generates loss and is reduced to a second thickness; and fourthly, performing source-drain injection to form corresponding source-drain regions. The invention can reduce the white point of the CMOS image sensor, and simultaneously does not influence the source-drain injection process and increase the process cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a CMOS image sensor.
Background
The existing CMOS Image Sensor (CIS) is composed of a Pixel unit circuit and a CMOS logic circuit, and has a better integratability because of adopting a CMOS standard manufacturing process compared with a CCD Image Sensor, and can be integrated with other digital-to-analog operation and control circuits on the same chip, thereby being more suitable for future development.
The conventional CMOS image sensor is mainly classified into a 3T structure and a 4T structure according to the number of transistors included in a pixel unit circuit.
As shown in fig. 1, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 3T-type CMOS image sensor; the pixel cell circuit of the conventional 3T-type CMOS image sensor includes a photodiode D1 and a CMOS pixel readout circuit. The CMOS pixel reading circuit is a 3T-type pixel circuit and comprises a reset tube M1, an amplifying tube M2 and a selecting tube M3 which are all NMOS tubes.
The N-type region of the photosensitive diode D1 is connected with the source electrode of the reset tube M1.
The gate of the Reset tube M1 is connected to a Reset signal Reset, the Reset signal Reset is a potential pulse, and when the Reset signal Reset is at a high level, the Reset tube M1 is turned on and absorbs electrons of the photodiode D1 into the power supply Vdd of the readout circuit to realize Reset. When light irradiates, the photosensitive diode D1 generates photo-generated electrons, the potential rises, and an electric signal is transmitted out through an amplifying circuit. The gate of the selection transistor M3 is connected to a row selection signal Rs for selecting the amplified electrical signal to be output, i.e., the output signal Vout.
As shown in fig. 2, it is an equivalent circuit schematic diagram of a pixel unit circuit of a conventional 4T-type CMOS image sensor; the difference from the structure shown in fig. 1 is that a transfer transistor or transfer transistor M4 is added in the structure shown in fig. 2, the source region of the transfer transistor 4 is an N-type region connected to the photodiode D1, the drain region of the transfer transistor 4 is a Floating active region (Floating Diffusion, FD), and the gate of the transfer transistor 4 is connected to a transfer control signal Tx. After photo-generated electrons are generated by the photodiode D1, the photo-generated electrons are transferred to the floating active region through the transfer transistor 4, and then the floating active region is connected to the gate of the amplifying tube M2 to amplify signals.
Generally, the photodiode D1 is an N-type Pinned Photodiode (PPD), NPPD; the NPPD mainly comprises a PN junction diode formed between an N-type injection region and a P-type semiconductor substrate at the bottom of the N-type injection region, and a P + layer serving as a pinpoint layer, namely a clamping layer, is formed on the surface of the N-type injection region to realize a pinpoint photodiode structure; the N-type injection region stores photo-generated electrons after the photosensitive diode is sensitive to light.
White spots (white points), i.e., white pixel points, of a CMOS image sensor are very sensitive to the integrity of the semiconductor substrate surface, e.g., silicon surface, of the photodiode, and defects on the surface of the photodiode easily cause white spots.
The pinning layer in the CMOS image sensor is usually formed by high-current ion implantation, and the ion implantation of the existing pinning layer is placed after the source and drain implantation of MOS transistors such as NMOS and PMOS in the process flow, which is briefly described as follows:
firstly, completing the process before the gate structure, and then forming the gate structure.
And then, forming a side wall on the side surface of the grid structure. The forming of the side wall mainly comprises the steps of depositing a side wall dielectric layer, defining by photoetching, and etching (spacer Etch) the side wall dielectric layer to form the side wall in a self-alignment mode on the side face of the grid structure.
After the etching process of the sidewall is completed, a certain amount of sidewall dielectric layer, such as an oxide layer, is usually left on the surface of the semiconductor substrate outside the sidewall.
Followed by a photoresist wet removal (PR WET STRIP-S) process. The photoresist wet removal process generates certain loss on the residual side wall dielectric layer on the surface of the semiconductor substrate, so that the thickness of the side wall dielectric layer remained outside the side wall is about the same
The thickness is not very beneficial to source-drain implantation, because the thickness of the side wall dielectric layer is thick, the source-drain implantation effect is poor, the doping of the source-drain region is insufficient, and the requirements on junction depth and doping concentration are not easily met.
Then, a POST-side-wall-etching cleaning (POST SPACER ET CLEAN) process is required, and the POST-side-wall-etching cleaning process can further generate loss on the side wall dielectric layer outside the side wall, so that the thickness of the side wall dielectric layer reaches the thickness of the side wall dielectric layer
The following; this thickness is also beneficial for source drain implantation.
And then carrying out source-drain injection. The source and drain implants include N + source and drain implants (NPLUS) and P + source and drain implants (PPLUS).
Then, a photolithography process (PPD _ PH) for opening a formation region of the photodiode is performed, and then a P + implantation is performed according to a photolithography definition to form a pinning layer. Because the beam current of the ion implantation of the needling layer is large (high current), Si on the surface of the photodiode forming area is easily damaged when the needling layer penetrates through the side wall dielectric layer with small thickness, so that dark current is easily generated and white spots are formed.
Disclosure of Invention
The invention aims to provide a manufacturing method of a CMOS image sensor, which can improve the white point problem of CIS imaging.
In order to solve the above technical problem, the method for manufacturing a CMOS image sensor according to the present invention includes the steps of:
providing a semiconductor substrate with a grid structure of an MOS transistor, wherein the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped; forming a side wall on the side surface of the gate structure, including: depositing a first dielectric layer, carrying out a side wall etching process on the first dielectric layer, and forming the side wall by self-aligning the first dielectric layer which is remained on the side surface of each grid structure after the side wall etching process.
And the first dielectric layer with the first thickness is remained on the surface of the semiconductor substrate outside the side wall after the side wall etching process.
And secondly, performing second conductive type heavily doped ion implantation in a forming area of the photodiode to form an acupuncture layer, wherein the ion implantation of the acupuncture layer can penetrate through the first dielectric layer, and the first thickness of the first dielectric layer is utilized to prevent the ion implantation of the acupuncture layer from damaging the surface of the semiconductor substrate, so that white spots of the CMOS image sensor are reduced.
And step three, performing a side wall etching post-cleaning process, wherein the side wall etching post-cleaning process can generate loss on the first dielectric layer and reduce the first dielectric layer reserved on the surface of the semiconductor substrate outside the side wall to a second thickness.
And fourthly, performing source-drain injection in the formation region of each MOS transistor to form a corresponding source-drain region, wherein the source-drain injection can penetrate through the first dielectric layer, and the doping of the source-drain region is optimized by reducing the thickness of the first dielectric layer to a second thickness.
In the first step, after the first dielectric layer is deposited and before the sidewall etching process, a first photoresist pattern is formed by a first photolithography process to define a region where the sidewall is to be formed.
And after the side wall etching process, performing a photoresist wet stripping process, wherein the photoresist wet stripping process can cause loss of the first dielectric layer, and the first thickness is the thickness of the first dielectric layer reserved on the surface of the semiconductor substrate outside the side wall after the photoresist wet stripping process.
In the first step, the first dielectric layer is an oxide layer, or a stacked layer of an oxide layer and a nitride layer, or a stacked layer of an oxide layer, a nitride layer and an oxide layer.
In the first step, the first dielectric layer on the surface of the semiconductor substrate, which is remained outside the side wall after the side wall etching process, is an oxide layer.
In a further refinement, the first thickness is
In a further refinement, the second thickness is less than
In a further improvement, the CMOS image sensor comprises a pixel area and a logic area;
the pixel region comprises a plurality of pixel unit circuits, and the pixel unit circuits comprise the photosensitive diodes and a plurality of MOS transistors.
A further improvement is that, when the pixel unit circuit is of a 3T-type structure, the pixel unit circuit includes 3 MOS transistors, which are: reset tube, amplifier tube and selection tube.
A further improvement is that, when the pixel unit circuit is of a 4T-type structure, the pixel unit circuit includes 4 MOS transistors, which are respectively: reset tube, amplifier tube, selection tube and transmission tube.
In a further improvement, MOS transistors in the pixel unit circuit are all NMOS;
the MOS transistors in the logic region include NMOS and PMOS.
The further improvement is that the semiconductor substrate is doped in a P type;
before forming the side wall, the method further comprises the step of forming a first N-type region in a forming region of the photosensitive diode, wherein a PN junction formed by the first N-type region and the P-type semiconductor substrate is used as the photosensitive diode;
and in the second step, the second conductive type doping of the needle layer is P-type doping, and the needle layer is formed on the surface of the first N-type region.
In a further improvement, the P-type ion implantation impurities of the pinning layer include boron.
In a further improvement, a first P-type doped epitaxial layer is further formed on the surface of the semiconductor substrate, and the first N-type region is formed in the first epitaxial layer.
The further improvement is that in the fourth step, the source drain injection of the NMOS is N-type source drain injection;
and the source and drain injection of the PMOS is P-type source and drain injection.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
The invention adjusts the ion implantation of the acupuncture layer in the process, the ion implantation of the acupuncture layer in the prior art is placed after the source drain implantation, and the ion implantation of the acupuncture layer in the invention is placed before the source drain implantation and after the side wall etching post-cleaning process, so that the thickness loss of the side wall etching post-cleaning process to the side wall dielectric layer outside the side wall, namely the first dielectric layer can be placed, the ion implantation of the acupuncture layer can penetrate through the thicker first dielectric layer, namely the first thickness, thereby preventing the ion implantation of the acupuncture layer from damaging the semiconductor substrate such as the silicon surface, and further improving the white point problem of CIS imaging due to the surface damage of the photosensitive diode; meanwhile, the invention can be realized only by changing the process sequence of the manufacturing steps, so that the extra cost is not increased, and the invention also has the advantage of low process cost if the extra photoetching process or the deposition process of the dielectric film layer is not required to be increased.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is an equivalent circuit configuration diagram of a pixel unit circuit of a conventional CMOS image sensor of 3T type configuration;
fig. 2 is an equivalent circuit configuration diagram of a pixel unit circuit of a conventional CMOS image sensor of 4T type configuration;
FIG. 3 is a flow chart of a method of fabricating a CMOS image sensor in accordance with an embodiment of the present invention;
fig. 4A to 4G are cross-sectional views of devices in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention.
Detailed Description
Fig. 3 is a flow chart showing a method for manufacturing a CMOS image sensor according to an embodiment of the present invention; fig. 4A to 4G are cross-sectional views of devices in steps of a method for manufacturing a CMOS image sensor according to an embodiment of the present invention; the manufacturing method of the CMOS image sensor comprises the following steps:
step one, as shown in fig. 4A, providing a semiconductor substrate 101 formed with a gate structure of a MOS transistor, where the gate structure includes a gate dielectric layer 103 and a gate conductive material layer 104 which are sequentially stacked.
In the embodiment of the present invention, the CMOS image sensor includes a pixel region 201 and a logic region 202.
The pixel region 201 includes therein a plurality of pixel unit circuits including the photodiode D101 and a plurality of MOS transistors.
When the pixel unit circuit is of a 3T type structure, the pixel unit circuit comprises 3 MOS transistors which are respectively as follows: reset tube, amplifier tube and selection tube.
When the pixel unit circuit is of a 4T-type structure, the pixel unit circuit comprises 4 MOS transistors, which are respectively as follows: reset tube, amplifier tube, selection tube and transmission tube.
In fig. 4A, each MOS transistor in the pixel region 201 is represented by one MOS transistor M101. The MOS transistor M101 shown in FIG. 4A is adjacent to the photodiode D101, typically a pass transistor.
In fig. 4A, each MOS transistor in the logic region 202 is represented by a MOS transistor M102.
In some embodiments, the MOS transistors in the pixel cell circuit are all NMOS;
the MOS transistors in the logic region 202 include NMOS and PMOS.
The semiconductor substrate 101 is doped P-type.
The semiconductor substrate 101 includes a silicon substrate.
In some embodiments, before forming the side walls 105, a step of forming a first N-type region 102 in a formation region of the photodiode D101 is further included, and a PN junction formed by the first N-type region 102 and the P-type semiconductor substrate 101 is used as the photodiode D101;
in some embodiments, a P-type doped first epitaxial layer is further formed on the surface of the semiconductor substrate 101, and the first N-type region 102 is formed in the first epitaxial layer.
In some embodiments, the first N-type region 102 can be formed by an ion implantation process. In other embodiments, the first N-type region 102 can also be formed by forming a trench in the first epitaxial layer and then filling the trench with an N-type epitaxial layer.
In some embodiments, an isolation structure such as an isolation structure composed of a P-well is also formed on the periphery of the first N-type region 102.
As shown in fig. 4B, a sidewall spacer 105 is then formed on the side of the gate structure, including:
depositing a first dielectric layer, performing a side wall etching process on the first dielectric layer, and forming the side wall 105 by self-aligning the first dielectric layer which is remained on the side surface of each gate structure after the side wall etching process.
And after the side wall etching process, the first dielectric layer 105a with the first thickness is remained on the surface of the semiconductor substrate 101 outside the side wall 105. The first dielectric layer with a first thickness left on the surface of the semiconductor substrate 101 outside the sidewall 105 is separately denoted by reference numeral 105 a.
In some embodiments, after the deposition of the first dielectric layer and before the sidewall etching process, a first photolithography process is performed to form a first photoresist pattern to define a region where the sidewall 105 needs to be formed.
After the sidewall etching process, a photoresist wet stripping process is further performed, the photoresist wet stripping process can cause loss of the first dielectric layer, and the first thickness is the thickness of the first dielectric layer 105a reserved on the surface of the semiconductor substrate 101 outside the sidewall 105 after the photoresist wet stripping process.
In some embodiments, the first dielectric layer is an oxide layer or a stacked layer of an oxide layer and a nitride layer or a stacked layer of an oxide layer, a nitride layer and an oxide layer. The first dielectric layer 105a remaining on the surface of the semiconductor substrate 101 outside the sidewall 105 after the sidewall etching process is an oxide layer.
Preferably, the first thickness is
Step two, as shown in fig. 4C, a pattern of the photoresist 203 is formed by performing a photolithography process, and the formation region of the photodiode D101 is opened by the pattern of the photoresist 203.
As shown in fig. 4D, an ion implantation 204 with a heavy second conductivity type is performed in the formation region of the photodiode D101 to form the pinning layer 106, the ion implantation 204 of the pinning layer 106 penetrates through the first dielectric layer 105a, and the first thickness of the first dielectric layer is used to prevent the ion implantation 204 of the pinning layer 106 from damaging the surface of the semiconductor substrate 101, thereby reducing white spots of the CMOS image sensor.
In the embodiment of the present invention, the second conductive type doping of the pinning layer 106 is P-type doping, and the pinning layer 106 is formed on the surface of the first N-type region 102.
The P-type ion implantation impurities of the pinning layer 106 include boron.
Thereafter, as shown in fig. 4E, the photoresist 203 is removed.
Step three, as shown in fig. 4F, performing a post-sidewall-etching cleaning process, where the post-sidewall-etching cleaning process may generate loss on the first dielectric layer and reduce the thickness of the first dielectric layer 105b remaining on the surface of the semiconductor substrate 101 outside the sidewall 105 to a second thickness. The first dielectric layer with the second thickness reserved on the surface of the semiconductor substrate 101 outside the sidewall 105 is marked with a mark 105b alone.
The second thickness is less than
Step four, as shown in fig. 4G, source/drain implantation is performed in the formation region of each MOS transistor to form a corresponding source/drain region 107, where the source/drain implantation may pass through the first dielectric layer 105b, and the doping of the source/drain region 107 is optimized by reducing the thickness of the first dielectric layer 105b to a second thickness, for example, the junction depth and the doping concentration of the source/drain region 107 can be ensured.
In the embodiment of the invention, the source-drain injection of the NMOS is N-type source-drain injection;
and the source and drain injection of the PMOS is P-type source and drain injection.
In the embodiment of the invention, the ion implantation 204 of the acupuncture layer 106 is adjusted in the process, the ion implantation 204 of the acupuncture layer 106 in the prior art is placed after the source-drain implantation, but in the embodiment of the invention, the ion implantation 204 is placed before the source-drain implantation and after the side wall etching and post-cleaning process is placed, so that the thickness loss of the side wall etching and post-cleaning process on the side wall 105 dielectric layer, namely the first dielectric layer, outside the side wall 105 can be placed, the ion implantation 204 of the acupuncture layer 106 can penetrate through the first dielectric layer with the thicker thickness, namely the first thickness, and the ion implantation 204 of the acupuncture layer 106 can be prevented from generating damage to the semiconductor substrate 101, such as a silicon surface, so that the white spot problem caused by the surface damage of the photodiode D101 can be solved, and the embodiment of the invention can improve the white spot problem of CIS imaging; meanwhile, the embodiment of the invention can be realized only by changing the process sequence of the manufacturing steps, so that extra cost is not increased, for example, extra photoetching process or deposition process of a dielectric film layer is not required to be increased, and the embodiment of the invention also has the advantage of low process cost.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A method for manufacturing a CMOS image sensor, comprising the steps of:
providing a semiconductor substrate with a grid structure of an MOS transistor, wherein the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped; forming a side wall on the side surface of the gate structure, including: depositing a first dielectric layer, performing a side wall etching process on the first dielectric layer, and forming the side wall by self-aligning the first dielectric layer which is reserved on the side surface of each gate structure after the side wall etching process;
after the side wall etching process, the first dielectric layer with the first thickness is reserved on the surface of the semiconductor substrate outside the side wall;
performing second conductive type heavily doped ion implantation in a formation region of the photodiode to form an acupuncture layer, wherein the ion implantation of the acupuncture layer can penetrate through the first dielectric layer, and the first thickness of the first dielectric layer is utilized to prevent the ion implantation of the acupuncture layer from damaging the surface of the semiconductor substrate, so that white spots of the CMOS image sensor are reduced;
step three, performing a side wall etching post-cleaning process, wherein the side wall etching post-cleaning process can generate loss on the first dielectric layer and reduce the first dielectric layer reserved on the surface of the semiconductor substrate outside the side wall to a second thickness;
and fourthly, performing source-drain injection in the formation region of each MOS transistor to form a corresponding source-drain region, wherein the source-drain injection can penetrate through the first dielectric layer, and the doping of the source-drain region is optimized by reducing the thickness of the first dielectric layer to a second thickness.
2. The method of manufacturing a CMOS image sensor according to claim 1, wherein: in the first step, after the first dielectric layer is deposited and before the side wall etching process is carried out, a first photoetching process is carried out to form a first photoresist pattern so as to define an area needing to form the side wall;
and after the side wall etching process, performing a photoresist wet stripping process, wherein the photoresist wet stripping process can cause loss of the first dielectric layer, and the first thickness is the thickness of the first dielectric layer reserved on the surface of the semiconductor substrate outside the side wall after the photoresist wet stripping process.
3. The method of manufacturing a CMOS image sensor according to claim 2, wherein: in the first step, the first dielectric layer is an oxide layer or a superimposed layer of an oxide layer and a nitride layer or a superimposed layer of an oxide layer, a nitride layer and an oxide layer.
4. The method of manufacturing a CMOS image sensor according to claim 3, wherein: in the first step, the first dielectric layer on the surface of the semiconductor substrate, which is reserved outside the side wall after the side wall etching process, is an oxide layer.
5. The method of manufacturing a CMOS image sensor according to claim 4, wherein: the first thickness is
6. The method of manufacturing a CMOS image sensor according to claim 5, wherein: the second thickness is less than
7. The method of manufacturing a CMOS image sensor according to claim 1, wherein: the CMOS image sensor comprises a pixel area and a logic area;
the pixel region comprises a plurality of pixel unit circuits, and the pixel unit circuits comprise the photosensitive diodes and a plurality of MOS transistors.
8. The method of manufacturing a CMOS image sensor according to claim 7, wherein: when the pixel unit circuit is of a 3T type structure, the pixel unit circuit comprises 3 MOS transistors which are respectively as follows: reset tube, amplifier tube and selection tube.
9. The method of manufacturing a CMOS image sensor according to claim 7, wherein: when the pixel unit circuit is of a 4T-type structure, the pixel unit circuit comprises 4 MOS transistors, which are respectively as follows: reset tube, amplifier tube, selection tube and transmission tube.
10. The method of manufacturing a CMOS image sensor according to claim 7, wherein: MOS transistors in the pixel unit circuit are all NMOS;
the MOS transistors in the logic region include NMOS and PMOS.
11. The method of manufacturing a CMOS image sensor according to claim 10, wherein: the semiconductor substrate is doped in a P type manner;
before forming the side wall, the method further comprises the step of forming a first N-type region in a forming region of the photosensitive diode, wherein a PN junction formed by the first N-type region and the P-type semiconductor substrate is used as the photosensitive diode;
and in the second step, the second conductive type doping of the needle layer is P-type doping, and the needle layer is formed on the surface of the first N-type region.
12. The method of manufacturing a CMOS image sensor according to claim 11, wherein: the P-type ion implantation impurities of the pinning layer include boron.
13. The method of manufacturing a CMOS image sensor according to claim 11, wherein: a P-type doped first epitaxial layer is further formed on the surface of the semiconductor substrate, and the first N-type region is formed in the first epitaxial layer.
14. The method of manufacturing a CMOS image sensor according to claim 11, wherein: in the fourth step, the source drain injection of the NMOS is N-type source drain injection;
and the source and drain injection of the PMOS is P-type source and drain injection.
15. The method of manufacturing a CMOS image sensor according to claim 1, wherein: the semiconductor substrate includes a silicon substrate.
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