CN114242136A - Reference voltage optimization adjustment method and system for 3D NAND flash memory and computer-readable storage medium - Google Patents

Reference voltage optimization adjustment method and system for 3D NAND flash memory and computer-readable storage medium Download PDF

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CN114242136A
CN114242136A CN202111604633.XA CN202111604633A CN114242136A CN 114242136 A CN114242136 A CN 114242136A CN 202111604633 A CN202111604633 A CN 202111604633A CN 114242136 A CN114242136 A CN 114242136A
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pec
ret
flash memory
reference voltage
noise
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韩国军
朱广平
刘畅
张孝谊
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Guangdong University of Technology
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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Abstract

The invention discloses a method and a system for optimally adjusting reference voltage of a 3D NAND flash memory and a computer readable storage medium, wherein the method comprises the following steps: s1: randomly selecting an NAND flash memory block, sequentially adding PEC noise, Retention noise and Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise; s2: establishing a reference voltage regulation model by using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage; s3: a reference voltage offset value is calculated using a reference voltage adjustment model, and data is read from the NAND flash memory block using the reference voltage offset value. The invention integrates multidimensional noise and noise coupling when constructing the reference voltage regulation model, and simultaneously establishes the reference voltage regulation model by utilizing the optimal reference voltage, adopts model fitting of different orders and adds corresponding constraint.

Description

Reference voltage optimization adjustment method and system for 3D NAND flash memory and computer-readable storage medium
Technical Field
The invention relates to the technical field of flash memories, in particular to a method and a system for optimally adjusting reference voltage of a 3D NAND flash memory and a computer-readable storage medium.
Background
The 3D NAND flash memory technology is a mainstream storage technology in the era of Internet + big data, and has the characteristics of high read-write speed, high storage density and the like. The number of stacked layers of the current 3D NAND flash memory reaches 176, and with the continuous increase of storage density, data stored in the 3D NAND flash memory is more prone to error, and particularly after noise influences such as multiple times of erasing and writing, long-time placement and the like, the storage reliability is greatly influenced.
As the 3D NAND flash inevitably faces PEC noise and external noise interference of Data Retention and Read Disturb, the 3D NAND flash needs to adjust the reference voltage in the using process to reduce the generation of reading errors, and the reliability of the 3D NAND flash is improved. As shown in fig. 1, when the original read reference voltage is used to read data after the threshold voltage distribution is shifted, since the optimal decision point (i.e. the intersection point of two distributions, which makes the integration interval of the misjudgment probability minimum) is not selected in the overlapping distribution, the misjudgment probabilities of the two states are greatly increased.
The current way of adjusting the Read reference voltage by the 3D NAND flash memory controller is passive adjustment, i.e. the offset of the reference voltage is performed only when the error condition is bad and the Error Control Code (ECC) of the controller cannot be decoded successfully, which is often called Read Retry (RRT). Given the severe threshold voltage shift, the large number of RRT operations results in a large read delay for the NAND flash memory. As long as the ECC decoding fails, the controller will request RRT operation, and perform positive or negative bias on the reference voltage until the ECC decoding succeeds.
In order to reduce the read time delay of the 3D NAND flash memory, the current read reference voltage adjustment strategy increasingly adopts a dynamic adjustment mode, that is, the read reference voltage is autonomously adjusted when the controller senses that noise exists in the 3D NAND flash memory. The self-generating regulation method needs the controller to know prior information, namely, the controller needs to actually measure the change of the threshold voltage channel of the actual 3D NAND flash under different noise conditions, and then calculates the optimal reference voltage (Vopt) under different noise conditions to obtain the deviation value, so that the method can be applied to regulation, the 3D NAND flash channel is often measured and modeled in the step, and the flow diagram of the mainstream dynamic regulation mode is shown in FIG. 3.
The existing threshold voltage model only considers parameters of PEC and Data retentions, the Read reference voltage regulation accuracy of the 3D NAND flash memory is not enough, and the interference caused by external noise of Read Disturb and internal noise of Layer Variation is not considered. Meanwhile, in the existing PEC and Data Retention regulation models, most of the PEC and Data Retention regulation models do not consider the physical characteristics caused by abrasion of the PEC on the 3D NAND flash memory, so that the noise of the Data Retention and Read Disturb changes along with the PEC and Read Disturb, namely the noise of the PEC is coupled with other noise, the existing models only respectively measure, fit and calculate various noises, and the noise coupling condition is rarely considered. The current 3D NAND flash memory products are already applied to an Internet Data server center in a large number, the servers have trillion times of Data reading requests every day, the 3D NAND flash memory threshold voltage model which only considers PEC and Data Retention is limited in optimizing capacity of the 3D NAND flash memory which has heavy reading requests, the 3D NAND flash memory which has heavy reading requests can be interfered by stronger Read Disturb, and the 3D NAND flash memory threshold voltage model which considers the Read Disturb is urgently required in the design of a 3D NAND flash memory controller on the market; meanwhile, in the existing scheme, the noise coupling condition of the 3D NAND flash memory is not considered much, the scene considered by the flash memory threshold voltage model is single and not accurate enough, and further improvement is needed.
In addition, the existing model is based on a threshold voltage model of a 3D FG NAND flash memory or a 3D CT NAND flash memory, the measurement and modeling processes of various schemes for different types of 3D NAND flash memories are different, and none of the schemes for measuring and modeling two types of 3D NAND flash memories by using the same method is available on the market, and the design of the adjustment method for the controller of the 3D NAND flash memory product on the actual market is not comprehensive.
The prior art discloses a method and a system for adjusting threshold voltage in a 3D flash memory and the 3D flash memory, and relates to the technical field of flash memory data reading. The technical key point of the adjusting method comprises that a storage element of a reserved part in a flash memory block is used as a check storage element; writing specified collation data in the collation memory element; reading the check data on the check storage element as read data; comparing the check data with the read data to obtain a detection set of the memory cells; selecting a problem threshold voltage from the seven threshold voltages based on the comparison detection set; and modifying the problem threshold voltage based on the calculation of the detection set. This scheme does not take into account multi-dimensional noise and noise coupling.
Disclosure of Invention
The invention provides a method and a system for optimally adjusting reference voltage of a 3D NAND flash memory and a computer-readable storage medium, aiming at overcoming the defects that the existing 3D NAND flash memory reference voltage adjustment is not comprehensive in noise consideration, does not consider noise coupling and cannot be suitable for different types of flash memories.
The primary objective of the present invention is to solve the above technical problems, and the technical solution of the present invention is as follows:
the invention provides a reference voltage optimization and regulation method for a 3D NAND flash memory, which comprises the following steps:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: a reference voltage offset value is calculated using a reference voltage adjustment model, and data is read from the NAND flash memory block using the reference voltage offset value.
Further, the method comprises the steps of randomly selecting a NAND flash memory block, sequentially adding PEC noise, Retention noise and Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block with the noise added to obtain corresponding optimal reference voltage, and specifically comprises the following steps:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution by utilizing the PEC-Ret-Read threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
Further, the concrete steps of establishing a reference voltage regulation model by using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage are as follows:
inputting the PEC-Ret optimal reference voltage, the PEC and the Ret into a first mathematical model for fitting, and outputting coefficients a, b, c, f and i, wherein a is a constant, b represents a PEC noise coefficient, c represents a noise coefficient of logarithm of Data Retention duration, f represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, i represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, the PEC represents flash memory erasing times, and the Ret represents Data Retention duration;
inputting the PEC-Ret-Read optimal reference voltages PEC and Read, a known coefficient b and a coefficient a about the PEC into a second mathematical model for fitting, and outputting coefficients d and g, wherein d represents a Read Disturb noise coefficient, and g represents a PEC and a ReadDisturb noise coupling coefficient;
inputting the PEC-Ret optimal reference voltage PEC, Layer, known coefficients about the PEC and a coefficient a into a third mathematical model for fitting, wherein output coefficients e and h represent Layer Variation noise coefficients, h represents coupling coefficients of the PEC and the Layer Variation noise, and Layer represents the number of layers of a flash memory;
and inputting the obtained coefficients a-i into the original mathematical model to obtain a final reference voltage regulation model.
Further, the first mathematical model expression is as follows:
Figure BDA0003433278810000041
further, the second mathematical model expression is:
Vopt＝a+b*PEC+d*Read+g*PEC*Read。
further, the third mathematical model expression is:
Vout＝a+b*PEC+e*Layer+h*PEC*Layer。
further, the mathematical expression of the original model is as follows:
Vopt＝a+b*PEC+c*logRet.+d*Read+e*Layer+f*PEC*logRet. +g*PEC*Read+h*PEC*Layer+i*log2Ret。
the invention provides a reference voltage optimization and regulation system of a 3D NAND flash memory, which comprises: the device comprises a memory and a processor, wherein the memory comprises a 3D NAND flash memory reference voltage optimization adjustment method program, and the 3D NAND flash memory reference voltage optimization adjustment method program realizes the following steps when executed by the processor:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: and calculating a reference voltage offset value by using a reference voltage regulation model, reading data from the NAND flash memory block by using the reference voltage offset value and default reference voltage respectively, and comparing the error rates of the two data reading modes.
Further, the method comprises the steps of randomly selecting a NAND flash memory block, sequentially adding PEC noise, Retention noise and Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block with the noise added to obtain corresponding optimal reference voltage, and specifically comprises the following steps:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution by utilizing the PEC-Ret-Read threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
The third aspect of the present invention provides a computer-readable storage medium, where the computer-readable storage medium includes a 3D NAND flash memory reference voltage optimization adjustment method program, and when the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of the 3D NAND flash memory reference voltage optimization adjustment method are implemented.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the invention integrates multidimensional noise and noise coupling when constructing the reference voltage regulation model, and adopts model fitting of different orders and adds corresponding constraint when utilizing the optimal reference voltage to establish the reference voltage regulation model.
Drawings
FIG. 1 is a diagram illustrating two shift conditions of threshold voltage distributions of a 3D NAND flash memory in the prior art.
FIG. 2 is a flow chart of a reference voltage regulation strategy of a 3D NAND flash memory in the prior art.
FIG. 3 is a flow chart of a conventional method for dynamically adjusting a read reference voltage.
Fig. 4 is a flowchart of a reference voltage optimization adjusting method for a 3D NAND flash memory according to the present invention.
FIG. 5 is a block diagram of a reference voltage optimization and regulation system of a 3D NAND flash memory according to the present invention.
FIG. 6 is a comparison graph of bit error rates of read data from two different types of 3D NAND flash memories according to an embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
The noun explains:
PEC noise: and in the flash memory threshold voltage channel modeling process, the PEC error is erased and written for many times to cause noise with voltage change.
Retention noise: in the flash memory threshold voltage channel modeling, the voltage is changed due to Data Retention errors which are placed for a long time.
Read noise: in the threshold voltage channel modeling of the flash memory, the Read Disturb error caused by multiple reading leads to the noise of voltage change.
PEC-Ret threshold voltage detection: in the modeling process of the flash memory threshold voltage channel, coupling noise caused by the combined action of PEC errors after multiple times of erasing and writing and Data retentivity errors caused by long-time placement.
PEC-Ret-Read threshold voltage detection: in the process of modeling a flash memory threshold voltage channel, PEC errors after multiple times of erasing, Data Retention errors brought by long-time placement, Read Disturb errors brought by multiple times of reading and coupling noise brought by the combined action of the PEC errors, the Data Retention errors and the Read Disturb errors.
Example 1
As shown in fig. 1, a first aspect of the present invention provides a method for optimally adjusting reference voltage of a 3D NAND flash memory, comprising the following steps:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Re optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: a reference voltage offset value is calculated using a reference voltage adjustment model, and data is read from the NAND flash memory block using the reference voltage offset value.
It should be noted that, in the invention, noise is added to a randomly selected NAND flash memory block, PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are respectively carried out on the NAND flash memory block added with the noise to obtain threshold voltage counting points, then gaussian fitting is carried out on the counting points of the threshold voltage to obtain 3D NAND flash memory threshold voltage discrete distribution, intersection points of adjacent storage states in the discrete distribution are solved to obtain PEC-Ret optimal reference voltage and PEC-Ret-Read optimal reference voltage, and a reference voltage regulation model is established by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage; and finally, calculating a reference voltage offset value by using a reference voltage regulation model, and reading data from the NAND flash memory block by using the reference voltage offset value.
Further, the specific steps of randomly selecting the NAND flash memory block, sequentially adding the PEC noise, the Retention noise and the Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise are as follows:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution by utilizing the PEC-Ret-Read threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
It should be noted that, in a specific embodiment, the threshold voltage detection may be performed by using a reference voltage offset method, that is, reading a count point of a storage state of the 3D NAND flash memory under each offset to obtain a discrete distribution of the threshold voltage of the 3D NAND flash memory, first reading the storage state count with a default reference voltage of each state, then setting a positive offset of the reference voltage, reading the storage state count under the state, and calculating a difference between the count point of the state and a previous state count to obtain a storage state count value falling in the interval. In a specific implementation process, marking a flash memory block obtained by adding PEC noise and Retention noise as a first flash memory block, and adding Read noise to the first flash memory block as a second flash memory block;
performing PEC-Ret threshold voltage counting on the first flash memory block by adopting a reference voltage migration method, performing Gaussian fitting by using the PEC-Ret threshold voltage counting to obtain PEC-Ret threshold voltage distribution, solving adjacent storage state intersection points in the PEC-Ret threshold voltage distribution, wherein the abscissa corresponding to the intersection points is the PEC-Ret optimal reference voltage;
and counting the PEC-Ret-Read threshold voltage of the second flash memory block by adopting a reference voltage offset method, performing Gaussian fitting by utilizing the PEC-Ret-Read threshold voltage counting to obtain PEC-Ret-Read threshold voltage distribution, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution, wherein the abscissa of the intersection point is the optimal reference voltage of the PEC-Ret-Read.
Further, the concrete steps of establishing a reference voltage regulation model by using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage are as follows:
inputting the PEC-Ret optimal reference voltage, the PEC and the Ret into a first mathematical model for fitting, and outputting coefficients a, b, c, f and i, wherein a is a constant, b represents a PEC noise coefficient, c represents a noise coefficient of logarithm of Data Retention duration, f represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, i represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, the PEC represents flash memory erasing times, and the Ret represents Data Retention duration;
inputting the PEC-Ret-Read optimal reference voltages PEC and Read, a known coefficient b and a coefficient a about the PEC into a second mathematical model for fitting, and outputting coefficients d and g, wherein d represents a Read Disturb noise coefficient, and g represents a PEC and a ReadDisturb noise coupling coefficient;
and inputting the PEC-Ret optimal reference voltage PEC, Layer, known coefficients about the PEC and a coefficient a into a third mathematical model for fitting, wherein output coefficients e and h represent Layer Variation noise coefficients, h represents a coupling coefficient of the PEC and the Layer Variation noise, and Layer represents the number of layers of the flash memory.
And inputting the obtained coefficients a-i into the original mathematical model to obtain a final reference voltage regulation model.
Further, the first mathematical model expression is as follows:
Figure BDA0003433278810000081
further, the second mathematical model expression is:
Vopt＝a+b*PEC+d*Read+g*PEC*Read。
further, the third mathematical model expression is:
Vopt＝a+b*PEC+e*Layer+h*PEC*Layer。
further, the mathematical expression of the original model is as follows:
Vopt＝a+b*PEC+c*logRet.+d*Read+e*Layer+f*PEC*logRet. +g*PEC*REad+h*PEC*Layer+i*log2Ret。
it should be noted that the reference voltage regulation model provided by the present invention is a model related to multidimensional parameters, and is performed by a method of fitting actual measurement values on the model establishment, and meanwhile, due to the large fitting complexity of the multidimensional model, the model establishment can adopt distributed fitting, that is, noise with large influence is fitted first, after the parameter is obtained, the parameter is brought into the model with constraint, and then noise with small influence is fitted. The mathematical representation of the original model proposed by the present invention obtains the value of each coefficient by step-wise fitting.
Firstly, inputting a PEC-Ret optimal reference voltage Vopt (namely, an optimal reference voltage obtained under the PEC-Retention noise), a PEC and Ret into a first mathematical model for fitting, wherein parameters irrelevant to the PEC and Data Retention in the model are set to be 0, and only considering the noise and coupling of the PEC and Data Retention, the fitting expression is as follows:
Vopt＝a+b*PEC+c*logRet.+f*PEC*logRet +i*log2Ret
the output coefficients are a, b, c, f and i, and it should be noted that the above formula model is a linear regression model of PEC first order and ret second order. By selecting the second-order model, the Early Loss phenomenon existing in the current 3D NAND flash memory can be better fitted compared with the traditional first-order model.
Inputting the PEC-Ret-Read optimal reference voltage (optimal reference voltage obtained under PEC-Retention-Read noise), the PEC, the Read, known coefficients about the PEC and coefficients a into a second mathematical model for fitting, wherein the fitting only considers noise and coupling of the PEC and the Read, and at the moment, the model fitting selects data fixed by Retention, so the coefficients about the Ret are set to be 0, and the fitting expression is as follows:
Vopt＝a+b*PEC+d*Read+g*PEC*Read
the output coefficients d, g, Read represent Read noise, and it should be noted that the second mathematical model is a linear regression model of PEC order and Read order.
Inputting the PEC-Ret optimal reference voltage Vopt (namely the optimal reference voltage obtained under the PEC-latency noise), the PEC, the Layer, known coefficients about the PEC and coefficients a into a third mathematical model for fitting, only considering the noise and coupling of the PEC and the Layer, and setting the coefficients about the Ret to be 0 at the moment because the model fitting selects data with fixed latency, wherein the fitting expression is as follows:
Vopt＝a+b*PEC+e*Layer+h*PEC*Layer
the output coefficients e and h are linear regression models of PEC first order and Layer first order.
And inputting the obtained coefficients a to i into the original mathematical model to obtain a final reference voltage regulation model. The fitting of the model considers the sequencing of the influence of noise, firstly fits the noise combination with the largest influence, obtains the correlation coefficient and then brings the next group of noise combinations into the fitting to carry out constraint fitting, and improves the accuracy of the model.
Example 2
The second aspect of the present invention provides a reference voltage optimization and regulation system for a 3D NAND flash memory, comprising: the device comprises a memory and a processor, wherein the memory comprises a 3D NAND flash memory reference voltage optimization adjustment method program, and the 3D NAND flash memory reference voltage optimization adjustment method program realizes the following steps when executed by the processor:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: a reference voltage offset value is calculated using a reference voltage adjustment model, and data is read from the NAND flash memory block using the reference voltage offset value.
Further, the method comprises the steps of randomly selecting a NAND flash memory block, sequentially adding PEC noise, Retention noise and Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block with the noise added to obtain corresponding optimal reference voltage, and specifically comprises the following steps:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage distribution by utilizing the PEC-Ret-Read threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
Example 3
The third aspect of the present invention provides a computer-readable storage medium, where the computer-readable storage medium includes a 3D NAND flash memory reference voltage optimization adjustment method program, and when the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of the 3D NAND flash memory reference voltage optimization adjustment method are implemented.
Verification and analysis
In the embodiment, the 3D NAND flash memory block is randomly selected again, noise is added to the flash memory block, the optimal reference voltage and the default reference voltage are applied to read data, the error rates of the optimal reference voltage and the default reference voltage are compared, and the improvement of the optimal reference voltage calculated by the verification model on the reliability of the 3D NAND flash memory is verified. Because the reference voltage of the current 3D NAND flash only supports block adjustment, and the trend change of the difference between layers according to the original bit error rate (RBER) of the 3D NAND flash is linear, the Layer parameter of the equation takes the median stored in the 3D NAND flash to be calculated, the 3D NAND flash adopting a 64-Layer process in the invention takes the median of 32. The optimal reference voltage model is reduced by 20% on average for the original bit error rate of the 3D FG TLC NAND flash memory and 30% on average for the original bit error rate of the 3D CT TLC NAND flash memory, as shown in fig. 6, it is verified that the model is effective, wherein in fig. 6, the left side is the 3D FG TLC NAND flash memory and is compared with the error rate of data read by adopting the default voltage, and the right side is the 3D CT TLC NAND flash memory and is compared with the error rate of data read by adopting the default voltage.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. It will be apparent to those skilled in the art that other variations and modifications can be made on the basis of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (10)

1. A reference voltage optimization and regulation method for a 3D NAND flash memory is characterized by comprising the following steps:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: a reference voltage offset value is calculated using a reference voltage adjustment model, and data is read from the NAND flash memory block using the reference voltage offset value.
2. The method for optimally adjusting the reference voltage of the 3D NAND flash memory according to claim 1, wherein the method comprises the following specific steps of randomly selecting a NAND flash memory block, sequentially adding PEC noise, Retention noise and Read noise, and respectively performing PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block with the noise added to obtain the corresponding optimal reference voltage:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage count to the PEC-Ret-Read threshold voltage distribution, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
3. The method for optimally adjusting the reference voltage of the 3D NAND flash memory according to claim 2, wherein the concrete steps of establishing a reference voltage adjustment model by using the PEC-Ret threshold voltage and the PEC-Ret-Read threshold voltage are as follows:
inputting the PEC-Ret optimal reference voltage, the PEC and the Ret into a first mathematical model for fitting, and outputting coefficients a, b, c, f and i, wherein a is a constant, b represents a PEC noise coefficient, c represents a noise coefficient of logarithm of Data Retention duration, f represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, i represents a coupling coefficient of the PEC and the Data Retention duration logarithmic noise, the PEC represents flash memory erasing times, and the Ret represents Data Retention duration;
inputting the PEC-Ret-Read optimal reference voltages PEC and Read, a known coefficient b and a coefficient a about the PEC into a second mathematical model for fitting, and outputting coefficients d and g, wherein d represents a Read Disturb noise coefficient, and g represents a PEC and a Read Disturb noise coupling coefficient;
inputting the PEC-Ret optimal reference voltage PEC, Layer, known coefficients about the PEC and a coefficient a into a third mathematical model for fitting, wherein output coefficients e and h represent Layer Variation noise coefficients, h represents coupling coefficients of the PEC and the Layer Variation noise, and Layer represents the number of layers of a flash memory;
and inputting the obtained coefficients a-i into the original mathematical model to obtain a final reference voltage regulation model.
4. The method as claimed in claim 3, wherein the first mathematical model expression is as follows:
Figure FDA0003433278800000021
5. the method as claimed in claim 3, wherein the second mathematical model expression is as follows:
Vopt＝a+b*PEC+d*Read+g*PEC*Read。
6. the method of claim 3, wherein the third mathematical model expression is as follows:
Vopt＝a+b*PEC+e*Layer+h*PEC*Layer。
7. the method of claim 3, wherein the mathematical expression of the original model is as follows:
Vopt＝a+b*PEC+c*log Ret+d*Read+e*Layer+f*PEC*log Ret+g*PEC*Read+h*PEC*Layer+i*log2Ret。
8. A3D NAND flash memory reference voltage optimization regulation system, the system comprising: the device comprises a memory and a processor, wherein the memory comprises a 3D NAND flash memory reference voltage optimization adjustment method program, and the 3D NAND flash memory reference voltage optimization adjustment method program realizes the following steps when executed by the processor:
s1: selecting a NAND flash memory block randomly, adding PEC noise, Retention noise and Read noise in sequence, and respectively carrying out PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection on the NAND flash memory block added with the noise to obtain corresponding optimal reference voltage;
s2: establishing a reference voltage regulation model by using the PEC-Ret optimal reference voltage and the PEC-Ret-Read optimal reference voltage;
s3: and calculating a reference voltage offset value by using a reference voltage regulation model, reading data from the NAND flash memory block by using the reference voltage offset value and default reference voltage respectively, and comparing the error rates of the two data reading modes.
9. The system of claim 8, wherein the random selection of the NAND flash memory block and the sequential addition of the PEC noise, the Retention noise, and the Read noise are performed to the NAND flash memory block after the noise addition, and PEC-Ret threshold voltage detection and PEC-Ret-Read threshold voltage detection are performed to obtain the corresponding optimal reference voltage, and the specific steps are as follows:
randomly selecting a NAND flash memory block, adding PEC noise and Retention noise in sequence to obtain a flash memory block, recording the flash memory block as a first flash memory block, and adding Read noise to the first flash memory block, and recording the flash memory block as a second flash memory block;
detecting PEC-Ret threshold voltage count of the first flash memory block, fitting PEC-Ret threshold voltage distribution by utilizing the PEC-Ret threshold voltage count, and solving the intersection point of adjacent storage states in the PEC-Ret threshold voltage distribution to obtain the PEC-Ret optimal reference voltage;
and detecting the PEC-Ret-Read threshold voltage count of the second flash memory block, fitting the PEC-Ret-Read threshold voltage count to the PEC-Ret-Read threshold voltage distribution, and solving the intersection point of adjacent storage states in the PEC-Ret-Read threshold voltage distribution to obtain the PEC-Ret-Read optimal reference voltage.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium includes a 3D NAND flash memory reference voltage optimization adjustment method program, and when the 3D NAND flash memory reference voltage optimization adjustment method program is executed by a processor, the steps of a 3D NAND flash memory reference voltage optimization adjustment method according to any one of claims 1 to 7 are implemented.
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* Cited by examiner, † Cited by third party
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