CN114242131A - Chip and related chip system - Google Patents

Chip and related chip system Download PDF

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Publication number
CN114242131A
CN114242131A CN202010942264.4A CN202010942264A CN114242131A CN 114242131 A CN114242131 A CN 114242131A CN 202010942264 A CN202010942264 A CN 202010942264A CN 114242131 A CN114242131 A CN 114242131A
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CN
China
Prior art keywords
chip
data
dram
serial transmission
transmission interface
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Pending
Application number
CN202010942264.4A
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Chinese (zh)
Inventor
郑景升
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202010942264.4A priority Critical patent/CN114242131A/en
Publication of CN114242131A publication Critical patent/CN114242131A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 

Abstract

The invention discloses a chip and a related chip system, wherein the chip system comprises a first chip, a first DRAM, a second chip and a second DRAM, wherein the first chip comprises a first DRAM controller and a first serial transmission interface, the first DRAM is coupled with the first DRAM controller, the second chip comprises a second DRAM controller and a second serial transmission interface, the second serial transmission interface is coupled with the first serial transmission interface, and the second DRAM is coupled with the second DRAM controller. When the first chip is to temporarily store first data and second data, the first chip stores the first data to the first DRAM through the first DRAM controller, and transmits the second data to the second chip through the first serial transmission interface; and the second chip stores the second data to the second DRAM through the second DRAM controller.

Description

Chip and related chip system
Technical Field
The invention relates to a chip system comprising a dynamic random access memory.
Background
A Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) is a Memory having a high-speed multi-bit parallel transmission interface, and considering that the parallel transmission interface has many contacts/pins and transmission lines, a single chip only has a DDR interface circuit. However, since a single chip only has one DDR interface circuit, the bandwidth (bandwidth) of the DDR interface circuit limits the applications and capabilities of the chip and the system.
Disclosure of Invention
Therefore, one of the objectives of the present invention is to provide a system comprising a plurality of chips, wherein a single chip can request access to the DDR DRAM of another chip through a serial transmission interface, so as to effectively expand the bandwidth of the chip, and no additional DDR interface circuit is required to be provided, so as to solve the problems described in the prior art.
In one embodiment of the present invention, a chip system is disclosed, which comprises a first chip, a first DRAM, a second chip and a second DRAM, wherein the first chip comprises a first DRAM controller and a first serial transmission interface, the first DRAM is coupled to the first DRAM controller of the first chip, the second chip comprises a second DRAM controller and a second serial transmission interface, the second serial transmission interface is coupled to the first serial transmission interface, and the second DRAM is coupled to the second DRAM controller of the second chip. When the first chip is to temporarily store a first data and a second data, the first chip stores the first data to the first DRAM through the first DRAM controller and transmits the second data to the second chip through the first serial transmission interface; and the second chip stores the second data to the second DRAM through the second DRAM controller.
In another embodiment of the present invention, a chip is disclosed, which comprises a core circuit, a DRAM controller and a serial transmission interface, wherein the DRAM controller is coupled to a DRAM, and the serial transmission interface is coupled to another chip. When the core circuit is to temporarily store a first data and a second data, the core circuit stores the first data to the DRAM through the DRAM controller, and transmits the second data to the other chip through the serial transmission interface, so that the other chip can store the second data in the other DRAM which can be accessed by the other chip.
Drawings
Fig. 1 is a schematic diagram of a chip system according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a chip system according to another embodiment of the invention.
Detailed Description
Fig. 1 is a diagram of a chip system 100 according to an embodiment of the invention. As shown in fig. 1, the chip system 100 includes three chips 110, 120, and 130 and three DRAMs 141, 142, and 143, wherein the chip 110 includes a core circuit 112, a DRAM controller 114, a serial transmission interface (in this embodiment, a Peripheral Component Interconnect Express (PCIe) interface 116), and a memory 118; chip 120 includes a core circuit 122, a DRAM controller 124, two PCIe interfaces 126, 127, and a memory 128; chip 130 includes a core circuit 132, a DRAM controller 134, a PCIe interface 136, and a memory 138. In the present embodiment, the chips 110, 120, 130 may be any chip that may include a DRAM controller, such as a central processing unit, a graphics processor, or any other chip with specific or general functionality. In addition, it should be noted that in other embodiments, the serial transmission interface is not limited to use a PCIe interface, and may be any transmission interface capable of providing an equivalent bandwidth.
In the embodiment, the chip 110 includes only a single DRAM controller 114, that is, the chip 110 itself includes only one set of DDR interface circuits, and the chip 110 can only directly access the DRAM 141 but cannot directly access other DRAMs, but the invention is not limited thereto. In addition, the chip 120 includes only a single DRAM controller 124, and the chip 130 also includes only a single DRAM controller 134, but the invention is not limited thereto.
In the embodiment shown in fig. 1, since the chip 110 only includes a single DRAM controller 114 and can only directly access the DRAM 141, in order to avoid the function and application of the chip 110 being limited by the bandwidths of the DRAM controller 114 and the DRAM 141, the chip 110 in this embodiment may regard the DRAMs 142 and 143 shown as virtual memories of its own that can only be directly accessed by the chips 120 and 130, that is, the chip 110 may access the DRAMs 142 and 143 through the chips 120 and 130 to expand its own bandwidth.
Specifically, when chip 110 needs to write three data items to DRAM, core circuit 112 may directly write the first data item to DRAM 141 through DRAM controller 114; in addition, the chip 110 additionally transmits the second and third data to the chip 120 through the PCIe interface 116, and after the core circuit 122 of the chip 120 receives the second and third data from the chip 110 through the PCIe interface 127, the core circuit 122 may directly write the second data to the DRAM 142 through the DRAM controller 124 and transmit the third data to the chip 130 through the PCIe interface 126; after the core circuit 132 of the chip 130 receives the third data from the chip 120 through the PCIe interface 136, the core circuit 132 may directly write the third data to the DRAM 143 through the DRAM controller 134. As described above, by using the PCIe interface 116 to transmit part of the data to the chips 120 and 130 and write the data to the DRAMs 142 and 143 corresponding to the chips 120 and 130, respectively, the storage space and the bandwidth of the chip 110 can be effectively increased.
In this embodiment, the chip 110 may write data of the chip 110 itself to the DRAMs 142 and 143 corresponding to the chips 120 and 130, respectively, by means of address extension (address extended) or address mapping (address mapping). For example, assuming that the first, second and third data of the chip 110 respectively have addresses (logical addresses) LBA1, LBA2 and LBA3, the core circuit 112 may establish a lookup table in the memory 118, wherein the lookup table may record that the first data having address LBA1 is stored in the DRAM 141, and the second and third data having addresses LBA2 and LBA3 are stored in other chips; the core circuit 122 of the chip 120 also builds a lookup table in the memory 128, wherein the lookup table can record the second data with the address LBA2 stored in the DRAM 142, and the third data with the address LBA3 stored in the chip 130.
When the chip 110 needs to access the first, second and third data previously written into the DRAMs 141, 142 and 143, respectively, first, the core circuit 112 refers to the lookup table stored in the memory 118 to determine that the first data is stored in the directly accessible DRAM 141, and the second and third data are stored in the other chips. At this time, the core circuit 112 transfers the address LBA1 of the first data to the DRAM controller 114 for the DRAM controller 114 to read the first data from the DRAM 141 according to the internal address mapping mechanism, and the core circuit 112 additionally sends a read command to transfer the addresses LBA2 and LBA3 of the second and third data to the chip 120 through the PCIe interface 116. After the chip 120 receives the addresses LBA2 and LBA3, first, the core circuit 122 refers to the lookup table stored in the memory 128 to determine that the second data is stored in the directly accessible DRAM 142, and the third data is stored in the chip 130, at this time, the core circuit 122 transmits the address LBA2 of the second data to the DRAM controller 124, so that the DRAM controller 124 reads the second data from the DRAM 142 according to the internal address mapping mechanism, and the core circuit 122 additionally transmits the address LBA3 of the third data to the chip 130 through the PCIe interface 126; in addition, after the second data is read, the core circuit 122 immediately transmits the second data to the chip 110 through the PCIe interface 127. Then, after the chip 130 receives the address LBA3, the core circuit 132 transmits the address LBA3 of the third data to the DRAM controller 134, so that the DRAM controller 134 reads the third data from the DRAM 143 according to an internal address mapping mechanism, and immediately transmits the read third data to the chip 120 through the PCIe interface 136; the core circuit 122 of the chip 120 receives the third data from the chip 130 and immediately transmits the third data to the chip 110 through the PCIe interface 127.
In one embodiment, chip 110 receives the first data from DRAM 141 and the second data from chip 120 simultaneously in partially overlapping time periods to quickly retrieve the first data and the second data.
As mentioned above, DRAM 141, 142, 143 can be regarded as a memory accessible by chip 110, and the serial transmission speed of the current PCIe fifth generation specification can reach 64Gb/s (gigabits per second), so that the bandwidth of chip 110 can be greatly increased by using both DDR interface and PCIe interface to transmit data. Further, since the PCIe interface 116 using serial transmission has fewer data transmission lines, it does not cause too much burden on the chip area for the chip 110.
It should be noted that the number of chips in the chip system 100 shown in fig. 1 is only for exemplary purposes and is not a limitation of the present invention. Specifically, the chip system 100 may include only two chips, i.e., the chip 130, the DRAM 143, and the PCIe interface 126 of FIG. 1 may be removed from the figure without affecting the essential operation of the present invention. In addition, the chip system 100 may also include a fourth chip and a DRAM directly accessible only by the fourth chip, so as to be used as a virtual memory for the chip 110. Such variations in implementation are intended to be within the scope of the present invention.
In addition, fig. 1 illustrates the PCIe interfaces as an example, however, in other embodiments, the PCIe interfaces 116, 126, 127, 136 may be replaced by transmission interfaces with other specifications, such as Universal Serial Bus (USB).
Fig. 2 is a diagram of a chip system 200 according to another embodiment of the invention. As shown in fig. 2, the chip system 200 includes four chips 210, 220, 230, 240 and four DRAMs 251, 252, 253, 254, wherein the chip 210 includes a core circuit 212, a DRAM controller 214, two serial transmission interfaces (PCIe interfaces 216, 217 in this embodiment) and a memory 218; chip 220 includes a core circuit 222, a DRAM controller 224, two PCIe interfaces 226, 227, and a memory 228; the chip 230 includes a core circuit 232, a DRAM controller 234, two PCIe interfaces 236, 237, and a memory 238; chip 240 includes a core circuit 242, a DRAM controller 244, two PCIe interfaces 246, 247, and a memory 248. In the present embodiment, the chips 210, 220, 230, 240 may be any chip that may include a DRAM controller, such as a central processing unit, a graphics processor, or any other chip with specific or general functionality.
In the embodiment, the chips 210, 220, 230, and 240 all include only a single DRAM controller, that is, the chips 210, 220, 230, and 240 can only directly access the corresponding DRAM, but cannot directly access other DRAMs.
In the embodiment shown in fig. 2, since the chips 210, 220, 230, and 240 only include a single DRAM controller, in order to avoid the limitation of the functions and applications of the chips 210, 220, 230, and 240 by the bandwidth of the DRAM, the chips 210, 220, 230, and 240 in this embodiment may all regard the DRAMs 251, 252, 253, and 254 as their own virtual memories, that is, each of the chips 210, 220, 230, and 240 may access other DRAMs through other chips to expand its own bandwidth.
Specifically, when the chip 210 needs to write three data to the DRAM, the core circuit 212 may directly write the first data to the DRAM 251 through the DRAM controller 214; in addition, the chip 210 additionally transmits the second and third data to the chips 220 and 240 through PCIe interfaces 216 and 217, respectively. After the core circuit 222 of the chip 220 receives the second data from the chip 210 through the PCIe interface 227, the core circuit 222 may directly write the second data to the DRAM 252 through the DRAM controller 224; and the core circuit 242 of the chip 240 may write the third data to the DRAM 254 directly through the DRAM controller 244 after receiving the third data from the chip 210 through the PCIe interface 246. As described above, part of the data is transferred to the chips 220, 240 by using the PCIe interfaces 216, 217, and the data is written to the DRAMs 252, 254 corresponding to the chips 220, 240, respectively.
In the present embodiment, the chip 210 may write the data of the chip 210 itself to the DRAMs 252 and 254 corresponding to the chips 220 and 240 respectively by means of address extension or address mapping. For example, assuming that the first, second and third data of the chip 210 have addresses (logical addresses) LBA1, LBA2 and LBA3, respectively, the core circuit 112 may establish a lookup table in the memory 218, wherein the lookup table may record that the first data having address LBA1 is stored in the DRAM 251, and the second and third data having addresses LBA2 and LBA3 are stored in the chips 220 and 240.
When the chip 210 needs to access the first, second and third data previously written into the DRAMs 251, 252 and 254, respectively, first, the core circuit 212 refers to the lookup table stored in the memory 218 to determine that the first data is stored in the directly accessible DRAM 251, and the second and third data are stored in the chips 220 and 240, respectively. At this time, the core circuit 212 transfers the address LBA1 of the first data to the DRAM controller 214 for the DRAM controller 214 to read the first data from the DRAM 251 according to the internal address mapping mechanism, and the core circuit 112 additionally sends a read command to transfer the addresses LBA2 and LBA3 of the second and third data to the chips 220 and 240 through the PCIe interfaces 216 and 217, respectively. After the chip 220 receives the address LBA2, the core circuit 222 transmits the address LBA2 of the second data to the DRAM controller 224, so that the DRAM controller 224 reads the second data from the DRAM 252 according to an internal address mapping mechanism and immediately transmits the second data to the chip 210 through the PCIe interface 227; in addition, after the chip 240 receives the address LBA3, the core circuit 242 transmits the address LBA3 of the third data to the DRAM controller 244, so that the DRAM controller 244 reads the third data from the DRAM 254 according to an internal address mapping mechanism and immediately transmits the third data to the chip 210 through the PCIe interface 246.
It should be noted that the above description uses the chip 210 to write data into the DRAM as an example, however, the chips 220, 230, 240 in fig. 2 may also write their own data into the DRAMs of other chips through the above mechanism, for example, the chip 230 may transmit their own data to the chips 220, 240 through the PCIe interfaces 237, 236 to be stored in the DRAMs 252, 254.
As described above, the DRAMs 251, 252, 253, 254 can be regarded as memories accessible to the chips 210, 220, 230, 240, so that the bandwidths of the chips 210, 220, 230, 240 can be greatly increased by using the DDR interface and the PCIe interface to transmit data. Furthermore, since the serial-transfer PCIe interface has fewer data lines, it does not cause too much burden on the chip area for the chips 210, 220, 230, 240.
It should be noted that the number of chips in the chip system 200 shown in FIG. 2 is only for exemplary purposes and is not a limitation of the present invention. Specifically, system-on-chip 200 may include only three chips, e.g., chip 230 and DRAM 253 may be removed from the figure in FIG. 2, and PCIe interface 226 of chip 220 may be connected to PCIe interface 247 of chip 240. In addition, some chips in the chip system 200, such as the chip 210, may include more PCIe interfaces for connecting to more chips, so as to further expand the bandwidth of the chip system itself. Such variations in implementation are intended to be within the scope of the present invention.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
[ notation ] to show
100: chip system
110. 120, 130: chip and method for manufacturing the same
112. 122, 132: core circuit
114. 124, 134: DRAM controller
116. 126, 127, 136: PCIe interface
118. 128, 138: memory device
141、142、143：DRAM
200: chip system
210. 220, 230, 240: chip and method for manufacturing the same
212. 222, 232, 242: core circuit
214. 224, 234, 244: DRAM controller
216. 217, 226, 227, 236, 237, 246, 247: PCIe interface
218. 228, 238, 248: memory device
151、152、153、154：DRAM。

Claims (10)

1. A chip system, comprising:
a first chip including a first DRAM controller and a first serial transmission interface;
a first DRAM coupled to the first DRAM controller of the first chip;
a second chip including a second DRAM controller and a second serial transmission interface, wherein the second serial transmission interface is coupled to the first serial transmission interface; and
a second DRAM coupled to the second DRAM controller of the second chip;
when the first chip is to temporarily store a first data and a second data, the first chip stores the first data to the first dynamic random access memory through the first dynamic random access memory controller and transmits the second data to the second chip through the first serial transmission interface; and the second chip stores the second data into the second dynamic random access memory through the second dynamic random access memory controller.
2. The system on a chip of claim 1, wherein the first chip does not include other dram controllers than the first dram controller, and the first dram controller can only directly access the first dram.
3. The chip system according to claim 1, wherein the first serial transmission interface and the second serial transmission interface are peripheral component interconnect express (PCI express) interfaces.
4. The chip system of claim 1, wherein the first chip further comprises a memory including a lookup table, and the lookup table records that the address of the first data corresponds to the first DRAM or the first chip, and the address of the second data corresponds to the second chip.
5. The chip system according to claim 1, 2, 3 or 4, wherein when the first chip is to read the first data and the second data, the first chip reads the first data from the first DRAM through the first DRAM controller; and the first chip transmits a reading instruction to the second chip through the first serial transmission interface, wherein the reading instruction comprises the address of the second data, so that the second chip reads the second data from the second dynamic random access memory through the second dynamic random access memory controller and transmits the second data to the first chip through the second serial transmission interface.
6. The chip system of claim 5, wherein the first chip receives the first data from the first DRAM and the second data from the second chip simultaneously within partially overlapping times.
7. The chip system of claim 1, wherein the second chip further comprises another second serial transmission interface, and the chip system further comprises:
a third chip comprising a third dram controller and a third serial transmission interface, wherein the third serial transmission interface is coupled to the second serial transmission interface; and
a third DRAM coupled to the third DRAM controller of the third chip;
when the first chip is to temporarily store a third data, the first chip transmits the third data to the second chip through the first serial transmission interface, the second chip transmits the third data to the third chip through the other second serial transmission interface, and the third chip stores the third data to the third dynamic random access memory through the third dynamic random access memory controller.
8. The chip system of claim 1, wherein the first chip further comprises another first serial transmission interface, and the chip system further comprises:
a third chip including a third dram controller and a third serial transmission interface, wherein the third serial transmission interface is coupled to the other first serial transmission interface; and
a third DRAM coupled to the third DRAM controller of the third chip;
when the first chip is to temporarily store the first data, the second data and a third data, the first chip stores the first data into the first dynamic random access memory through the first dynamic random access memory controller, transmits the second data to the second chip through the first serial transmission interface, and transmits the third data to the third chip through the other first serial transmission interface; and the second chip stores the second data to the second dram through the second dram controller, and the third chip stores the third data to the third dram through the third dram controller.
9. A chip, comprising:
a core circuit;
a dynamic random access memory controller coupled to a dynamic random access memory;
a serial transmission interface coupled to another chip;
when the core circuit is to temporarily store a first data and a second data, the core circuit stores the first data to the dynamic random access memory through the dynamic random access memory controller, and transmits the second data to the other chip through the serial transmission interface, so that the other chip can store the second data in the other dynamic random access memory which can be accessed by the other chip.
10. The chip of claim 9, wherein when the core circuit is to read the first data and the second data, the core circuit reads the first data from the dram through the dram controller; and the core circuit transmits a read command to the other chip through the serial transmission interface, wherein the read command comprises an address of the second data so that the other chip can read the second data from the other dynamic random access memory.
CN202010942264.4A 2020-09-09 2020-09-09 Chip and related chip system Pending CN114242131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010942264.4A CN114242131A (en) 2020-09-09 2020-09-09 Chip and related chip system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010942264.4A CN114242131A (en) 2020-09-09 2020-09-09 Chip and related chip system

Publications (1)

Publication Number Publication Date
CN114242131A true CN114242131A (en) 2022-03-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010942264.4A Pending CN114242131A (en) 2020-09-09 2020-09-09 Chip and related chip system

Country Status (1)

Country Link
CN (1) CN114242131A (en)

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