CN114241963B - Display panel, display device and crack detection method - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The disclosure provides a display panel, a display device and a crack detection method, and belongs to the technical field of display. The display panel comprises a first power line, a second power line, a third power line and a crack detection circuit, wherein the crack detection circuit is positioned in a non-display area; the crack detection circuit comprises a detection line and a switch unit, one end of the detection line is connected with a first end of the switch unit, the other end of the detection line is connected with a second end of the switch unit, one of the second end and the third end of the switch unit is connected with a second power line, and the other of the second end and the third end of the switch unit is connected with a third power line; the switching unit is configured to turn on the second terminal and the third terminal when the detection line breaks, so that a display luminance difference between the second display region and the first display region becomes large. The crack detection of the display panel can be completed by only utilizing the original power line of the display panel, and other signal lines are not required to be additionally arranged, so that the structure of a crack detection circuit of the display panel is simplified.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a display panel, a display device and a crack detection method.
Background
In the actual production and transportation process, the outer packaging material of the display panel is easy to break under the action of stress, so that cracks (cracks) are generated in the non-display area at the side edge of the display panel, and the yield of the display panel is reduced.
In the related art, the non-display area of the display panel includes a crack detection circuit, but in general, the crack detection circuit needs to be additionally designed with a switch control signal line, and the structure of the crack detection circuit is complex.
Disclosure of Invention
The embodiment of the disclosure provides a display panel, which can simplify the structure of a crack detection circuit of the display panel. The technical scheme is as follows:
in a first aspect, a display panel is provided, the display panel having a non-display region, a first display region and a second display region, the first display region surrounding the second display region, the non-display region surrounding the first display region; the display panel comprises a first power line, a second power line, a third power line and a crack detection circuit which are positioned in the non-display area; the first power line is used for providing a first positive power voltage for pixels in the first display area, the second power line is used for providing a second positive power voltage for pixels in the second display area, the third power line is used for providing a negative power voltage for the display panel, and the first positive power voltage is smaller than the second positive power voltage; the crack detection circuit comprises a detection line and a switch unit, wherein the switch unit is provided with a first end, a second end and a third end; one end of the detection line is connected with the first end of the switch unit, and the other end of the detection line is connected with the second end of the switch unit; one of a second end and a third end of the switching unit is connected with one of the first power line and the second power line, and the other of the second end and the third end of the switching unit is connected with the third power line; the switching unit is configured to turn on the second terminal and the third terminal when the detection line breaks.
Optionally, the detection line includes a first portion and a second portion, one end of the first portion is connected with one end of the second portion and extends along two adjacent sides of the display panel, the other end of the first portion is connected with the second end of the switch unit, and the other end of the second portion is connected with the first end of the switch unit.
Optionally, the switching unit includes a switching transistor, a gate of the switching transistor is a first end of the switching unit, a source of the switching transistor is a second end of the switching unit, and a drain of the switching transistor is a third end of the switching unit; alternatively, the switching unit includes a plurality of switching transistors connected in series, a source of one end of the plurality of switching transistors connected in series is a second end of the switching unit, a drain of the other end of the plurality of switching transistors connected in series is a third end of the switching unit, and sources and drains of two adjacent switching transistors are connected.
Optionally, one of the second end and the third end of the switching unit is connected to the second power line through a second power supply branch line, the other of the second end and the third end of the switching unit is connected to the third power supply line through a third power supply branch line, the second power supply branch line and the second power supply line are located in different layers, and the third power supply branch line and the third power supply line are located in different layers.
Optionally, one of the second end and the third end of the switching unit is connected to the first power line through a first power branch line, the other of the second end and the third end of the switching unit is connected to the third power line through a third power branch line, the first power branch line and the first power line are located at the same layer or different layers, and the third power branch line and the third power line are located at different layers.
Optionally, the display panel includes at least two crack detection circuits, and the two crack detection circuits are respectively located at two opposite sides of the display panel.
Optionally, the display panel includes a substrate, a semiconductor layer, a first gate insulating layer, a first electrode layer, a second gate insulating layer, a second electrode layer, an interlayer insulating layer, a third electrode layer, a planarization layer, and a pixel defining layer sequentially located on the substrate; the first power line is positioned on the second electrode layer or the third electrode layer, the second power line is positioned on the second electrode layer, the third power line is positioned on the first electrode layer, and the second power branch line, the third power branch line and the detection line are positioned on the third electrode layer; the grid electrode of the switching transistor is positioned on the first electrode layer, and the detection line is connected with the grid electrode of the switching transistor through a via hole; the source of the switching transistor and the drain of the switching transistor are located in the semiconductor layer; the second power supply line is connected with the second power supply branch line through a via hole, and the second power supply branch line is connected with one of the second end and the third end of the switch unit through the via hole; the third power line is connected with the third power branch line through a via hole, and the third power branch line is connected with the other one of the second end and the third end of the switch unit through a via hole.
Optionally, the display panel includes a substrate, a semiconductor layer, a first gate insulating layer, a first electrode layer, a second gate insulating layer, a second electrode layer, an interlayer insulating layer, a third electrode layer, a planarization layer, and a pixel defining layer sequentially located on the substrate; the first power line is positioned on the second electrode layer or the third electrode layer, the second power line is positioned on the second electrode layer, the third power line is positioned on the first electrode layer, and the first power branch line, the third power branch line and the detection line are positioned on the third electrode layer; the grid electrode of the switching transistor is positioned on the first electrode layer, and the detection line is connected with the grid electrode of the switching transistor through a via hole; the source of the switching transistor and the drain of the switching transistor are located in the semiconductor layer; the first power supply line is connected with the first power supply branch line through a via hole, and the first power supply branch line is connected with one of the second end and the third end of the switch unit through the via hole; or, the first power line is connected with the first power branch line, and the first power branch line is connected with one of the second end and the third end of the switch unit through a via hole; the third power line is connected with the third power branch line through a via hole, and the third power branch line is connected with the other one of the second end and the third end of the switch unit through a via hole.
In a second aspect, a display device is provided, which includes the display panel of the first aspect.
In a third aspect, there is provided a crack detection method applied to the display panel of the first aspect, the method including: controlling the display panel to display; and determining whether the display panel has cracks or not according to the display brightness of the second display area and the display brightness of the first display area.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
in an embodiment of the disclosure, a display panel includes a first power line, a second power line, a third power line, and a crack detection circuit in a non-display area. The crack detection circuit comprises a detection line and a switch unit. One end of the detection line is connected with the first end of the switch unit, the other end of the detection line is connected with the second end of the switch unit, one of the second end and the third end of the switch unit is connected with one of the first power line and the second power line, and the other of the second end and the third end of the switch unit is connected with the third power line. Since the first power line provides the first positive power voltage for the pixels in the first display area, the second power line provides the second positive power voltage for the pixels in the second display area, the third power line provides the negative power voltage for the display panel, when the detection line breaks, the second end and the third end of the switch unit are conducted, the first positive power voltage of the first power line can be pulled down by the switch unit or the second positive power voltage of the second power line can be pulled down by the switch unit, and the brightness difference between the second display area and the subareas with the same area as the second display area in the first display area is increased. In this way, it is possible to determine whether or not a crack occurs in the display panel based on the display luminance difference between the first display region and the second display region. According to the embodiment of the disclosure, the crack detection of the display panel can be completed by only utilizing the original first power line, the second power line and the third power line of the display panel, and other signal lines are not required to be additionally arranged, so that the structure of a crack detection circuit of the display panel is simplified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic view of a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of pixel distribution of a display panel according to an embodiment of the disclosure;
fig. 3 is a schematic power supply diagram of a display panel according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 5 is a schematic structural view of another display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;
fig. 7 is a schematic structural view of another display panel according to an embodiment of the present disclosure;
fig. 8 is a schematic structural view of another display panel according to an embodiment of the present disclosure;
fig. 9 is a schematic structural view of another display panel according to an embodiment of the present disclosure;
Fig. 10 is a schematic structural view of another display panel according to an embodiment of the present disclosure;
FIG. 11 is a schematic view of another display panel according to an embodiment of the present disclosure;
fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the disclosure;
FIG. 13 is a process diagram of a display panel according to an embodiment of the present disclosure;
FIG. 14 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 15 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 16 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 17 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 18 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 19 is a process diagram of a display panel according to an embodiment of the present disclosure;
FIG. 20 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
FIG. 21 is a process diagram of a display panel made in accordance with an embodiment of the present disclosure;
fig. 22 is a flowchart of a crack detection method of a display panel according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
With the development of technology, the technology of an under-screen camera becomes more and more mainstream. The under-screen Camera technology refers to placing a Camera below a screen, so that a Camera display area can perform normal picture display function and Camera shooting function. Unlike previous hole-digging screen techniques, the camera area also retains the full screen display function.
Fig. 1 is a schematic view of a display panel according to an embodiment of the disclosure. As shown in fig. 1, the display panel has a non-display area B, a first display area a, and a second display area B. The first display area a surrounds the second display area b.
Wherein the non-display area B includes a peripheral area c surrounding the first display area a, a PAD area d, and an MFPC (Main Flexible Printed Circuit, main flexible circuit board) area e. The PAD region d is a binding region for crimping signal lines of the first display region a and the second display region b to external driving circuit boards, leads of driving ICs (Intergrated Circuit, integrated circuits), and pins.
The first display area a is an area under the screen where no camera is provided. The second display area b is a light-transmitting display area, and a camera is arranged below the screen of the second display area b. The second display area b may also be referred to as UDC (Under Display Camera, under-screen camera) area.
The second display area b is required to display pictures and avoid influencing the normal work of the camera, so that the second display area b has higher requirement on the screen transmittance.
Two methods may be employed to increase the screen transmittance of the second display region b.
In the first scheme, the second display area b adopts a low pixel density (PPI, pixels Per Inch), that is, the number of Pixels in the second display area b is reduced, and the pixel size is unchanged. Fig. 2 is a schematic diagram of pixel distribution of a display panel according to an embodiment of the disclosure. As shown in fig. 2, a block p in the figure is a pixel, and the number of pixels in the first display area a is greater than the number of pixels in the second display area b in the same display area. That is, the pixel density of the first display region a is higher than that in the second display region b.
In the second scheme, the number of pixels in the second display area b is unchanged, and the light emitting area of the pixels is reduced.
In both schemes, if the first display area a and the second display area b are controlled to emit light with the same electric parameter, the display brightness of the corresponding screen of the second display area b is lower than the display brightness of the screen corresponding to the first display area a. However, the display luminance of the first display area a and the display luminance of the second display area b should be the same in normal cases.
Here, the same electrical parameter includes that the positive power supply voltage and the pixel voltage of the pixel in the first display area a and the pixel in the second display area b are the same.
Fig. 3 is a schematic power supply diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 3, the positive power supply voltage ELVDD1 of the first display area a and the positive power supply voltage ELVDD2 of the second display area b are separately designed, that is, the positive power supply voltage ELVDD1 supplies power to the pixels in the first display area a and the positive power supply voltage ELVDD2 supplies power to the second display area b.
Equation (1) is a calculation equation of the current of the screen, see equation (1):
in the formula (1), W/L is the width-to-length ratio of a Drive TFT (thin film transistor), cox is the dielectric constant of a gate oxide layer, mu is the electron mobility, ELVDD is the positive power supply voltage, and Vdata is the IC Source voltage.
Since the screen light emission luminance is proportional to the current Id, in order to increase the screen luminance of the second display region b, the power supply voltage ELVDD2 of the second display region b is set to be greater than the power supply voltage ELVDD1 of the first display region a to reduce the luminance difference between the first display region a and the second display region b. Illustratively, the power supply voltage ELVDD1 of the first display area a is 4.6V and the power supply voltage ELVDD2 of the second display area b is 6V.
Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. Illustratively, the display panel is a flexible display panel, such as a flexible AMOLED (active-matrix organic light-emitting diode). A flexible display panel refers to a flexible display screen. Compared with the traditional display panel, the flexible display panel can be bent or folded, and has the advantages of impact resistance, strong shock resistance, light weight, portability and the like.
As shown in fig. 4, the display panel has a non-display area B (only areas c and d are shown in the figure), a first display area a surrounding the second display area B, and a second display area B surrounding the first display area a.
The display panel includes a first power line 10, a second power line 20, a third power line 30, and a crack detection circuit 40 located in the non-display region (B).
The first power line 10 is used for providing a first positive power voltage for the pixels in the first display area a, the second power line 20 is used for providing a second positive power voltage for the pixels in the second display area b, the first positive power voltage is smaller than the second positive power voltage, and the third power line 30 is used for providing a negative power voltage for the display panel.
The crack detection circuit includes a detection line 41 and a switching unit 42, the switching unit 42 having a first end 42a, a second end 42b, and a third end 42c.
One end of the detection line 41 is connected to a first end 42a of the switching unit 42, and the other end of the detection line 41 is connected to a second end 42b of the switching unit 42. One of the second end 42b and the third end 42c of the switching unit 42 is connected to one of the first power line 10 and the second power line 20, and the other of the second end 42b and the third end 42c of the switching unit 42 is connected to the third power line 30 of the display panel (only a case where the second end 42b of the switching unit 42 is connected to the second power line 20 and the third end 42c of the switching unit 42 is connected to the third power line 30 is shown in fig. 4).
The switching unit 42 is configured to turn on the second end 42a of the switching unit 42 and the third end 42c of the switching unit 42 when the detection line 41 breaks.
In some examples, as shown in fig. 4, one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the second power line 20, and one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the third power line 30.
When the display panel is cracked such that the detection line 41 is broken, since the switching unit 40 is in the on state, the negative power supply voltage of the third power supply line 30 interferes with the second positive power supply voltage of the second power supply line 20 and pulls down the second positive power supply voltage of the second power supply line 20, so that the display brightness of the second display region b is reduced. The first positive power voltage of the first power line 10 is not pulled down, and the display of the first display area a corresponding to the first power line 10 is not affected. The display luminance difference between the second display region b and the sub-region of the second display region a having the same area as the second display region b increases.
In other examples, as shown in fig. 5, one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the first power line 10, and one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the third power line 30.
When the display panel is cracked such that the detection line 41 is broken, since the switching unit 40 is in the on state, the negative power supply voltage of the third power supply line 30 interferes with the first positive power supply voltage of the first power supply line 10 and pulls down the first positive power supply voltage of the first power supply line 10, so that the display brightness of the first display area a is reduced. The second positive power voltage of the second power line 20 is not pulled down, and the display of the second display area b corresponding to the second power line 20 is not affected. The display luminance difference between the second display region b and the sub-region of the second display region a having the same area as the second display region b increases.
Therefore, when the detection line 41 breaks, the second display region b is clearly seen as abnormal in display according to the display luminance of the first display region a and the display luminance of the second display region b. At this time, it can be determined that the edge of the display panel is cracked.
In an embodiment of the disclosure, a display panel includes a first power line, a second power line, a third power line, and a crack detection circuit in a non-display area. The crack detection circuit comprises a detection line and a switch unit. One end of the detection line is connected with the first end of the switch unit, the other end of the detection line is connected with the second end of the switch unit, one of the second end and the third end of the switch unit is connected with one of the first power line and the second power line, and the other of the second end and the third end of the switch unit is connected with the third power line.
Since the first power line provides the first positive power voltage for the pixels in the first display area, the second power line provides the second positive power voltage for the pixels in the second display area, the third power line provides the negative power voltage for the display panel, when the detection line breaks, the switch unit is turned on, the first positive power voltage of the first power line is pulled down by the switch unit or the second positive power voltage of the second power line is pulled down by the switch unit, and the display brightness difference between the second display area and the first display area is increased. Thus, whether or not a crack occurs in the display panel can be determined based on the difference in display luminance between the first display region and the second display region. According to the embodiment of the disclosure, the crack detection of the display panel can be completed by only utilizing the original first power line, the second power line and the third power line of the display panel, and other signal lines are not required to be additionally arranged, so that the structure of a crack detection circuit of the display panel is simplified.
Alternatively, as shown in fig. 4, in the embodiment of the present disclosure, one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the second power line 20 through the second power supply branch line 21, and the other of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the third power supply line 30 through the third power supply branch line 31. The second power supply branch 21 and the second power supply line 20 are located at different layers, and the third power supply branch 31 and the third power supply line 30 are located at different layers.
The switching unit 42 is facilitated to be connected to the second power line 20 by providing the second power branch line 21, and the switching unit 42 is facilitated to be connected to the third power line 30 by providing the third power branch line 31.
Alternatively, as shown in fig. 5, in the embodiment of the present disclosure, one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the first power line 10 through the first power supply branch line 11, the other of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 is connected to the third power line 30 through the third power supply branch line 31, the first power supply branch line 11 and the first power line 10 are located at different layers or the same layer, and the third power supply branch line 31 and the third power supply line 30 are located at different layers.
The switching unit 42 is facilitated to be connected to the first power line 10 by providing the first power branch 11, and the switching unit 42 is facilitated to be connected to the third power line 30 by providing the third power branch 31.
Optionally, in the embodiment of the present disclosure, the detection line 41 includes a first portion 411 and a second portion 412, one end of the first portion 411 and one end of the second portion 412 are connected and extend along two adjacent sides of the display panel, the other end of the first portion 411 is connected to the second end 42b of the switch unit 42, and the other end of the second portion 412 is connected to the first end 42a of the switch unit 42.
As shown in fig. 4, the first portion 411 of the sensing line 41 extends along the left side edge of the display panel to the upper and lower edges of the display panel, and the second portion 412 of the sensing line 41 extends along the lower side edge of the display panel to the right.
By providing the first portion 411 and the second portion 412, the detection line 41 can be disposed more on the non-display area B of the display panel, so that cracks generated in the non-display area B of the display panel can be detected more comprehensively.
Alternatively, in the embodiment of the present disclosure, the sensing line 41 includes a first portion 411, and the first portion 411 may extend along one side of the display panel. Fig. 6 is a schematic structural view of another display panel provided in an embodiment of the present disclosure, and as shown in fig. 6, a first portion 411 of the inspection line 41 extends along a left side edge of the display panel to an upper edge and a lower edge of the display panel.
Optionally, in an embodiment of the disclosure, the display panel includes at least two crack detection circuits 40, where the at least two crack detection circuits 40 are respectively located on two opposite sides of the display panel. Illustratively, the display panel includes two crack detection circuits 40, the two crack detection circuits 40 being symmetrically disposed on opposite sides of the display panel.
Optionally, in the embodiment of the present disclosure, the non-display area B on each side of the display panel is provided with at least one crack detection circuit 40. One of the second end 42b and the third end 42c of the switching unit 42 in the crack detection circuit 40 of the same side is connected to the first power supply line 10. Alternatively, one of the second end 42b and the third end 42c of the switching unit 42 in the crack detection circuit 40 of the same side is connected to the second power supply line 20.
Illustratively, the non-display area B on each side of the display panel is provided with two crack detection circuits 40. The detection lines 41 in the two crack detection circuits 40 are arranged in parallel at intervals.
By redundancy design of the crack detection circuits on each side of the display panel, cracks of the display panel can be detected in case of failure of one of the crack detection circuits, for example, failure of the switching unit 42.
Optionally, in an embodiment of the present disclosure, the switching unit 42 of the display panel includes at least one TFT (Thin Film Transistor, thin film field effect transistor) 421.
When the detection line 41 is not broken, the at least 1 TFT 421 is in an off state. When the detection line 41 is broken, the at least 1 TFT 421 is in an on state, so that the first positive power supply voltage corresponding to the first power supply line 10 is pulled down, thereby reducing the display brightness of the first display area a corresponding to the first power supply line 10; alternatively, the at least 1 TFT 421 is in an on state such that the second positive power supply voltage of the second power supply line 20 is pulled down, thereby causing the display brightness of the second display region b corresponding to the second power supply line 20 to decrease. The display luminance difference between the second display region b and the sub-region of the first display region a having the same area as the second display region b becomes large. Note that the number of TFTs 421 is not particularly limited in the embodiment of the present disclosure.
In some examples, when the detection line 41 is not broken, the display luminance of the sub-region of the second display region b and the first display region a having the same area as the second display region b is substantially the same, and when the detection line 41 is broken, the display luminance of the second display region b is reduced to be lower than the display luminance of the sub-region of the first display region a having the same area as the second display region b, so that the display luminance difference between the second display region b and the sub-region of the first display region a having the same area as the second display region b becomes larger.
In other examples, when the detection line 41 is not broken, the display luminance of the sub-areas of the second display area b and the first display area a having the same area as the second display area b is substantially the same, and when the detection line 41 is broken, the display luminance of the first display area a is reduced to be lower than the display luminance of the second display area b, so that the display luminance difference between the sub-areas of the second display area b and the first display area a having the same area as the second display area b becomes larger.
Alternatively, in the embodiment of the present disclosure, at least one TFT 421 may be a P-channel field effect transistor or an N-channel field effect transistor.
When the TFT 421 is a P-channel field effect transistor, the second terminal 42b of the switching unit 42 is connected to the first power line 10 through the first power supply branch line 11, or the second terminal 42b of the switching unit 42 is connected to the second power line 20 through the second power supply branch line 21, and the third terminal 42c of the switching unit 42 is connected to the third power supply line 30 through the third power supply branch line 31.
When the TFT 421 is an N-channel field effect transistor, the second terminal 42b of the switching unit 42 is connected to the third power line 30 through the third power supply branch line 31, the third terminal 42c of the switching unit 42 is connected to the first power line 10 through the first power supply branch line 11, or the third terminal 42c of the switching unit 42 is connected to the second power line 20 through the second power supply branch line 21.
In the embodiment of the present disclosure, an exemplary explanation is made with one of the second end 42b of the switching unit 42 and the third end 42c of the switching unit 42 connected to the second power line 20 through the second power supply branch line 21.
In some embodiments, the switching unit 42 includes 1 TFT 421. The gate of the TFT 421 is the first terminal 42a of the switching unit 42, the source of the TFT 421 is the second terminal 42b of the switching unit 42, and the drain of the TFT 421 is the third terminal 42c of the switching unit 42.
In some examples, TFT 421 is a P-channel field effect transistor. Fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the disclosure. As shown in fig. 7, the TFT 421 is a P-channel field effect transistor. The second end 42b of the switching unit 42 is connected to the second power line 20 through the second power branch line 21, and the third end 42c of the switching unit 42 is connected to the third power line 30 through the third power branch line 31.
Illustratively, the second positive supply voltage of the second power supply line 20 is 6V and the negative supply voltage of the third power supply line 30 is-7V. The turn-on voltage threshold of the P-channel field effect transistor is-2.5V. The P-channel field effect transistor needs to be turned on with a voltage difference between the gate voltage and the source voltage smaller than 0 and smaller than the turn-on voltage threshold of the P-channel field effect transistor.
When the detection line 41 is not broken, both the gate voltage and the source voltage of the TFT 421 are the second positive power supply voltage 6v of the second power supply line 20, the difference between the gate voltage and the source voltage of the TFT 421 is 0, and the TFT 421 is in the off state.
When the detection line 41 breaks, for example, from the point M in fig. 6, the gate voltage of the TFT 421 is 0, the source voltage of the TFT 421 is the second positive power voltage 6v of the second power line 20, the difference between the gate voltage and the source voltage of the TFT 421 is less than 0 and less than the on-voltage threshold-2.5 v of the P-channel field effect transistor, and the TFT 421 is in an on state. When the detection line 41 breaks, the TFT 421 is turned on, so that the voltage of the second power line 20 is pulled down, thereby causing the display brightness of the second display region b corresponding to the second power line 20 to decrease. The second display region b may appear to be darkened in display brightness, not displayed (the second display region is darkened), or otherwise abnormally displayed.
In other examples, TFT 421 is an N-channel field effect transistor. Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. As shown in fig. 8, the TFT 421 is an N-channel field effect transistor. The second end 42b of the switching unit 42 is connected to the third power line 30 via the third power branch 31, and the third end 42c of the switching unit 42 is connected to the second power line 20 via the second power branch 21.
Illustratively, the second positive supply voltage of the second power supply line 20 is 6V and the negative supply voltage of the third power supply line 30 is-7V. The turn-on voltage threshold of the N-channel field effect transistor is 2.5V. The N-channel field effect transistor needs to be turned on when the voltage difference between the gate voltage and the source voltage is greater than 0 and greater than the turn-on voltage threshold of the N-channel field effect transistor.
When the detection line 41 is not broken, both the gate voltage and the source voltage of the TFT 421 are negative power supply voltage-7 v of the third power supply line 30, the difference between the gate voltage and the source voltage of the TFT 421 is 0, and the TFT 421 is in an off state.
When the detection line 41 breaks, for example, from the N point in fig. 7, the gate voltage of the TFT 421 is 0v, the source voltage of the TFT 421 is-7 v, the difference between the gate voltage and the source voltage of the TFT 421 is greater than 0 and greater than the on-voltage threshold of the N-channel field effect transistor by 2.5v, and the TFT 421 is in an on state. When the detection line 41 breaks, the TFT 421 is turned on, so that the second positive power supply voltage of the second power supply line 20 is pulled down, thereby causing the display brightness of the second display region b corresponding to the second power supply line 20 to decrease. The second display region b may appear to be darkened in display brightness, not displayed (the second display region is darkened), or otherwise abnormally displayed.
In other embodiments, the switching unit 42 includes a plurality of TFTs 421 connected in series, a source of one end of the plurality of TFTs 421 connected in series is the second end 42b of the switching unit 42, a drain of the other end of the plurality of TFTs 421 connected in series is the third end 42c of the switching unit 42, and sources and drains of two adjacent TFTs 421 are connected.
The number of the plurality of TFTs 421 is 2 or more, for example, 2 TFTs. The plurality of TFTs 421 are connected in series, which corresponds to increasing the conduction channel between the drain and the source of the TFTs 421, that is, to increasing the equivalent resistance of the TFTs 421, thereby reducing the leakage current of the TFTs 421 to achieve the reduction of the leakage current.
In some examples, the TFT is a P-channel field effect transistor. Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. As shown in fig. 9, the TFT 421 is a P-channel field effect transistor, the second terminal 42b of the switching unit 42 is connected to the second power line 20 through the second power supply branch line 21, and the third terminal 42c of the switching unit 42 is connected to the third power supply line 30 through the third power supply branch line 31. Two TFTs 421 (TFT 1 and TFT 2) are illustrated in fig. 9.
When the detection line 41 is not broken, both the gate voltage and the source voltage of the TFT1 are the second positive power supply voltage 6v of the second power supply line 20, the difference between the gate voltage and the source voltage of the TFT1 is 0, and the TFT1 is in an off state. The gate voltage of the TFT2 is the second positive power supply voltage 6v of the second power supply line 20, the source voltage of the TFT2 is 0, the difference between the gate voltage and the source voltage of the TFT2 is greater than 0, and the TFT2 is also in the off state. Therefore, when the detection line 41 is not broken, both TFT1 and TFT2 are in the off state.
When the detection line 41 breaks, the gate voltage of the TFT1 is 0, the source voltage of the TFT1 is 6v of the voltage of the second power line 20, the difference between the gate voltage and the source voltage of the TFT1 is less than 0 and less than the on-voltage threshold of the P-channel field effect transistor-2.5 v, and the TFT1 is in an on state. The gate voltage of the TFT2 is 0V, the source voltage of the TFT2 is 6V, the difference between the gate voltage and the source voltage of the TFT2 is smaller than 0 and smaller than the on voltage threshold value of the P-channel field effect transistor-2.5V, and the TFT2 is also in an on state. Therefore, when the detection line 41 breaks, both the TFT1 and the TFT2 are in the on state, so that the second positive power supply voltage of the second power supply line 20 is pulled down, thereby causing the display brightness of the display area corresponding to the second power supply line 20 to decrease. The second display region b may appear to be darkened in display brightness, not displayed (the second display region is darkened), or otherwise abnormally displayed.
In other examples, TFT 421 is an N-channel field effect transistor. Fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. As shown in fig. 10, the TFT 421 is an N-channel field effect transistor, and the second terminal 42b of the switching unit 42 is connected to the third power line 30 through the third power supply branch line 31, and the third terminal 42c of the switching unit 42 is connected to the second power supply line 20 through the second power supply branch line 21. Two TFTs are illustrated in fig. 10.
When the detection line 41 is not broken, both the gate voltage and the source voltage of the TFT2 are negative power supply voltage-7 v of the third power supply line 30, the difference between the gate voltage and the source voltage of the TFT2 is 0, and the TFT2 is in an off state. The gate voltage of the TFT1 is negative supply voltage-7 v of the third power supply line 30, the source voltage of the TFT1 is 0, the difference between the gate voltage and the source voltage of the TFT1 is less than 0, and the TFT1 is also in an off state. Therefore, when the detection line 41 is not broken, both TFT1 and TFT2 are in the off state.
When the detection line 41 breaks, the gate voltage of the TFT2 is 0v, the source voltage of the TFT2 is-7 v, the difference between the gate voltage and the source voltage of the TFT2 is greater than 0 and greater than the on-voltage threshold of the N-channel field effect transistor by 2.5v, and the TFT2 is in an on state. The gate voltage of the TFT1 is 0v, the source voltage of the TFT1 is negative power supply voltage-7 v of the third power supply line 30, the difference between the gate voltage and the source voltage of the TFT1 is greater than 0 and greater than the on-voltage threshold of the N-channel field effect transistor by 2.5v, and the TFT1 is also in an on state. Therefore, when the detection line 41 breaks, both the TFT1 and the TFT2 are in the on state, so that the second positive power supply voltage of the second power supply line 20 is pulled down, thereby causing the display luminance of the second display region b corresponding to the second power supply line 20 to decrease. The second display region b may appear to be darkened in display brightness, not displayed (the second display region is darkened), or otherwise abnormally displayed.
In the embodiment of the disclosure, whether the edge of the display panel generates a crack may be detected by observing whether the second display area of the display panel corresponding to the second power line is abnormal. The scheme has simple circuit design and can intuitively and effectively detect cracks generated at the edge of the display panel.
The embodiment of the disclosure also provides a display device, which comprises any one of the display panels.
In specific implementation, the display device provided by the embodiment of the disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
Fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 11, the display panel includes a base substrate 50, and a semiconductor layer 51, a first gate insulating layer 52, a first electrode layer 53, a second gate insulating layer 54, a second electrode layer 55, an interlayer insulating layer 56, a third electrode layer 57, a planarizing layer 58, and PDL (Pixel Definition Layer, pixel defining layer) 59, which are sequentially disposed on the base substrate 50.
Illustratively, the semiconductor layer 51 may be fabricated using a semiconductor active material P-Si or the like. The first gate insulating layer 52, the second gate insulating layer 54, and the interlayer insulating layer 56 may be made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The first electrode layer 53 and the second electrode layer 55 may be made of a metal material, such as Mo (molybdenum), cu (copper), or the like. The third electrode layer 57 may be made of a metal material such as Ti (titanium) or Al (aluminum). The planarization layer 58 and the PDL layer 59 may be made of PI (polyimide), resin, or the like.
The first power line 10 is located at the second electrode layer 55 or the third electrode layer 57, the second power line 20 is located at the second electrode layer 55, the third power line 30 is located at the first electrode layer 53, and the first power branch line 11, the second power branch line 21, the third power branch line 31 and the detection line 41 are located at the third electrode layer 57.
The gate of the switching transistor 421 is located on the first electrode layer 53, and the detection line 41 is connected to the gate of the switching transistor 421 through the via 57 a.
In some embodiments, the source of the switching transistor 421 and the drain of the switching transistor 421 are located in the semiconductor layer 51.
In some examples, the second power line 20 is connected to the second power branch line 21 through a via 57b, and the second power branch line 21 is connected to one of the second end 42b and the third end 42c of the switching unit 42 through a via 57 c. The third power supply line 30 is connected to the third power supply branch line 31 through a via 57d, and the third power supply branch line 31 is connected to the other of the second end 42b and the third end 42c of the switching unit 42 through a via 57 e.
In other examples, the first power line 10 is connected to the first power branch line 11 through the via hole 57b, and the first power branch line 11 is connected to one of the second end 42b and the third end 42c of the switching unit 42 through the via hole 57 c. The third power supply line 30 is connected to the third power supply branch line 31 through a via 57d, and the third power supply branch line 31 is connected to the other of the second end 42b and the third end 42c of the switching unit 42 through a via 57 e.
Alternatively, when the first power line 10 is located at the third electrode layer 57, the first power line 10 may be directly connected to the first power branch line, which is connected to one of the second and third ends 42b and 42c of the switching unit 42 through the via hole 57 c.
The switching transistor is arranged on the semiconductor layer, a new Mask plate (Mask) is not needed to be added, and the manufacturing cost of the display panel is saved.
In other embodiments, when the switching unit 42 includes the plurality of switching transistors 421, the sources and drains of the plurality of switching transistors 421 are located at the semiconductor layer 51 and the third electrode layer 57. In the embodiment of the present disclosure, two switching transistors 421 are exemplified.
The first pole of the first switching transistor and the second pole of the second switching transistor are located in the semiconductor layer 51, and the second pole of the first switching transistor and the first pole of the second switching transistor are located in the third electrode layer 57. The second pole of the first switching transistor is connected to the first power supply branch 11, the first power supply branch 11 is connected to the first power supply line 10 via the via 57b, or the second pole of the first switching transistor is connected to the second power supply branch 21, the second power supply branch 21 is connected to the second power supply line 20 via the via 57b, the second pole of the first switching transistor is connected to the first pole of the first switching transistor via the via 57c, the second pole of the second switching transistor is connected to the first pole of the second switching transistor via the via 57e, the first pole of the second switching transistor is connected to the third power supply branch 31, and the third power supply branch 31 is connected to the third power supply line 30 via the via 57 d.
Wherein the control electrode is a gate electrode, the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode. In some examples, the first and second switching transistors are P-channel field effect transistors, the first electrode is a drain, and the second electrode is a source. In other examples, the first and second switching transistors are N-channel field effect transistors, the first electrode is a source, and the second electrode is a drain.
In the embodiment of the disclosure, the control electrode of the first switching transistor and the control electrode of the second switching transistor are both disposed on the first electrode layer, the first electrode of the first switching transistor, the second electrode of the second switching transistor and the first electrode of the switching transistor of the pixel circuit are disposed on the third electrode layer, and the second electrode of the first switching transistor and the first electrode of the second switching transistor are disposed on the active layer. And a new Mask plate (Mask) is not required to be added, so that the manufacturing cost of the display panel is saved.
The embodiment of the disclosure also provides a manufacturing method of the display panel. Fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the disclosure, referring to fig. 12, the method includes:
In step 101, a substrate base plate is provided.
In step 102, a semiconductor layer is formed on a substrate base.
Fig. 13 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 13, a semiconductor layer 51 is located on a substrate base 50.
In step 102, a thin film of active material may be formed on a substrate base. For example, a thin film of active material may be formed on a substrate by deposition.
Then, the active material thin film is processed through a patterning process to obtain a pattern of the semiconductor layer 51. After the pattern of the semiconductor layer 51 is obtained, a portion of the region in the semiconductor layer 51 may be subjected to a metallization process, so that the metallized region forms a source and a drain, which may be the source of the TFT1 and the drain of the TFT2, or the drain of the TFT1 and the source of the TFT 2.
In step 103, a first gate insulating layer is formed on the semiconductor layer.
Fig. 14 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 14, a first gate insulating layer 52 (GI 1) is located on the active layer 51. The first gate insulating layer 52 may be formed on the semiconductor layer 51 by a CVD (Chemical Vapor Deposition ) process, for example.
In step 104, a first electrode layer is formed on the first gate insulating layer.
Fig. 15 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 15, a first electrode layer (Gate 1) 53 is located on the first Gate insulating layer 52. The first electrode layer 53 includes gates of the respective TFTs and a third power supply line. For example, a gate of TFT1, a gate of TFT2, and a third power supply line.
For example, the first electrode layer 53 may be fabricated on the first gate insulating layer 52 using a Sputer (magnetron sputtering) process or a PECVD (Plasma Enhanced Chemical Vapor Deposition, ion-enhanced chemical vapor deposition) process.
In step 105, a second gate insulating layer is formed on the first electrode layer.
Fig. 16 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 16, a second gate insulating layer 54 (GI 2) is located on the first electrode layer 53. The insulating layer 54 may be formed on the first electrode layer 53 by a CVD process, for example.
In step 106, a second electrode layer is formed on the second gate insulating layer.
Fig. 17 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 17, a second electrode layer 55 (Gate 2) is located on the second Gate insulating layer 54. The second electrode layer 55 includes a second power line. The second electrode layer 55 may be formed on the insulating layer using a Sputer process or a PECVD process, for example.
In step 107, an interlayer insulating layer is formed on the second electrode layer.
Fig. 18 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 18, an interlayer insulating layer 56 is located on the second electrode layer 55. Illustratively, an interlayer insulating layer 56 may be fabricated on the second electrode layer 55 using a CVD process.
In step 108, a second electrode layer is formed on the interlayer insulating layer.
Fig. 19 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 19, the second electrode layer 57 is located on the interlayer insulating layer 56. The second electrode layer 57 is a source and drain layer, for example, a source of TFT1 and a drain of TFT2, or a drain of TFT1 and a source of TFT 2.
The second electrode layer 57 is connected to the semiconductor layer 51, the first electrode layer 53, and the second electrode layer 54 through the via hole 57 a.
In step 109, a planarization layer is formed over the second electrode layer.
Fig. 20 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 20, a planarization layer 58 is located on the second electrode layer. Illustratively, the planarization layer 58 is used to ensure flatness between the second electrode layer 57 and the metal anode of the light emitting diode. A planarization layer may be formed on the second electrode layer by Coating (Coating) or Curing (Curing) or the like.
In step 110, a pixel defining layer is formed on the planarization layer.
The PDL layer 59 is formed by the same method as the planarization layer 58.
Fig. 21 is a process diagram of manufacturing a display panel according to an embodiment of the present disclosure. As shown in fig. 21, a PDL layer 59 is located on the planarization layer 58.
The embodiment of the disclosure also provides a crack detection method of the display panel. Fig. 22 is a flowchart of a method for detecting cracks of a display panel according to an embodiment of the present disclosure, where the method may be applied to detect cracks before shipping the display panel or during normal use of the display panel by a user. As shown in fig. 22, the method includes:
in step 201, the display panel is controlled to display.
In step 202, it is determined whether a crack occurs in the display panel according to the display luminance of the second display area and the display luminance of the first display area.
In some embodiments, when the detection line is not broken, there is substantially no difference in display brightness between the second display region and a sub-region of the same area as the second display region in the first display region. Step 202 comprises: the display brightness difference between the second display area and the subareas of the same area as the second display area in the first display area becomes large, and the display panel is determined to be cracked.
In other embodiments, step 202 comprises: and the display brightness of the second display area is smaller than that of a subarea which is equal to the area of the second display area in the first display area, so that the display panel is determined to be cracked.
In an embodiment of the disclosure, a display panel includes a first power line, a second power line, a third power line, and a crack detection circuit located in a non-display area. The crack detection circuit comprises a detection line and a switch unit. One end of the detection line is connected with the first end of the switch unit, the other end of the detection line is connected with the second end of the switch unit, one of the second end and the third end of the switch unit is connected with the second power line, and the other of the second end and the third end of the switch unit is connected with the third power line. Because the first power line provides a first positive power voltage for the pixels in the first display area, the second power line provides a second positive power voltage for the pixels in the second display area, the third power line provides a negative power voltage for the display panel, when the detection line breaks, the switch unit is turned on, and the voltage of the second power line can be pulled down by the switch unit, so that the display brightness difference between the second display area and the subareas with the same area as the second display area in the first display area is increased. Thus, whether or not a crack occurs in the display panel can be determined based on the difference in display luminance between the first display region and the second display region. According to the embodiment of the disclosure, the crack detection of the display panel can be completed by only utilizing the original first power line, the second power line and the third power line of the display panel, and other signal lines are not required to be additionally arranged, so that the structure of a crack detection circuit of the display panel is simplified.
The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, any modification, equivalent replacement, improvement, etc. that comes within the spirit and principles of the present disclosure are included in the scope of the present disclosure.
Claims (10)
1. A display panel, wherein the display panel has a non-display area, a first display area and a second display area, the first display area surrounding the second display area, the non-display area surrounding the first display area;
the display panel comprises a first power line (10), a second power line (20), a third power line (30) and a crack detection circuit (40) which are positioned in the non-display area;
the first power supply line (10) is for providing a first positive power supply voltage for pixels in the first display area, the second power supply line (20) is for providing a second positive power supply voltage for pixels in the second display area, the third power supply line (30) is for providing a negative power supply voltage for the display panel, the first positive power supply voltage being smaller than the second positive power supply voltage;
the crack detection circuit (40) comprises a detection line (41) and a switch unit (42), wherein the switch unit (42) is provided with a first end, a second end and a third end; one end of the detection line (41) is connected with a first end of the switch unit (42), and the other end of the detection line (41) is connected with a second end of the switch unit (42); one of a second end and a third end of the switching unit (42) is connected to one of the first power line (10) and the second power line (20), and the other of the second end and the third end of the switching unit (42) is connected to the third power line (30);
The switching unit (42) is configured to turn on the second terminal and the third terminal when the detection line (41) is broken.
2. The display panel according to claim 1, wherein the sensing line (41) includes a first portion (411) and a second portion (412), one end of the first portion (411) and one end of the second portion (412) are connected and extend along adjacent two sides of the display panel, respectively, and the other end of the first portion is connected to the second end of the switching unit (42) and the other end of the second portion is connected to the first end of the switching unit (42).
3. The display panel according to claim 1 or 2, wherein the switching unit (42) comprises a switching transistor (421), the gate of the switching transistor (421) being the first terminal of the switching unit (42), the source of the switching transistor (421) being the second terminal of the switching unit (42), the drain of the switching transistor (421) being the third terminal of the switching unit (42); or,
the switching unit (42) comprises a plurality of switching transistors (421) connected in series, a source of one end of each of the plurality of switching transistors (421) connected in series is a second end of the switching unit (42), a drain of the other end of each of the plurality of switching transistors (421) connected in series is a third end of the switching unit (42), and sources and drains of two adjacent switching transistors (421) are connected.
4. A display panel according to claim 3, characterized in that one of the second and third ends of the switching unit (42) is connected to the second power supply line (20) via a second power supply branch (21), the other of the second and third ends of the switching unit (42) is connected to the third power supply line (30) via a third power supply branch (31), the second power supply branch (21) and the second power supply line (20) are located in different layers, and the third power supply branch (31) and the third power supply line (30) are located in different layers.
5. A display panel according to claim 3, characterized in that one of the second and third ends of the switching unit (42) is connected to the first power supply line (10) via a first power supply branch (11), the other of the second and third ends of the switching unit (42) is connected to the third power supply line (30) via a third power supply branch (31), the first power supply branch (11) and the first power supply line (10) are located in the same layer or in different layers, and the third power supply branch (31) and the third power supply line (30) are located in different layers.
6. The display panel according to claim 1, characterized in that the display panel comprises at least two crack detection circuits (40), the two crack detection circuits (40) being located on opposite sides of the display panel, respectively.
7. The display panel according to claim 4, characterized in that the display panel comprises a substrate base plate (50) and a semiconductor layer (51), a first gate insulating layer (52), a first electrode layer (53), a second gate insulating layer (54), a second electrode layer (55), an interlayer insulating layer (56), a third electrode layer (57), a planarization layer (58) and a pixel defining layer (59) which are sequentially located on the substrate base plate (50);
the first power line (10) is located at the second electrode layer (55) or the third electrode layer (57), the second power line (20) is located at the second electrode layer (55), the third power line (30) is located at the first electrode layer (53), and the second power branch line (21), the third power branch line (31) and the detection line (41) are located at the third electrode layer (57);
the grid electrode of the switch transistor (421) is positioned on the first electrode layer (53), and the detection line (41) is connected with the grid electrode of the switch transistor (421) through a via hole;
-the source of the switching transistor (421) and the drain of the switching transistor (421) are located in the semiconductor layer (51);
the second power line (20) is connected with the second power branch line (21) through a via hole, and the second power branch line (21) is connected with one of a second end and a third end of the switch unit (42) through the via hole;
The third power line (30) is connected with the third power branch line (31) through a via hole, and the third power branch line (31) is connected with the other of the second end and the third end of the switch unit (42) through a via hole.
8. The display panel according to claim 5, characterized in that the display panel comprises a substrate base plate (50) and a semiconductor layer (51), a first gate insulating layer (52), a first electrode layer (53), a second gate insulating layer (54), a second electrode layer (55), an interlayer insulating layer (56), a third electrode layer (57), a planarization layer (58) and a pixel defining layer (59) which are sequentially located on the substrate base plate (50);
the first power line (10) is located at the second electrode layer (55) or the third electrode layer (57), the second power line (20) is located at the second electrode layer (55), the third power line (30) is located at the first electrode layer (53), and the first power branch line (11), the third power branch line (31) and the detection line (41) are located at the third electrode layer (57);
the grid electrode of the switch transistor (421) is positioned on the first electrode layer (53), and the detection line (41) is connected with the grid electrode of the switch transistor (421) through a via hole;
-the source of the switching transistor (421) and the drain of the switching transistor (421) are located in the semiconductor layer (51);
The first power line (10) is connected with the first power branch line (11) through a via hole, and the first power branch line (11) is connected with one of the second end and the third end of the switch unit (42) through the via hole; alternatively, the first power line (10) is connected to the first power branch line (11), and the first power branch line (11) is connected to one of the second end and the third end of the switching unit (42) through a via hole;
the third power line is connected with the third power branch line (31) through a via hole, and the third power branch line (31) is connected with the other of the second end and the third end of the switch unit (42) through a via hole.
9. A display device, characterized in that the display device comprises the display panel of any one of claims 1 to 8.
10. A crack detection method applied to the display panel according to any one of claims 1 to 8, the method comprising:
controlling the display panel to display;
and determining whether the display panel has cracks or not according to the display brightness of the second display area and the display brightness of the first display area.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257571A (en) * | 2015-06-16 | 2016-12-28 | 三星显示有限公司 | Display device |
| CN111696459A (en) * | 2020-05-26 | 2020-09-22 | 京东方科技集团股份有限公司 | Detection module, crack detection method, display panel and display device |
| CN112397557A (en) * | 2019-08-19 | 2021-02-23 | 三星显示有限公司 | Electronic panel and electronic device including the same |
| CN113466252A (en) * | 2020-03-30 | 2021-10-01 | 昆山国显光电有限公司 | Display panel, detection method of display panel and display device |
| CN113655646A (en) * | 2021-08-16 | 2021-11-16 | 京东方科技集团股份有限公司 | Display panel, display module and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200105574A (en) * | 2019-02-28 | 2020-09-08 | 삼성디스플레이 주식회사 | Sencer unit, display device including the sensor unit and device and crack detection method using thereof |
| CN110264951B (en) * | 2019-07-22 | 2021-01-22 | 京东方科技集团股份有限公司 | Organic electroluminescent display panel, display device and detection method |
-
2021
- 2021-12-27 CN CN202111619077.3A patent/CN114241963B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257571A (en) * | 2015-06-16 | 2016-12-28 | 三星显示有限公司 | Display device |
| CN112397557A (en) * | 2019-08-19 | 2021-02-23 | 三星显示有限公司 | Electronic panel and electronic device including the same |
| CN113466252A (en) * | 2020-03-30 | 2021-10-01 | 昆山国显光电有限公司 | Display panel, detection method of display panel and display device |
| CN111696459A (en) * | 2020-05-26 | 2020-09-22 | 京东方科技集团股份有限公司 | Detection module, crack detection method, display panel and display device |
| CN113655646A (en) * | 2021-08-16 | 2021-11-16 | 京东方科技集团股份有限公司 | Display panel, display module and display device |
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