CN114238127A - Interface test method, device, equipment and storage medium - Google Patents

Interface test method, device, equipment and storage medium Download PDF

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Publication number
CN114238127A
CN114238127A CN202111570825.3A CN202111570825A CN114238127A CN 114238127 A CN114238127 A CN 114238127A CN 202111570825 A CN202111570825 A CN 202111570825A CN 114238127 A CN114238127 A CN 114238127A
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China
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interface
tested
target processor
sequence
data
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CN202111570825.3A
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张立国
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China Construction Bank Corp
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China Construction Bank Corp
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Priority to CN202111570825.3A priority Critical patent/CN114238127A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites

Abstract

The application relates to the technical field of testing, in particular to an interface testing method, device, equipment and storage medium, wherein the method is applied to a control processor and comprises the following steps: the method comprises the steps of obtaining a preset configuration file of an interface test and an original to-be-tested data group containing at least one original to-be-tested data, analyzing the preset configuration file, obtaining a processor execution list comprising at least one target processor and a target processor execution sequence and an interface calling list comprising at least one interface and each interface calling sequence, calling each interface in sequence according to the target processor execution sequence, each interface calling sequence and the original to-be-tested data group to realize that each target processor processes the corresponding original to-be-tested data in sequence, and obtaining the state of each interface in sequence, so that at least one interface is called in sequence in one interface test process to obtain the state of each to-be-tested interface, and the efficiency of the interface test is improved.

Description

Interface test method, device, equipment and storage medium
Technical Field
The present application relates to the field of test technologies, and in particular, to an interface test method, apparatus, device, and storage medium.
Background
The interface test is a process of simulating that a client sends a request message to a server by calling an interface, the server processes the corresponding message after receiving the request message and returns a response to the client, and the client receives the response again to check the safety and the stability of the system.
In the prior art, when a user performs an interface test each time, the user needs to prepare corresponding data according to configuration information and data information required by a system corresponding to each interface to be tested, and calls the corresponding interfaces respectively according to an execution sequence of the system, so as to obtain a state of the interface to be tested in a process of testing the interface once, which results in low efficiency of the process of testing the interface.
Therefore, how to improve the efficiency of the interface test becomes an urgent problem to be solved.
Disclosure of Invention
The application provides an interface testing method, an interface testing device, equipment and a storage medium, which are used for solving the technical problem of improving the interface testing efficiency.
In a first aspect, the present application provides an interface testing method, where the method is applied to a control processor, and the method includes:
acquiring a preset configuration file of an interface test and an original data set to be tested; the original data group to be tested comprises at least one original data to be tested;
analyzing a preset configuration file to obtain a processor execution list and an interface calling list; the processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence;
and sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested so as to realize that each target processor processes the corresponding original data to be tested according to the sequence and sequentially obtain the state of each interface.
In the technical scheme, the control processor calls and tests the interfaces to be tested in sequence according to the processor execution list and the interface call list in the preset configuration file, so that the states of all the interfaces to be tested are obtained in the process of testing the interfaces once, and the efficiency of interface testing is improved.
Optionally, sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface, and the original data group to be tested to realize that each target processor processes the corresponding original data to be tested according to the sequence, and sequentially obtaining the state of each interface, specifically including:
according to the execution sequence of the target processor, the calling sequence of each interface and the original data set to be tested, calling each interface in sequence to realize that each target processor processes corresponding original data to be tested according to the sequence and obtain corresponding test result data through each interface;
and comparing the test result data with the preset result data to obtain the state of each interface.
Optionally, when the number of the interfaces is 1, sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface, and the original data group to be tested to realize that each target processor processes the corresponding original data to be tested in sequence, and obtaining the corresponding test result data through each interface, specifically including:
analyzing intermediate data to be tested and instructions to be executed of each target processor from the original data group to be tested;
transmitting the intermediate data to be tested and the instruction to be executed to a target processor through calling of an interface;
and after the target processor executes the corresponding to-be-executed instruction by using the to-be-tested intermediate data according to the execution sequence of the target processor, obtaining the test result data returned from the interface.
Optionally, the target processor comprises a preprocessing unit and a main body processing unit; after the target processor executes the corresponding to-be-executed instruction by using the to-be-tested intermediate data according to the execution sequence of the target processor, obtaining test result data returned from the interface, specifically including:
sending the intermediate data group to be tested to the preprocessing unit so as to analyze the data to be tested which can be processed by the main body processing unit from the intermediate data to be tested by using the preprocessing unit;
after the preprocessing unit sends the data to be tested to the main body processing unit so that the main body processing unit executes the corresponding instruction to be executed, the test result data generated by the main body processing unit is obtained from the interface.
Optionally, the method further comprises:
and sending the intermediate data to be tested to the preprocessing unit, analyzing the environmental parameters required by the main body processing unit for building the logic processing environment from the intermediate data to be tested by using the preprocessing unit, and transmitting the environmental parameters to the main body processing unit to realize building of the operation environment of the instruction to be executed.
Optionally, when the number of the interfaces is multiple, the interfaces include a first interface and a second interface; according to the execution sequence of the target processor, the calling sequence of each interface and the original data set to be tested, calling each interface in sequence to realize that each target processor processes corresponding original data to be tested according to the sequence and obtains corresponding test result data through each interface, the method specifically comprises the following steps:
analyzing intermediate data to be tested and instruction groups to be executed of each target processor from the original data groups to be tested;
the method comprises the steps that a first interface is called to transmit a first intermediate sub data group to be tested in intermediate data to be tested to a target processor, so that the target processor obtains a second intermediate sub data group to be tested, which is generated by the target processor, after the target processor finishes processing the first intermediate sub data group to be tested according to a first instruction to be executed in an instruction group to be executed;
and acquiring an instruction according to the second intermediate sub data group to be tested, and transmitting corresponding data to the target processor by calling the second interface so that the target processor acquires test result data from the second interface after finishing processing the second intermediate sub data group to be tested according to a second instruction to be executed in the instruction group to be executed.
Optionally, the method further comprises:
and sending a test ending instruction to the target processor to control the target processor to complete the processing flow of the preset logic processing.
In the technical scheme, the control processor analyzes original data to be tested into intermediate data to be tested, wherein the intermediate data to be tested comprises required data, environment data and instructions to be executed of each interface to be tested, obtains a calling sequence of the target processor and the interfaces to be tested according to a preset configuration file, sequentially transmits the intermediate data to be tested to the target processor, controls the target processor to process corresponding data according to the instructions to be executed, and sequentially judges the state of the called interface according to returned result data, so that the state test of at least one interface to be tested is realized, and the efficiency of interface test is improved.
In a second aspect, the present application provides an interface testing apparatus, comprising:
the acquisition module is used for acquiring a preset configuration file of the interface test and an original data set to be tested; the original data group to be tested comprises at least one original data to be tested;
the processing module is used for analyzing a preset configuration file to obtain a processor execution list and an interface calling list; the processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence;
the processing module is further used for sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested so as to realize that each target processor processes the corresponding original data to be tested according to the sequence and sequentially obtain the state of each interface.
In a third aspect, the present application provides an electronic device, comprising: a control processor and a memory communicatively coupled to the control processor;
the memory stores computer-executable instructions;
the control processor executes computer-executable instructions stored in the memory to implement the interface testing method according to the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored, and the computer instructions are executed by a processor to implement the interface testing method according to the first aspect.
The application provides an interface test method, an interface test device, equipment and a storage medium, wherein the method is applied to a control processor and comprises the following steps: the method comprises the steps of obtaining a preset configuration file of an interface test and an original to-be-tested data group containing at least one original to-be-tested data, analyzing the preset configuration file, obtaining a processor execution list comprising at least one target processor and a target processor execution sequence and an interface calling list comprising at least one interface and each interface calling sequence, calling each interface in sequence according to the target processor execution sequence, each interface calling sequence and the original to-be-tested data group to realize that each target processor processes the corresponding original to-be-tested data in sequence, and obtaining the state of each interface in sequence, so that at least one interface is called in sequence in one interface test process to obtain the state of each to-be-tested interface, and the efficiency of the interface test is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is an application scenario diagram of an interface testing method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of an interface testing method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of an interface testing method according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of an interface testing apparatus according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of an interface test system according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The interface test is a process of simulating that a client sends a request message to a server by calling an interface, the server processes the corresponding message after receiving the request message and returns a response to the client, and the client receives the response again to check the safety and the stability of the system.
In the prior art, when a user performs an interface test each time, the user needs to prepare corresponding data according to configuration information and data information required by a system corresponding to each interface to be tested, and calls the corresponding interfaces respectively according to an execution sequence of the system, so as to obtain a state of the interface to be tested in a process of testing the interface once, which results in low efficiency of the process of testing the interface.
Therefore, how to improve the efficiency of the interface test becomes an urgent problem to be solved.
In view of the foregoing technical problems, embodiments of the present application provide an interface testing method, apparatus, device, and storage medium, which aim to solve the problem of improving the efficiency of interface testing. The technical idea of the application is as follows: and calling the interfaces to be tested in sequence according to the configuration file and the preset original data to be tested, and controlling the target processor to execute corresponding operation so as to test at least one interface in the built-in system of the target processor in one-time test process, thereby improving the efficiency of interface test.
Fig. 1 is a block diagram of an engine control system provided in the present application, as shown in fig. 1, including an electronic device 10 and a data server 20. Wherein, electronic equipment 10 includes: the system comprises a control processor 11 and a target processor 12, wherein the target processor 12 is provided with a system to be tested, the system is provided with at least one interface for interaction, when the interface is tested, a corresponding interface test can be carried out through an interface test system built in the control processor 11, namely, the control processor transfers required parameters to the target processor by calling the interface of the target processor, and obtains data returned from the interface of the target processor after the target processor carries out corresponding operation according to built-in logic, and the control processor judges whether the applied interface is in a normal state or not according to a preset result and the returned data.
During the interface test, the data required by the control processor 11 and the target processor 12 may be obtained directly by calling the data stored locally in the electronic device 10, or may be obtained by remotely calling the data stored in the data server 20.
Fig. 2 is a schematic flowchart of an interface testing method according to an exemplary embodiment of the present application. As shown in fig. 2, the interface testing method provided by the present application includes:
s201, the control processor obtains a preset configuration file of the interface test and an original data set to be tested.
The preset configuration file is a configuration file stored locally that can be called by an interface test tool installed in the control processor. The configuration file comprises a processor which is associated with the system of the interface to be tested and performs corresponding operation according to the data obtained by the test interface and the calling sequence of the processor.
More specifically, the preset configuration file further includes relevant parameters required by the processor during operation.
Interface test tools installed in the control processor include, but are not limited to: meter, Loadrunner, Postman, soap ui.
The original data group to be tested is a data group required by a target processor of a system corresponding to a built-in interface to be tested in the running process, and the data group comprises at least one original data to be tested. The system corresponding to the interface to be tested is different, and the type and the content of the original data to be tested are different.
S202, the control processor analyzes the preset configuration file to obtain a processor execution list and an interface calling list.
Wherein the preset configuration file is obtained from step S201.
The control processor analyzes the preset configuration file refers to the control processor extracting necessary information in the preset configuration file, so that an interface testing tool in the control processor can perform corresponding interface testing according to the necessary information. The necessary information refers to information required by a system where the interface to be tested is located in the operation process.
More specifically, the necessary information includes a processor execution list and an interface call list.
The processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence.
S203, the control processor calls the interfaces in sequence according to the execution sequence of the target processor, the calling sequence of the interfaces and the original data set to be tested so as to realize that the target processor processes the corresponding original data to be tested in sequence and obtains the states of the interfaces in sequence.
Wherein, the target processor execution sequence and each interface calling sequence are obtained from step S202, and the original data set to be tested is obtained from step S201.
The step of calling the interfaces in sequence means that the target processors perform sequential operation according to an execution sequence, and when the currently executed target processor needs to acquire instructions or data transmitted by the current interface, the control processor executes corresponding operation in a calling mode, so that the target processor is controlled to finish executing a system processing flow corresponding to the interface to be tested.
The state of each interface includes a normal state and an abnormal state. According to different modes of generating the exception, the interface in the exception state returns the exception code corresponding to the exception state to the control processor. The exception status and the corresponding exception code are prior art and will not be described herein.
In the technical scheme, the control processor calls and tests the interfaces to be tested in sequence according to the processor execution list and the interface call list in the preset configuration file, so that the states of all the interfaces to be tested are obtained in the process of testing the interfaces once, and the efficiency of interface testing is improved.
Fig. 3 is a flowchart illustrating an interface testing method according to an embodiment of the present application, in which an execution subject of the method is a control processor. As shown in fig. 3, the interface testing method provided by the present application includes:
s301, acquiring a preset configuration file of the interface test and an original data set to be tested.
The explanation of the preset configuration file and the original data set to be tested and the process of acquiring the data and the file are explained in detail in step S201, and are not described herein again.
S302, analyzing the preset configuration file to obtain a processor execution list and an interface calling list.
The processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence.
More specifically, the parsing of the configuration file is explained in detail in step S202, and is not described here.
And S303, sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested to realize that each target processor processes corresponding original data to be tested according to the sequence and obtain corresponding test result data through each interface.
The execution order of the target processor and the call order of each interface are obtained from step S302.
The method includes the steps that according to an execution sequence of a target processor, a calling sequence of each interface and an original data group to be tested, the interfaces are called in sequence to enable the target processor to process corresponding original data to be tested according to the sequence, namely, the control processor determines the target processor which executes operation currently according to the execution sequence of the target processor, and when the target processor sends a request to the control processor through the interfaces, the control processor calls the target processor according to the calling sequence of the interfaces to enable the target processor which sends the request to transmit corresponding data or instructions. Wherein the data may be data in the original data set to be tested in one embodiment, and may be data separately input by a user through an interface test tool installed in the target processor in another embodiment. The interface testing tool is explained in detail in step S201, and is not described herein.
The interface test method is divided into two cases according to the number of tested interfaces:
when the number of the interfaces is 1, sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested to realize that each target processor processes the corresponding original data to be tested according to the sequence, and acquiring the corresponding test result data through each interface specifically comprises steps S3031 to S3033:
s3031, analyzing the intermediate data to be tested and the instruction to be executed of each target processor from the original data group to be tested.
Wherein the original data set to be tested is obtained from step S301.
The intermediate data to be tested is all data sets required by the operation of each target processor, and the data sets comprise protocol configuration data for controlling the communication mode of the processor and the target processors, environment data required by the target processors for executing the instructions to be executed and data to be tested.
The to-be-executed instruction refers to a series of execution instructions that the target processor needs to perform in order to process instructions and/or data that are introduced by the called to-be-tested interface.
S3032, transmitting the intermediate data to be tested and the instruction group to be executed to the target processor through the call of the interface.
Wherein, the intermediate data to be tested and the instruction to be executed are obtained from step S3031.
More specifically, the control processor transmits the intermediate data to be tested to the corresponding target processor according to the processing requirement of the target processor.
S3033, after the target processor executes the corresponding to-be-executed instruction by using the to-be-executed intermediate data according to the execution sequence of the target processor, obtaining the test result data returned from the interface.
The execution sequence of the target processor is the target processor execution sequence that the control processor retrieves from the configuration file.
And the target processor executes corresponding instructions to be executed according to the execution sequence, wherein the instructions to be executed refer to that the target processor processes corresponding intermediate data to be tested according to locally stored preset logic. The preset logic execution sequence of the target processor comprises at least one execution stage, and when one execution stage is completed, the target processor returns corresponding test result data through a corresponding interface.
More specifically, the target processor includes a preprocessing unit and a main body processing unit.
The specific process of acquiring the test result data includes steps S30331 to S30333:
s30331, sending the intermediate data to be tested to the preprocessing unit, analyzing the environmental parameters required by the main processing unit for building the logic processing environment from the intermediate data to be tested by using the preprocessing unit, and transmitting the environmental parameters to the main processing unit to realize building of the instruction running environment to be executed.
Wherein the intermediate data to be tested is obtained from step S3031.
The preprocessing unit is a unit which performs corresponding preparation operations for the main body processing unit to be able to normally execute according to a preset logic sequence. The preparation operation includes, but is not limited to, a data preparation operation and an environment construction operation. The data preparation operation is to convert the intermediate data to be tested into data which can be directly called and processed by a main body processing unit in the target processor.
The environment construction means that the construction of the environment corresponding to the preset logic processing can be realized by inputting an environment construction instruction and related environment setting parameters in a system installed in a target processor, that is, the logic processing executed by the target processing is different, the required operating environment is also different, and the acquisition of the corresponding environment instruction and parameters and the environment construction need to be performed according to the corresponding processing.
More specifically, after the target processor environment building is completed, the target processor returns environment building success information to the control processor through the interface.
S30332, sending the intermediate data group to be tested to the preprocessing unit so as to analyze the data to be tested which can be processed by the main body processing unit from the intermediate data to be tested by using the preprocessing unit.
The analysis of the to-be-tested data that can be processed by the main body processing unit from the to-be-tested intermediate data by using the preprocessing unit is explained in detail in step S30331, and is not described herein again.
S30333, after the preprocessing unit sends the data to be tested to the main body processing unit so that the main body processing unit executes the corresponding instruction to be executed, the test result data generated by the main body processing unit is obtained from the interface.
Wherein, the instruction to be executed by the main body processing unit is acquired from step S3031.
And the main body execution unit calls the corresponding to-be-tested data stored in the local preset logic processing according to the to-be-executed instruction. The preset logics can be a plurality of groups in the theme execution unit, and when the execution of each group of preset logics is finished, the main execution unit obtains corresponding test intermediate result data. And when all the preset logics corresponding to the to-be-executed instruction are completely executed, the main body execution unit obtains final test result data.
And after the main body processing unit in the target processor obtains the test result data, returning the test result data to the control processor in a return value mode through an interface called by the control processor.
After this step is completed, the flow proceeds to step S304.
When the number of the interfaces is multiple, in an embodiment, the number of the interfaces is 2, and the interfaces include a first interface and a second interface. The process of sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested to realize that each target processor processes the corresponding original data to be tested according to the sequence and obtain the corresponding test result data through each interface specifically comprises steps S3034 to S3036:
s3034, analyzing the intermediate data to be tested and the instruction group to be executed of each target processor from the original data group to be tested.
The interpretation and obtaining of the intermediate data to be tested and the instruction to be executed are explained in detail in step S3031, and are not described herein again.
The instruction group to be executed is a set of different instructions to be executed according to different intermediate data to be tested called by each interface of the target processor.
S3035, the first to-be-tested intermediate sub data group in the intermediate data to be tested is transmitted to the target processor by calling the first interface, so that the target processor obtains a second to-be-tested intermediate sub data group obtaining instruction generated by the target processor after the target processor finishes processing the first to-be-tested intermediate sub data group according to the first to-be-executed instruction in the to-be-executed instruction group.
Wherein, the data to be tested and the instruction group to be executed are obtained from step S3034.
The first intermediate child data to be tested includes but is not limited to: the system comprises protocol configuration data of a communication mode of a control processor and a target processor, environment data required by the target processor to execute a first instruction to be executed and data to be tested.
The first to-be-executed instruction processing first to-be-tested intermediate sub-data set comprises the steps of constructing the first to-be-executed instruction environment and executing preset logic processing corresponding to the first to-be-executed instruction. The environment is built in the same way as in step S30331, and the execution of the first instruction to be executed is the same as in step S30333, which are not described herein again.
And when the first to-be-executed instruction is finished, acquiring data for executing a subsequent stage from a second interface, and acquiring an instruction by the target processor according to a second to-be-tested intermediate sub data set generated by the requirement.
S3036, obtaining the instruction according to the second intermediate sub-data group to be tested, and transmitting the corresponding data to the target processor by calling the second interface so that the target processor obtains the test result data from the second interface after finishing processing the second intermediate sub-data group to be tested according to the second instruction to be executed in the instruction group to be executed.
Wherein, the second intermediate sub-data group to be tested obtaining instruction is obtained from step S3035.
The step of calling the second interface to transmit the corresponding data to the target processor and the step of processing the second intermediate sub data set to be tested by the target processor according to the second instruction to be executed in the instruction set to be executed is the same as the step of calling the first interface to transmit the first intermediate sub data set to be tested in the intermediate data to be tested to the target processor and the step of processing the first intermediate sub data set to be tested by the target processor according to the first instruction to be executed in the instruction set to be executed in step S3035, and details are not repeated here.
And after the second to-be-executed instruction is executed and the test result data is obtained, the test result data is returned to the control processor in a return value mode through a second interface called by the control processor.
S304, comparing the test result data with the preset result data to obtain the state of each interface.
The test result data is obtained from step S303, and the preset result data is the preset result data stored in the memory that can be called by the control processor.
The control processor compares the test result data with the preset result data through a built-in assertion program, and judges the state of each interface according to whether the comparison results are consistent, namely if the judgment results are consistent, the result to be tested is in a normal state, otherwise, the result is in an abnormal state.
The states of the interfaces are explained in detail in step S203, and are not described in detail here.
S305, sending a test ending instruction to the target processor to control the target processor to complete the processing flow of the preset logic processing.
After obtaining the states of the interfaces in step S304, the control processor sends a test end instruction to the target processor to control the target processor to complete the currently running program. And after the operation is finished, cleaning the test data acquired by the target processor for executing the interface test so as to ensure the storage utilization rate of a memory in the equipment where the target processor is located.
In the technical scheme, the control processor analyzes original data to be tested into intermediate data to be tested, wherein the intermediate data to be tested comprises required data, environment data and instructions to be executed of each interface to be tested, obtains a calling sequence of the target processor and the interfaces to be tested according to a preset configuration file, sequentially transmits the intermediate data to be tested to the target processor, controls the target processor to process corresponding data according to the instructions to be executed, and sequentially judges the state of the called interface according to returned result data, so that the state test of at least one interface to be tested is realized, and the efficiency of interface test is improved.
Fig. 4 is a schematic structural diagram of an interface testing apparatus according to another embodiment of the present application. As shown in fig. 4, the interface test apparatus 400 includes:
the obtaining module 401 is configured to obtain a preset configuration file for interface testing and an original data set to be tested. The original data group to be tested comprises at least one original data to be tested.
The processing module 402 is configured to parse the preset configuration file to obtain a processor execution list and an interface call list. The processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence.
The processing module 402 is further configured to sequentially call the interfaces according to the execution sequence of the target processor, the call sequence of the interfaces, and the original data group to be tested, so that the target processors sequentially process the corresponding original data to be tested, and sequentially obtain the states of the interfaces.
Fig. 5 is a schematic structural diagram of an interface test system according to an embodiment of the present application. As shown in fig. 5, interface test system 500 includes a control processor 501 and a target processor 502. The control processor 501 includes an obtaining module 5011, a parsing module 5012, and an assertion processing module 5013, and the target processor 502 includes a pre-processing unit 5021, a core processing unit 5022, and a post-processing unit 5023.
The obtaining module 5011 has the same function as the obtaining module 401 in the interface testing apparatus, and is not described herein again.
The parsing module 5012 is configured to parse the preset configuration file and the original to-be-tested data set acquired by the acquiring module 5011 to obtain a processor execution list, an interface call list, to-be-tested intermediate data required by each interface, and to-be-executed instructions of the target processor.
The assertion processing module 5013 is configured to sequentially invoke each interface and control the corresponding target processor to execute the corresponding to-be-executed instruction according to the processor execution list and the interface invocation list obtained by the analyzing module 5012.
The pre-processing unit 5021 in the target processor 502 is used for obtaining the intermediate data to be tested after the control processor 501 calls the interface, and analyzing the data to obtain the running environment parameters and the data to be tested of the target processor 502.
The pre-processing unit 5021 is also used for building a corresponding operating environment by using the environment parameters.
The core processing unit 5022 processes the data to be tested, which is obtained by the pre-processing unit 5021 by the to-be-executed instruction obtained by the pre-processing unit 5021, to obtain corresponding test result data.
The assertion processing module 5013 is further configured to compare test result data returned by the target processor through the interfaces after the interfaces are called with a preset result stored in the memory and directly called by the control processor 501, so as to determine states of the interfaces.
After the assertion processing interface 5013 determines the status of the interface to be tested, the post-processing unit 5023 in the target processor 502 ends the status of executing the instruction to be executed in the target processor 502 and clears the data stored in the memory and utilized and stored by the target processor during the testing process.
As shown in fig. 6, an embodiment of the present application provides an electronic device 600, and the electronic device 600 includes a memory 601 and a control processor 602.
Wherein the memory 601 is used for storing computer instructions executable by the processor;
the control processor 602, when executing computer instructions, performs the steps in the interface testing method in the embodiments described above. Reference may be made in particular to the description relating to the method embodiments described above.
Alternatively, the memory 601 may be separate or integrated with the control processor 602. When the memory 601 is separately provided, the control device 600 further includes a bus for connecting the memory 601 and the control processor 602.
The embodiment of the present application further provides a computer-readable storage medium, in which computer instructions are stored, and when the processor executes the computer instructions, the steps in the interface testing method in the foregoing embodiment are implemented.
The embodiment of the present application further provides a computer program product, which includes computer instructions, and the computer instructions, when executed by a processor, implement the steps in the interface testing method in the foregoing embodiment.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. An interface testing method, applied to a control processor, the method comprising:
acquiring a preset configuration file of an interface test and an original data set to be tested; the original data group to be tested comprises at least one original data to be tested;
analyzing the preset configuration file to obtain a processor execution list and an interface calling list; the processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence;
and sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested so as to realize that each target processor processes corresponding original data to be tested according to the sequence and sequentially obtain the state of each interface.
2. The method of claim 1, wherein sequentially calling the interfaces according to the execution sequence of the target processor, the calling sequence of the interfaces, and the original data set to be tested to realize that the target processors process the corresponding original data to be tested according to the sequence and sequentially obtain the states of the interfaces specifically comprises:
sequentially calling each interface according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested so as to realize that each target processor processes corresponding original data to be tested according to the sequence and obtain corresponding test result data through each interface;
and comparing the test result data with preset result data to obtain the state of each interface.
3. The method according to claim 2, wherein when the number of the interfaces is 1, sequentially calling the interfaces according to the execution sequence of the target processor, the calling sequence of the interfaces, and the original data group to be tested to realize that the target processor processes the corresponding original data to be tested according to the sequence, and obtain the corresponding test result data through the interfaces specifically includes:
analyzing intermediate data to be tested and instructions to be executed of each target processor from the original data group to be tested;
transmitting the intermediate data to be tested and the instruction to be executed to a target processor through the call of the interface;
and after the target processor executes the corresponding to-be-executed instruction by using the to-be-tested intermediate data according to the execution sequence of the target processor, obtaining test result data returned from the interface.
4. The method of claim 3, wherein the target processor comprises a pre-processing unit and a main body processing unit; after the target processor executes the corresponding to-be-executed instruction by using the to-be-tested intermediate data according to the execution sequence of the target processor, obtaining test result data returned from the interface, specifically including:
sending the intermediate data group to be tested to the preprocessing unit so as to analyze the data to be tested which can be processed by the main body processing unit from the intermediate data to be tested by using the preprocessing unit;
and after the preprocessing unit sends the data to be tested to the main body processing unit so that the main body processing unit executes the corresponding instruction to be executed, acquiring the test result data generated by the main body processing unit from the interface.
5. The method of claim 4, further comprising:
and sending the intermediate data to be tested to the preprocessing unit, so that the preprocessing unit is utilized to analyze the environmental parameters required by the main body processing unit for building a logic processing environment from the intermediate data to be tested, and then the environmental parameters are transmitted to the main body processing unit to realize building of the operating environment of the instruction to be executed.
6. The method according to claim 2, wherein when the number of the interfaces is plural, the interfaces include a first interface and a second interface; according to the execution sequence of the target processor, the calling sequence of each interface and the original data group to be tested, calling each interface in sequence to realize that each target processor processes corresponding original data to be tested according to the sequence and obtains corresponding test result data through each interface, and the method specifically comprises the following steps:
analyzing the intermediate data to be tested and the instruction group to be executed of each target processor from the original data group to be tested;
transmitting a first intermediate sub data group to be tested in the intermediate data to be tested to a target processor by calling the first interface, so that the target processor obtains a second intermediate sub data group to be tested acquisition instruction generated by the target processor after finishing processing the first intermediate sub data group to be tested according to a first instruction to be executed in the instruction group to be executed;
and acquiring an instruction according to the second intermediate sub data group to be tested, and transmitting corresponding data to a target processor by calling the second interface so that the target processor acquires test result data from the second interface after finishing processing the second intermediate sub data group to be tested according to a second instruction to be executed in the instruction group to be executed.
7. The method of claim 2, further comprising:
and sending a test ending instruction to the target processor to control the target processor to complete the processing flow of preset logic processing.
8. An interface testing apparatus, the apparatus comprising:
the acquisition module is used for acquiring a preset configuration file of the interface test and an original data set to be tested; the original data group to be tested comprises at least one original data to be tested;
the processing module is used for analyzing the preset configuration file to obtain a processor execution list and an interface calling list; the processor execution list comprises at least one target processor and a target processor execution sequence, and the interface calling list comprises at least one interface and each interface calling sequence;
the processing module is further configured to sequentially call each interface according to the execution sequence of the target processor, the calling sequence of each interface, and the original data group to be tested, so that each target processor processes corresponding original data to be tested according to the sequence, and sequentially obtains the state of each interface.
9. An electronic device, comprising: a control processor and a memory communicatively coupled to the control processor;
the memory stores computer-executable instructions;
the control processor when executing the computer instructions is for implementing an interface testing method as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium having stored thereon computer instructions for implementing the interface testing method according to any one of claims 1 to 7 when executed by a processor.
CN202111570825.3A 2021-12-21 2021-12-21 Interface test method, device, equipment and storage medium Pending CN114238127A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115952100A (en) * 2023-01-10 2023-04-11 北京百度网讯科技有限公司 Interface test method, device, system, electronic equipment and storage medium
CN117234951A (en) * 2023-11-13 2023-12-15 建信金融科技有限责任公司 Function test method and device of application system, computer equipment and storage medium

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115952100A (en) * 2023-01-10 2023-04-11 北京百度网讯科技有限公司 Interface test method, device, system, electronic equipment and storage medium
CN117234951A (en) * 2023-11-13 2023-12-15 建信金融科技有限责任公司 Function test method and device of application system, computer equipment and storage medium
CN117234951B (en) * 2023-11-13 2024-01-30 建信金融科技有限责任公司 Function test method and device of application system, computer equipment and storage medium

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