CN114237904A - Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching - Google Patents

Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching Download PDF

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Publication number
CN114237904A
CN114237904A CN202111581589.5A CN202111581589A CN114237904A CN 114237904 A CN114237904 A CN 114237904A CN 202111581589 A CN202111581589 A CN 202111581589A CN 114237904 A CN114237904 A CN 114237904A
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component
components
node
state
nodes
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CN202111581589.5A
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陆超
韩文俊
李路野
唐强
丁琳琳
王嘎
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CETC 14 Research Institute
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CETC 14 Research Institute
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5055Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering software capabilities, i.e. software resources associated or available to the machine

Abstract

The invention provides a resource scheduling method facing embedded heterogeneous hardware based on subgraph matching, which solves the problem that the binding scheme between a functional component and a computing node in application is time-consuming in the scene that the computing nodes in the same plug-in box are fully interconnected and the computing nodes between different plug-in boxes are not fully interconnected. The front-end components are utilized to complete component combination, the related components are guaranteed to be deployed on the same computing node, and the symmetrical nodes are adopted for pruning, so that the time consumption for generating the scheme is shortened.

Description

Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching
Technical Field
The invention belongs to the technical field of information processing, and particularly relates to a resource scheduling method.
Background
In order to meet the changing application function requirements, software and hardware systems need to meet the requirement of being capable of quickly realizing new functions through component recombination.
The computing nodes in the system can be composed of various heterogeneous nodes such as a CPU, a DSP, an FPGA and the like, and dynamic scheduling deployment of software components in the heterogeneous computing nodes is a necessary condition for realizing dynamic recombination of the system. However, the scheduling deployment of heterogeneous computing nodes faces the problems of asymmetric computing power, non-full interconnection of computing nodes and the like, and a brand new challenge is provided for the real-time performance of dynamic scheduling deployment.
Under the background, a software dynamic reconfiguration technology is designed, which supports real-time dynamic reconfiguration of application components, improves the upgrade maintenance efficiency, ensures that the system can operate in a fast adaptive manner under different hardware configuration conditions, and improves the system stability.
Disclosure of Invention
The invention aims to: in the scene that computing nodes in the same subrack are all interconnected and computing nodes between different subracks are not all interconnected, the problem that the time is consumed for generating a binding scheme of a functional component and the computing nodes in an application is solved.
In order to achieve the purpose, the invention provides a resource scheduling method facing embedded heterogeneous hardware based on subgraph matching, which utilizes a front-end component to complete component combination and guarantee that associated components are deployed at the same computing node, and adopts symmetric nodes to prune, thereby shortening the time consumed by scheme generation. The method comprises the following steps:
a scheduling information generating step:
the upper computer program arranges the application function components, combines the components with larger communication data flow, and generates the topological relation of each new component and the corresponding computing resource requirement after arrangement;
acquiring the ID of a CPU occupied by a user and the ID of a subrack in which the CPU is located, acquiring the interconnection relationship of the subracks occupied by the user, and constructing a topological relationship of the subracks and a CPU state data structure in the subracks;
scheduling the programmed application components:
and searching a feasible scheduling scheme in the computing nodes currently owned by the user by utilizing a traversal pruning subgraph matching method according to the topological relation of the new organized components and the computing resource requirements.
Further, the method specifically comprises the following steps:
step 1, for an application with a plurality of functional components, a user combines a component with large interactive data flow and a component with high coupling degree to generate a plurality of new components;
step 2, analyzing the new components in the application after the components are arranged, storing the topological relation of the new components by an adjacent matrix, storing the requirements of the new components on the number of computing cores by a linked list, and setting the states of all the new components as 'temporarily unallocated';
step 3, analyzing the information of the remaining computing nodes of the current user, acquiring the IDs of the plug boxes where the remaining computing nodes are located, and storing the topological relation of the plug boxes by using an adjacent matrix;
step 4, constructing a plug-in box-node data structure, storing in a dictionary form, taking the key of the dictionary as a core number, taking the value of the dictionary as an ID list of the node with the core number, storing all the plug-in box-node data structures according to the list, and setting all the calculation node states as 'unbound';
step 5, sequentially selecting a new component with the state of 'temporarily unallocated', setting the state of the component as 'allocating', and jumping to the step 9 if no component with the state of 'temporarily unallocated' exists;
step 6, sequentially selecting a plug box which is not traversed, and if the plug box does not exist, jumping to step 9;
step 7, sequentially selecting any node which is not traversed and has the state of being unbound in the plug-in box, if the symmetrical node of the node is bound with the current component unsuccessfully, repeating the step 7, if the binding is successful, setting the node state as a bound component and setting the current component state as a distributed success, and jumping to the step 5;
step 8, setting the current component state as 'temporarily unallocated', if the current component is not the first component, setting the node state bound by the previous component as 'unbound' and setting the state of the previous component as 'temporarily unallocated', skipping to step 6, and if the current component is the first component, skipping to step 9;
step 9, finishing scheduling, if all the component states are 'successful allocation', outputting a corresponding allocation scheme, and otherwise, outputting a scheduling failure;
preferably, the symmetric nodes in step 7 refer to nodes with the same residual core number in the same subrack;
preferably, the basis for successful binding in step 7 is: and if the interconnection relationship exists between any two components which are successfully distributed after the current component and the current node are bound, the interconnection relationship also exists between the corresponding binding nodes.
The generation process of the scheduling information is the same as the step 1-4, and the scheduling process of the application component after arrangement is the same as the step 5-9.
The invention has the beneficial effects that:
the invention utilizes the symmetry of the same number of nodes in the same subrack to carry out search space pruning, thereby reducing the time consumption of scheduling.
According to the invention, the arrangement of the application components is carried out on the user side, and the association components are combined, so that the special combination requirement of the user on the deployment of the components is met, the scale of the scheduling components is reduced, and the time consumed by scheduling is further reduced.
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FIG. 1 application software functional component orchestration scheduling
Detailed Description
The technical solutions provided by the present invention will be described in detail below with reference to specific examples, and it should be understood that the following specific embodiments are only illustrative of the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1, each computing node in the subrack performs data interaction through a data bus, the subracks are connected through optical fibers, and only the nodes between the directly connected subracks can perform data interaction, thereby forming a fully-interconnected and non-fully-interconnected structure between the subracks in the subrack. The application software comprises a plurality of functional components, the functional components are firstly arranged, the arranged components form a new component, the core number requirement and the interconnection relation of the new component are given by the original component, and finally, the topological structure of the arranged component is formed. The scheduling method provided by the invention finally completes the one-to-one mapping between the arranged components and the computing nodes. Specifically, the method comprises the following steps:
step 1, for an application with a plurality of functional components, a user combines a component with large interactive data flow and a component with high coupling degree to generate a plurality of new components;
step 2, analyzing the new components in the application after the components are arranged, storing the topological relation of the new components by an adjacent matrix, storing the requirements of the new components on the number of computing cores by a linked list, and setting the states of all the new components as 'temporarily unallocated';
step 3, analyzing the information of the remaining computing nodes of the current user, acquiring the IDs of the plug boxes where the remaining computing nodes are located, and storing the topological relation of the plug boxes by using an adjacent matrix;
step 4, constructing a plug-in box-node data structure, storing in a dictionary form, taking the key of the dictionary as a core number, taking the value of the dictionary as an ID list of the node with the core number, storing all the plug-in box-node data structures according to the list, and setting all the calculation node states as 'unbound';
step 5, sequentially selecting a new component with the state of 'temporarily unallocated', setting the state of the component as 'allocating', and jumping to the step 9 if no component with the state of 'temporarily unallocated' exists;
step 6, sequentially selecting a plug box which is not traversed, and if the plug box does not exist, jumping to step 9;
step 7, sequentially selecting any node which is not traversed and has the state of being unbound in the plug-in box, if the symmetrical node of the node is bound with the current component unsuccessfully, repeating the step 7, if the binding is successful, setting the node state as a bound component and setting the current component state as a distributed success, and jumping to the step 5;
step 8, setting the current component state as 'temporarily unallocated', if the current component is not the first component, setting the node state bound by the previous component as 'unbound' and setting the state of the previous component as 'temporarily unallocated', skipping to step 6, and if the current component is the first component, skipping to step 9;
step 9, finishing scheduling, if all the component states are 'successful allocation', outputting a corresponding allocation scheme, and otherwise, outputting a scheduling failure;
preferably, the symmetric nodes in step 7 refer to nodes with the same residual core number in the same subrack;
preferably, the basis for successful binding in step 7 is: and if the interconnection relationship exists between any two components which are successfully distributed after the current component and the current node are bound, the interconnection relationship also exists between the corresponding binding nodes.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims (5)

1. A resource scheduling method facing embedded heterogeneous hardware based on subgraph matching is characterized in that a front-end component is used for arranging, completing component combination, ensuring that associated components are deployed on the same computing node, and pruning is performed by adopting symmetrical nodes, so that the time consumed by scheme generation is shortened; the method comprises the following steps:
a scheduling information generating step:
the upper computer program arranges the application function components, combines the components with larger communication data flow, and generates the topological relation of each new component and the corresponding computing resource requirement after arrangement;
acquiring the ID of a CPU occupied by a user and the ID of a subrack in which the CPU is located, acquiring the interconnection relationship of the subracks occupied by the user, and constructing a topological relationship of the subracks and a CPU state data structure in the subracks;
scheduling the programmed application components:
and searching a feasible scheduling scheme in the computing nodes currently owned by the user by utilizing a traversal pruning subgraph matching method according to the topological relation of the new organized components and the computing resource requirements.
2. The method according to claim 1, wherein the scheduling information generating step specifically comprises the steps of:
step 1, for an application with a plurality of functional components, a user combines a component with large interactive data flow and a component with high coupling degree to generate a plurality of new components;
step 2, analyzing the new components in the application after the components are arranged, storing the topological relation of the new components by an adjacent matrix, storing the requirements of the new components on the number of the computing cores by a linked list, and setting the states of all the new components as 'temporarily unallocated';
step 3, analyzing the information of the remaining computing nodes of the current user, acquiring the IDs of the plug boxes where the remaining computing nodes are located, and storing the topological relation of the plug boxes by using an adjacent matrix;
and 4, constructing a data structure of the plug-in box-node, storing in a dictionary form, taking the key of the dictionary as a core number, taking the value of the dictionary as an ID list of the node with the core number, storing all the data structures of the plug-in box-node according to the list, and setting the states of all the calculation nodes as 'unbound'.
3. The method according to claim 1, wherein the step of scheduling the choreographed application component comprises the steps of:
step 5, sequentially selecting a new component with the state of 'temporarily unallocated', setting the state of the component as 'allocating', and jumping to the step 9 if no component with the state of 'temporarily unallocated' exists;
step 6, sequentially selecting a plug box which is not traversed, and if the plug box does not exist, jumping to step 9;
step 7, sequentially selecting any node which is not traversed and has the state of being unbound in the plug-in box, if the symmetrical node of the node is bound with the current component unsuccessfully, repeating the step 7, if the binding is successful, setting the node state as a bound component and setting the current component state as a distributed success, and jumping to the step 5;
step 8, setting the current component state as 'temporarily unallocated', if the current component is not the first component, setting the node state bound by the previous component as 'unbound' and setting the state of the previous component as 'temporarily unallocated', skipping to step 6, and if the current component is the first component, skipping to step 9;
and 9, finishing scheduling, outputting a corresponding allocation scheme if all the component states are 'allocation success', otherwise, outputting a scheduling failure.
4. The method of claim 3, wherein the symmetric nodes in step 7 refer to nodes with the same number of cores remaining in the same subrack.
5. The method of claim 3, wherein the binding in step 7 is successful according to the following criteria: and if the interconnection relationship exists between any two components which are successfully distributed after the current component and the current node are bound, the interconnection relationship also exists between the corresponding binding nodes.
CN202111581589.5A 2021-12-22 2021-12-22 Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching Pending CN114237904A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111147555A (en) * 2019-12-13 2020-05-12 苏州博纳讯动软件有限公司 Heterogeneous resource mixed arrangement method
CN113722065A (en) * 2021-08-20 2021-11-30 中国电子科技集团公司第十四研究所 Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111147555A (en) * 2019-12-13 2020-05-12 苏州博纳讯动软件有限公司 Heterogeneous resource mixed arrangement method
CN113722065A (en) * 2021-08-20 2021-11-30 中国电子科技集团公司第十四研究所 Resource scheduling method facing embedded heterogeneous hardware based on subgraph matching

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