CN114236923A - Array substrate, preparation method thereof and liquid crystal display device - Google Patents
Array substrate, preparation method thereof and liquid crystal display device Download PDFInfo
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- CN114236923A CN114236923A CN202111509393.5A CN202111509393A CN114236923A CN 114236923 A CN114236923 A CN 114236923A CN 202111509393 A CN202111509393 A CN 202111509393A CN 114236923 A CN114236923 A CN 114236923A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
Abstract
The application relates to an array substrate, a preparation method thereof and a liquid crystal display device. The liquid crystal display panel comprises a display area and a non-display area located on the periphery of the display area, the array substrate comprises a metal layer formed on the first substrate, a plurality of test bonding pads are formed on the metal layer in the non-display area, the array substrate is located on the light emitting side of the liquid crystal display panel, identification patterns are further formed on the metal layer in the non-display area, the identification patterns are arranged adjacent to the test bonding pads, a light shielding layer is further formed on one side, away from the first substrate, of the metal layer, and an opening is formed in the light shielding layer corresponding to the identification patterns. The array substrate forms the identification pattern adjacent to the test pad through the metal layer in the non-display area, and the shading layer is formed on the periphery of the identification pattern, so that the identification pattern can reflect metal luster, identification patterns can be conveniently recognized even if a light source of the backlight module is not started, the occupied space of the identification pattern is small, and narrow frame of the liquid crystal display panel is favorably realized.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a liquid crystal display device.
Background
As liquid crystal display devices have become more popular, demands for the aesthetic appearance of the liquid crystal display devices have become higher. In order to make the appearance of a liquid crystal display device more beautiful and more scientific, a liquid crystal display panel is increasingly required to have a narrower frame, and it is desirable that the frame is smaller as better.
When a liquid crystal display device is assembled before shipment, a manufacturer usually needs to install its own brand Logo (Logo) on the liquid crystal display device. If set up the brand mark on the back of product or support, be unfavorable for improving the cognitive degree of product, if set up the brand mark in the positive frame department of product, will be unfavorable for realizing the narrow frame of product.
Disclosure of Invention
The array substrate forms an identification pattern adjacent to a test pad through a metal layer in a non-display area, and a shading layer is formed on the periphery of the identification pattern, so that the identification pattern can reflect metal luster, even if a light source of a backlight module is not started, the identification pattern can be conveniently recognized, the occupied space of the identification pattern is small, and the narrow frame of the liquid crystal display panel is favorably realized.
In a first aspect, an embodiment of the present application provides an array substrate for a liquid crystal display panel, where the liquid crystal display panel includes a display area and a non-display area located at a periphery of the display area, the array substrate includes a metal layer formed on a first substrate, and the metal layer is formed with a plurality of test pads in the non-display area; the array substrate is located on the light emitting side of the liquid crystal display panel, the metal layer is formed with identification patterns in a non-display area, the identification patterns are arranged adjacent to the test bonding pad, a light shielding layer is further formed on one side, away from the first substrate, of the metal layer, and openings are formed in the light shielding layer corresponding to the identification patterns.
In one possible embodiment, the metal layer includes a plurality of hollowed-out portions forming the identification pattern, and the insulating layer fills the hollowed-out portions.
In one possible embodiment, the metal layer is formed with a plurality of vias distributed at intervals around the circumference of the hollow portion.
In one possible embodiment, the via is a rectangular hole, and the via has a length dimension of 50 μm and a width dimension of 10 μm.
In a possible implementation manner, the array substrate further includes an insulating layer formed on a side of the metal layer away from the first substrate, and the insulating layer fills the hollow portion.
In one possible implementation, the metal layer includes a first metal layer formed on the first substrate, the first metal layer is formed with a scan line and a gate of a thin film transistor in the display region, and the identification pattern is formed in the non-display region of the first metal layer.
In one possible implementation, the metal layer includes a first metal layer and a second metal layer which are sequentially formed on the first substrate and are insulated from each other, in the display region, the first metal layer is formed with a scan line and a gate electrode of the thin film transistor, the second metal layer is formed with a data line and a source electrode and a drain electrode of the thin film transistor, and the identification pattern is formed in the non-display region of the second metal layer.
In a second aspect, an embodiment of the present application further provides a method for manufacturing an array substrate, where the array substrate is used for a liquid crystal display panel, the liquid crystal display panel includes a display area and a non-display area located at a periphery of the display area, and the method includes: forming a metal layer on the first substrate, wherein the metal layer is provided with a plurality of test pads and identification patterns in a non-display area, and the identification patterns are arranged adjacent to the test pads; and forming a light shielding layer on one side of the metal layer, which is far away from the first substrate, wherein the light shielding layer is provided with an opening corresponding to the identification pattern.
In a possible embodiment, before forming the light shielding layer on the side of the metal layer away from the first substrate, the preparation method further includes: and forming an insulating layer on one side of the metal layer, which is far away from the first substrate, wherein the insulating layer covers the identification pattern in the non-display area.
In a third aspect, an embodiment of the present application further provides a liquid crystal display device, including: a liquid crystal display panel including a display region and a non-display region positioned at a periphery of the display region, the liquid crystal display panel comprising: the color film substrate is positioned in the display area; the array substrate is arranged opposite to the color film substrate, and is positioned on the light emergent side of the liquid crystal display panel; the liquid crystal layer is arranged between the array substrate and the color film substrate; and the backlight module is positioned on the backlight side of the liquid crystal display panel and used for providing light sources for the liquid crystal display panel.
According to the array substrate, the manufacturing method of the array substrate and the liquid crystal display device, the identification pattern adjacent to the test bonding pad is formed on the metal layer of the non-display area of the array substrate, and the light shielding layer is formed on the periphery of the identification pattern, so that the identification pattern can reflect metal luster, even if a light source of the backlight module is not started, the identification pattern can be conveniently recognized, the occupied space of the identification pattern is small, and the narrow frame of the liquid crystal display panel is favorably realized.
Drawings
Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are provided with like reference numerals. The drawings are not necessarily to scale, and are merely intended to illustrate the relative positions of the layers, the thicknesses of the layers in some portions being exaggerated for clarity, and the thicknesses in the drawings are not intended to represent the proportional relationships of the actual thicknesses.
Fig. 1 is a schematic diagram illustrating a top view structure of a liquid crystal display panel according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of the liquid crystal display panel shown in FIG. 1 taken along a direction B-B;
FIG. 3 is a schematic view showing a partially enlarged structure of a region C in FIG. 1;
fig. 4 is a partial cross-sectional view illustrating an array substrate according to an embodiment of the present application;
fig. 5 is a cross-sectional view illustrating a non-display region of an array substrate according to another embodiment of the present application;
fig. 6 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Description of reference numerals:
1. an array substrate; AA. A display area; NA, non-display area; p, testing a bonding pad; F. a flexible circuit board; 10. a printed circuit board; m, marking a pattern;
11. a first substrate; 12. a metal layer; 121. a first metal layer; 122. a second metal layer; 123. a semiconductor layer; 12a, a hollow part; 12b, a via hole; 13. an insulating layer; 14. a light-shielding layer; 141. an opening; 15. a pixel electrode;
2. a color film substrate; 21. a second substrate; 22. a color resist layer; 23. a common electrode; 3. and a liquid crystal layer.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Fig. 1 is a schematic top view of a liquid crystal display panel according to an embodiment of the present disclosure, and fig. 2 is a cross-sectional view of the liquid crystal display panel shown in fig. 1 along a direction B-B.
As shown in fig. 1 and fig. 2, an embodiment of the present application provides a liquid crystal display panel, including a display area AA and a non-display area NA located at a periphery of the display area AA, the liquid crystal display panel including: the liquid crystal display panel comprises an array substrate 1, a color film substrate 2 and a liquid crystal layer 3, wherein the array substrate 1 and the color film substrate 2 are arranged oppositely, and the liquid crystal layer 3 is arranged between the array substrate 1 and the color film substrate 2, wherein the array substrate 1 is positioned on the light emergent side of the liquid crystal display panel.
The color filter substrate 2 includes a second substrate 21, a color resist layer 22 on the second substrate 21, and a common electrode 23 on a side of the color resist layer 22 away from the second substrate 21. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and both fluid like a liquid and have certain crystalline characteristics. When liquid crystal molecules are placed in an electric field, their alignment direction changes according to the change of the electric field. The pixel electrode 15 is disposed on one side of the array substrate 1, and different driving voltages are applied to control the rotation of liquid crystal molecules of the liquid crystal layer 3 by generating an electric field with a predetermined intensity between the pixel electrode 15 and the common electrode 23, so as to refract light provided by the backlight module to generate a picture.
Since the lcd panel is a non-emissive light receiving device, a light source needs to be provided through a backlight module disposed on a backlight side thereof. The liquid crystal display panel controls the rotation of liquid crystal molecules of the liquid crystal layer 3 by applying a driving voltage on the array substrate 1 and the color film substrate 2, so that light rays provided by the backlight module are refracted out to generate a picture. In order to display a color picture, a thin film transistor array is generally fabricated on the array substrate 1 for driving the rotation of liquid crystal molecules to control the display of each sub-pixel. A color resist layer 22 is then prepared on the color filter substrate 2 for forming the color of each sub-pixel.
Further, the liquid crystal display panel further includes a Circuit Board assembly including a flexible Circuit Board F and a Printed Circuit Board (PCB) 10. The flexible circuit board F is made of a Chip On Film (COF) material as a substrate, one end of the flexible circuit board F is manufactured in the non-display area NA of the array substrate 1 by a TAB (TAB) process, the other end of the flexible circuit board F is electrically connected with the printed circuit board 10, and the circuit board assembly can be bent downwards and attached to the lower surface of the color Film substrate 2 through the flexible circuit board F so as to be hidden between the backlight module and the liquid crystal display panel.
In addition, a plurality of test pads P are usually disposed near the flexible circuit board F for performing related tests during the assembly process of the array substrate 1. After the test is qualified, the liquid crystal display panel can be attached to the backlight module through the adhesive, and a user cannot see the circuit board assembly when watching the liquid crystal display panel of a television or a display from one side of the array substrate 1. In addition, manufacturers of televisions or displays usually need to set a brand Logo on a frame of a liquid crystal display panel, which is not favorable for realizing a narrow-frame or frameless design.
Therefore, the embodiment of the application provides an array substrate 1, and the marking pattern M is arranged near the position of the test pad P in the non-display area NA, which is beneficial to realizing the narrow frame of the liquid crystal display panel.
The specific structure of the array substrate 1 provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Fig. 3 is a schematic partial enlarged view illustrating a structure of a region C in fig. 1, and fig. 4 is a partial cross-sectional view illustrating an array substrate according to an embodiment of the present application.
As shown in fig. 3 and 4, an array substrate 1 is provided in an embodiment of the present application, and is used for a liquid crystal display panel, where the liquid crystal display panel includes a display area AA and a non-display area NA located at a periphery of the display area AA, the array substrate 1 includes a metal layer 12 sequentially formed on a first substrate 11, and the metal layer 12 is formed with a plurality of test pads P in the non-display area NA.
The array substrate 1 is located the light-emitting side of the liquid crystal display panel, in the non-display area NA, the metal layer 12 is formed with an identification pattern M, the identification pattern M is arranged adjacent to the test pad P, a light-shielding layer 14 is further formed on one side of the metal layer 12 departing from the first substrate 11, and an opening 141 is formed on the light-shielding layer 14 corresponding to the identification pattern M.
The first substrate 11 may be a transparent substrate such as a glass substrate or a quartz substrate. The material of the metal layer 12 may be, for example, but not limited to, copper, tin, molybdenum, etc., and the metal layer 12 is prepared on the first substrate 11 by sputtering, deposition, etc. The metal layer 12 is generally used for forming a pixel circuit of the display area AA, and the identification pattern M is formed on the metal layer 12, so that the identification pattern is conveniently manufactured in the non-display area NA while the pixel circuit of the display area AA is manufactured, and the manufacturing process is simplified. In addition, the identification pattern M may also be formed at a corresponding position of the metal layer 12 by laser and other processes after the array substrate 1 is formed, which is not described in detail.
Optionally, the identification pattern M is a brand identification of the product. Alternatively, the logo pattern M may be a shape pattern having a certain depth. Since the logo pattern M is formed of the metal layer 12, metallic luster can be emitted. In addition, the light-shielding layer 14 may be a Black Matrix (BM), and the BM material may be a Black organic photoresist or an opaque metal. The light-shielding layer 14 is formed around the marker pattern M, and the contrast of the marker pattern M can be improved. Even if the light source of the backlight module is not started, the identification pattern M is convenient to identify, and the identifiability of the identification pattern M is improved.
Optionally, the non-display area NA is a strip-shaped area, the width of the non-display area NA is about 5mm to 8mm, and the plurality of test pads P are distributed at intervals along the length direction of the non-display area NA. Optionally, the identification pattern M is located in the middle of the plurality of test pads P, so that the user can quickly identify the identification pattern M of the product, and the identifiability of the identification pattern M is further improved. In addition, the mark pattern M borrows the position of the original test pad P, occupies small space and is beneficial to realizing the narrow frame of the liquid crystal display panel.
According to the array substrate 1 provided by the embodiment of the application, the identification pattern M adjacent to the test pad P is formed on the metal layer 12 of the non-display area NA, and the light shielding layer 14 is formed on the periphery of the identification pattern M, so that the identification pattern M can reflect metal luster, even if a light source of the backlight module is not turned on, the identification pattern M can be conveniently identified, the occupied space of the identification pattern M is small, and the narrow frame of the liquid crystal display panel is favorably realized.
In some embodiments, the metal layer 12 includes a plurality of hollowed-out portions 12a forming the identification pattern M.
As shown in fig. 3, taking the mark pattern M as "HKC" as an example, the metal layer 12 includes a plurality of hollow portions 12a forming the mark pattern M, and when a light source provided by the backlight module irradiates the hollow portions 12a, light directly passes through the first substrate 11 and exits from the light exit surface, so that a brighter mark pattern M can be displayed in the non-display area NA of the liquid crystal display panel.
In some embodiments, the metal layer 12 is formed with a plurality of vias 12b distributed at intervals around the circumference of the hollow portion 12 a. Optionally, the via 12b is a rectangular hole, and the length dimension of the via 12b is 50 μm and the width dimension is 10 μm. The via hole 12b may also be a circular hole, etc., and will not be described in detail. When the light source of the backlight module is turned on, the light is emitted from the via holes 12b, so that the identification pattern M is more striking, and the identifiability of the identification pattern M is further improved.
In some embodiments, the array substrate 1 further includes an insulating layer 13 formed on a side of the metal layer 12 facing away from the first substrate 11, and the insulating layer 13 fills the hollow portion 12 a. The insulating layer 13 is made of a transparent insulating material, and in the non-display area NA, the insulating layer 13 can prevent the marking pattern M made of a metal material from being scratched in an assembling process to generate scratches, which affects the aesthetic property of the marking pattern M.
In some embodiments, the metal layer 12 includes a first metal layer 121 formed on the first substrate 11, in the display area AA, the first metal layer 121 is formed with a scan line and a Gate electrode of a thin film transistor, and the identification pattern M is formed in the non-display area NA of the first metal layer 121. The insulating layer 13 is a Passivation layer (PV) and may be deposited by Chemical Vapor Deposition (CVD).
As shown in fig. 4, the array substrate 1 includes a first metal layer 121, an insulating layer 13, a semiconductor layer 123, and a second metal layer 122 sequentially formed on the first substrate 11.
In the display area AA, the first metal layer 121 is formed with a plurality of scan lines and a plurality of gate electrodes G of tfts, the second metal layer 122 is formed with a plurality of data lines (not shown), and a plurality of source electrodes S and drain electrodes D of tfts, and any one of the source electrodes S and the drain electrodes D is electrically connected to the data lines. The plurality of scan lines and the plurality of data lines are arranged to cross to define a plurality of sub-pixels.
In the non-display area NA, the first metal layer 121 is formed with an identification pattern M adjacent to the test pad P. The insulating layer 13 extends to the non-display area NA and covers the mark pattern M, and the test pad P needs to be electrically connected to the outside, so that the insulating layer 13 is not disposed on the side of the test pad P away from the first substrate 11. The insulating layer 13 is further provided with a light shielding layer 14 on a side away from the first substrate 11, and the light shielding layer 14 is formed with an opening 141 corresponding to the mark pattern M, and the opening 141 exposes the mark pattern M, so that the contrast of the mark pattern M is improved.
Further, the first metal layer 121 is formed with a plurality of via holes 12b distributed at intervals around the circumference of the hollow portion 12 a. Optionally, the via 12b is a rectangular hole, and the length dimension of the via 12b is 50 μm and the width dimension is 10 μm. The via hole 12b may also be a circular hole, etc., and will not be described in detail. When the light source of the backlight module is turned on, light is emitted from the plurality of via holes 12b, thereby further improving the identifiability of the identification pattern M.
Fig. 5 is a cross-sectional view illustrating a non-display area of an array substrate according to another embodiment of the present disclosure.
As shown in fig. 5, another embodiment of the present application further provides an array substrate 1, which is similar to the array substrate 1 shown in fig. 4, except that a mark pattern M is formed in the non-display area NA of the second metal layer 122.
Specifically, the array substrate 1 includes a first metal layer 121, a semiconductor layer 123, a second metal layer 122, and an insulating layer 15 sequentially formed on the first substrate 11.
In the display area AA, the first metal layer 121 is formed with a plurality of scan lines and a plurality of gate electrodes G of tfts, the second metal layer 122 is formed with a plurality of data lines (not shown), and a plurality of source electrodes S and drain electrodes D of tfts, and any one of the source electrodes S and the drain electrodes D is electrically connected to the data lines. The plurality of scan lines and the plurality of data lines are arranged to cross to define a plurality of sub-pixels.
In the non-display area NA, the second metal layer 122 is formed with an identification pattern M adjacent to the test pad P. The insulating layer 13 extends to the non-display area NA and covers the mark pattern M, and the insulating layer 13 may be a Passivation layer (PV), and may be formed by Deposition in a Chemical Vapor Deposition (CVD) manner. The test pads P need to be electrically connected to the outside, so that the side of the test pads P facing away from the first substrate 11 is free of the insulating layer 13. The insulating layer 13 is further provided with a light shielding layer 14 on a side away from the first substrate 11, and the light shielding layer 14 is formed with an opening 141 corresponding to the mark pattern M, and the opening 141 exposes the mark pattern M, so that the contrast of the mark pattern M is improved.
Further, the second metal layer 122 is formed with a plurality of via holes 12b distributed at intervals around the circumference of the hollow portion 12 a. Optionally, the via 12b is a rectangular hole, and the length dimension of the via 12b is 50 μm and the width dimension is 10 μm. The via hole 12b may also be a circular hole, etc., and will not be described in detail. When the light source of the backlight module is turned on, the light is emitted from the via holes 12b, so that the identification pattern M is more striking, and the identifiability of the identification pattern M is further improved.
Fig. 6 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Referring to fig. 4 and 6, an embodiment of the present application provides a method for manufacturing an array substrate, where the array substrate 1 is used for a liquid crystal display panel, the liquid crystal display panel includes a display area AA and a non-display area NA located at a periphery of the display area AA, and the method includes steps S1 to S2.
Step S1: a metal layer 12 is formed on the first substrate 11, wherein the metal layer 12 is formed with a plurality of test pads P and a logo pattern M in the non-display area NA, and the logo pattern M is disposed adjacent to the test pads P.
Step S2: a light-shielding layer 14 is formed on the side of the metal layer 12 away from the first substrate 11, and an opening 141 is formed in the light-shielding layer 14 corresponding to the marker pattern M.
As described above, the logo pattern M is formed on the first metal layer 121 or the second metal layer 122,
for convenience of description, the embodiment of the present application takes the mark pattern M formed on the first metal layer 121 as an example.
In one possible embodiment, the identification pattern M may be formed during the preparation of the array substrate 1 in order to simplify the fabrication process. Specifically, a first metal layer 121 is formed on the first substrate 11, wherein the first metal layer 121 is formed with a plurality of test pads P and a logo pattern M in the non-display area NA, and the logo pattern M is disposed adjacent to the test pads P; then, a light shielding layer 14 is coated on a side of the first metal layer 121 facing away from the first substrate 11, a light shielding mask is disposed at a position of the light shielding layer 14 corresponding to the marker pattern M, and the light shielding layer 14 is exposed and developed to form an opening 141 at a position of the light shielding layer 14 corresponding to the marker pattern M, wherein the marker pattern M is exposed by the opening 141.
Optionally, before step S2, that is, before forming the light shielding layer 14 on the side of the first metal layer 121 facing away from the first substrate 11, the preparation method further includes:
step S20: an insulating layer 13 is formed on a side of the first metal layer 121 facing away from the first substrate 11, and the insulating layer 13 covers the mark pattern M in the non-display area NA.
Therefore, the light shielding layer 14 is located on the side of the insulating layer away from the first substrate 11, and the marking pattern M made of a metal material can be prevented from being scratched in the assembling process to generate scratches, so that the appearance of the marking pattern M is prevented from being affected.
In another possible embodiment, the mark pattern M may also be formed at a corresponding position of the first metal layer 121 by a laser process or the like after the array substrate 1 is formed, and at this time, the insulating layer 13 is not formed on a side of the mark pattern M away from the first substrate 11.
In addition, the embodiment of the application also provides a liquid crystal display device, which comprises the liquid crystal display panel and the backlight module, wherein the backlight module is positioned at the backlight side of the liquid crystal display panel and is used for providing a light source for the liquid crystal display panel.
It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application can be widely applied to various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-plane switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.
It should be readily understood that "on … …", "above … …" and "above … …" in this application should be interpreted in its broadest sense such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" includes not only the meaning of "above something" or "above" but also includes the meaning of "above something" or "above" without intervening features or layers therebetween (i.e., directly on something).
The term "first substrate" as used herein refers to a material on which subsequent layers of material are added. The first substrate itself may be patterned. The material added atop the first substrate may be patterned or may remain unpatterned. Further, the first substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the first substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).
The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The first substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. An array substrate for a liquid crystal display panel, the liquid crystal display panel including a display region and a non-display region located at a periphery of the display region, the array substrate including a metal layer formed on a first substrate, the metal layer having a plurality of test pads formed in the non-display region,
the array substrate is located on the light emitting side of the liquid crystal display panel, a mark pattern is further formed on the metal layer, the mark pattern is arranged adjacent to the test pad, a light shielding layer is further formed on one side, deviating from the first substrate, of the metal layer, and an opening is formed in the light shielding layer corresponding to the mark pattern.
2. The array substrate of claim 1, wherein the metal layer comprises a plurality of hollowed-out portions forming the logo pattern.
3. The array substrate of claim 2, wherein the metal layer is formed with a plurality of vias spaced around a periphery of the hollow portion.
4. The array substrate of claim 3, wherein the via is a rectangular hole having a length dimension of 50 μm and a width dimension of 10 μm.
5. The array substrate of claim 2, further comprising an insulating layer formed on a side of the metal layer facing away from the first substrate, wherein the insulating layer fills the hollowed-out portion.
6. The array substrate of claim 1, wherein the metal layer comprises a first metal layer formed on the first substrate, the first metal layer is formed with a scan line and a gate of a thin film transistor in the display region, and the mark pattern is formed in the non-display region of the first metal layer.
7. The array substrate of claim 1, wherein the metal layer comprises a first metal layer and a second metal layer sequentially formed on the first substrate and insulated from each other, the first metal layer forms a scan line and a gate of the thin film transistor in the display region, the second metal layer forms a data line and a source and a drain of the thin film transistor, and the mark pattern is formed in the non-display region of the second metal layer.
8. A preparation method of an array substrate, wherein the array substrate is used for a liquid crystal display panel, and the liquid crystal display panel comprises a display area and a non-display area positioned at the periphery of the display area, and is characterized by comprising the following steps:
forming a metal layer on a first substrate, wherein the metal layer is formed with a plurality of test pads and a logo pattern in the non-display area, and the logo pattern is arranged adjacent to the test pads;
and forming a light shielding layer on one side of the metal layer, which is far away from the first substrate, wherein the light shielding layer is provided with an opening corresponding to the identification pattern.
9. The manufacturing method according to claim 8, wherein before forming a light shielding layer on a side of the metal layer facing away from the first substrate, the manufacturing method further comprises:
and forming an insulating layer on one side of the metal layer, which is far away from the first substrate, wherein the insulating layer covers the identification pattern in the non-display area.
10. A liquid crystal display device, comprising:
a liquid crystal display panel including a display region and a non-display region located at a periphery of the display region, the liquid crystal display panel including:
the color film substrate is positioned in the display area;
the array substrate according to any one of claims 1 to 7, disposed opposite to the color filter substrate, and located on a light-emitting side of the liquid crystal display panel; and
the liquid crystal layer is arranged between the array substrate and the color film substrate; and
and the backlight module is positioned on the backlight side of the liquid crystal display panel and used for providing a light source for the liquid crystal display panel.
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| CN202111509393.5A CN114236923A (en) | 2021-12-10 | 2021-12-10 | Array substrate, preparation method thereof and liquid crystal display device |
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| CN202111509393.5A CN114236923A (en) | 2021-12-10 | 2021-12-10 | Array substrate, preparation method thereof and liquid crystal display device |
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