CN114221661A - Successive approximation type analog-to-digital converter and electronic equipment - Google Patents

Abstract

The present invention relates to a successive approximation type analog-to-digital converter and an electronic device. The successive approximation type analog-to-digital converter includes: a voltage input for receiving an analog input voltage; the first input end of the comparator is coupled with one end of the capacitor, and the second input end of the comparator is coupled with a fixed reference voltage; the first input end of the successive approximation device is coupled with the output end of the comparator, the first output end of the successive approximation device is used for successively approximating and outputting analog voltage and is alternately coupled with the voltage input end to the other end of the capacitor, when the first output end of the successive approximation device is coupled with the capacitor, the first input end of the comparator is communicated with the output end of the comparator, and the second output end of the successive approximation device is used for outputting a multi-bit digital signal. The invention expands the input range of the analog input voltage received by the voltage input end under the condition of ensuring that the analog-digital converter keeps higher conversion precision.

Description

Successive approximation type analog-to-digital converter and electronic equipment

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a successive approximation type analog-to-digital converter and electronic equipment.

Background

The SoC chip is a chip of an integrated circuit, can effectively reduce the development cost of electronic/information system products, shorten the development period, and improve the competitiveness of the products, and is the most important product development mode to be adopted in the future industry. The ADC is capable of converting an analog signal to a digital signal. Successive approximation analog-to-digital converters (SAR ADCs) are integrated into many SOC chips. SAR ADC is a common analog-to-digital converter (ADC).

An ADC/SAR ADC typically includes a comparator and one or more digital to analog converters (DACs), which are devices that convert digital signals to analog signals. Because the comparator has mismatch deviation (it can be understood that two inputs are not completely symmetrical) during manufacturing, the two inputs of the comparator have difference, which results in inaccurate comparison function. This mismatch offset can generally be identified by an input mismatch voltage.

The existing scheme can eliminate or reduce mismatch influence by storing mismatch voltage and then offsetting the mismatch voltage during comparison, but the existing scheme has limitation on the input range of the analog-to-digital converter, if the input range is not proper, loop gain can be reduced, distortion is caused, namely the stored voltage is not accurate, and thus the conversion precision is reduced.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned problems, and an object of the present invention is to provide a successive approximation type analog-to-digital converter and an electronic device, which expand the input range of the analog input voltage received by the voltage input terminal while ensuring that the analog-to-digital converter maintains a high conversion accuracy.

In order to achieve the above object, an aspect of the present invention provides a successive approximation type analog-to-digital converter, including: a voltage input for receiving an analog input voltage; the first input end of the comparator is coupled with one end of the capacitor, and the second input end of the comparator is coupled with a fixed reference voltage; and a successive approximation device, a first input end of which is coupled to an output end of the comparator, a first output end of which is used for successive approximation to output an analog voltage and is alternately coupled to the voltage input end, and when the first output end of which is coupled to the capacitor, the first input end of the comparator is communicated with the output end of the comparator, and a second output end of which is used for outputting a multi-bit digital signal.

Optionally, when the first output terminal of the successive approximation device is coupled to the capacitor, the first input terminal of the comparator is communicated with the output terminal of the comparator, and the comparator is in a buffer mode; when the voltage input is coupled to the capacitor, the first input of the comparator is disconnected from the output of the comparator, the comparator being in comparator mode.

Optionally, the successive approximation analog-to-digital converter further includes: a first switch coupled between the voltage input terminal and the other end of the capacitor; a second switch coupled between a first output terminal of the successive approximation device and the other terminal of the capacitor; a third switch coupled between the first input terminal of the comparator and the output terminal of the comparator; when the first switch is turned on, the second switch and the third switch are turned off, and when the second switch and the third switch are turned on, the first switch is turned off.

Optionally, the closing and conducting of the first switch is controlled by a first clock signal; the closing and the conducting of the second switch and the third switch are controlled by a second clock signal; and/or the successive approximation type analog-to-digital converter further comprises an oscillator, wherein the oscillator is used for providing a first clock signal to control the closing and the conduction of the first switch; the oscillator is used for providing a second clock signal to control the second switch and the third switch to be closed and conducted.

Optionally, the successive approximation apparatus includes a successive approximation logic control module and a digital-to-analog converter, wherein: the successive approximation logic control module is used for receiving multiple comparison results output by the output end of the comparator through the first input end and outputting the multi-bit digital signal through the second output end in the successive approximation process so as to perform successive approximation control on the digital-to-analog converter; the digital-to-analog converter is used for converting the multi-bit digital signal into the analog voltage and then outputting the analog voltage through the first output end.

Optionally, the digital-to-analog converter is a capacitor array type digital-to-analog converter or a resistor array type digital-to-analog converter.

Optionally, the successive approximation logic control module includes: the resetting unit is used for resetting the successive approximation type analog-to-digital converter to an initial state; and/or the indicating unit is used for indicating the end of one analog-to-digital conversion process of the successive approximation type analog-to-digital converter.

A second aspect of the present invention provides a successive approximation type analog-to-digital converter, including: a voltage input for receiving an analog input voltage; the first input end of the comparator is coupled with one end of the capacitor, the second input end of the comparator is coupled with a fixed reference voltage, and the voltage higher than the first input end of the comparator is the mismatch voltage of the comparator; a successive approximation device, a first output end of which and the voltage input end are alternately coupled to the other end of the capacitor, so that the successive approximation device can successively approximate and output an analog voltage through the first output end according to a plurality of comparison results output by the output end of the comparator, and a second output end of the successive approximation device is used for outputting a corresponding multi-bit digital signal according to the plurality of comparison results; wherein: when the first output end of the successive approximation device is coupled with the capacitor, the first input end of the comparator is communicated with the output end of the comparator, the comparator works in a buffer mode, a first voltage at the first input end of the comparator can be latched and output to the output end of the comparator, and the voltage stored at two ends of the capacitor is the difference between the first voltage and the analog voltage; when the voltage input end is coupled with the other end of the capacitor, the comparator works in a comparator mode, a second voltage of a first input end of the comparator is the sum of the analog input voltage and the voltage stored at the two ends of the capacitor, and the comparator compares the sum of the second voltage and the mismatch voltage with the fixed reference voltage and outputs the comparison result through an output end of the comparator.

Optionally, the successive approximation apparatus includes a digital-to-analog converter and a successive approximation logic control module, wherein: the output end of the successive approximation logic control module is a second output end of the successive approximation device, and the successive approximation logic control module is used for generating a multi-bit digital signal in the successive approximation process according to the multiple comparison results so as to perform successive approximation control on the digital-to-analog converter; the output end of the digital-to-analog converter is a first output end of the successive approximation device, and the digital-to-analog converter is used for converting the multi-bit digital signal into the analog voltage and outputting the analog voltage through the first output end of the successive approximation device, so that the output end of the comparator sequentially outputs the comparison result, and the successive approximation logic control module outputs the corresponding multi-bit digital signal through a second output end of the successive approximation device according to the multiple comparison results after the successive approximation control is completed.

A third aspect of the present invention provides an electronic device comprising the successive approximation type analog-to-digital converter of the first aspect.

In the above scheme, the second input terminal of the comparator is coupled to the fixed reference voltage, and when the voltage input terminal is coupled to the other terminal of the capacitor, the comparator operates in a comparator mode and can output a comparison result; when the first output end of the successive approximation device is coupled with the capacitor and the first input end of the comparator is communicated with the output end of the comparator, the comparator works in a buffer memory mode, so that the first voltage of the output end/the first input end of the comparator is the difference between the fixed reference voltage and the mismatch voltage; since the mismatch voltage is typically small, the voltage at the output of the comparator can be about the fixed reference voltage. Thus, by reasonably setting the value of the fixed reference voltage, the voltage of the output end of the comparator can be larger than the saturation voltage of the output end when the comparator is used as a buffer and smaller than the difference value between the power supply voltage and the saturation voltage, the purpose that the voltage of the output end cannot change along with the change of the analog input voltage is realized, so that when the analog input voltage is less than the saturation voltage or close to the power supply voltage, the output voltage of the output end of the buffer can be ensured not to be less than the saturation voltage or close to the power supply voltage, namely, the output end of the comparator in the buffer mode can work in a saturation region, the problem that the conversion precision of the analog-to-digital converter is reduced due to inaccurate storage voltage caused by the reduction of loop gain is avoided, therefore, the input range of the analog input voltage received by the voltage input end is expanded under the condition that the analog-to-digital converter can keep higher conversion precision.

Additional features and advantages of the invention will be set forth in the detailed description which follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a successive approximation analog-to-digital converter;

FIG. 2 is a schematic diagram of an alternative successive approximation analog-to-digital converter;

fig. 3 is a schematic circuit structure diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that as used herein, the meaning of "coupled" includes direct connections between two or more circuit objects without any intervening circuit objects, as well as indirect connections between two or more circuit objects made through one or more intervening circuit objects. For example, two circuit objects that are directly connected to each other are said to be "coupled" to each other. Likewise, two circuit objects are also referred to as being "coupled" to each other if one or more intervening circuit objects are connected therebetween. That is, the term "coupled" may refer to a direct electrical connection or an indirect electrical connection, which means that other components, such as a resistor, a capacitor, etc., are spaced therebetween.

Fig. 1 is a schematic circuit diagram of a successive approximation type analog-to-digital converter. As shown in fig. 1, the successive approximation analog-to-digital converter/SAR ADC may include a comparator Comp, an oscillator OSC, a successive approximation Logic control module SAR Logic, and a digital-to-analog converter DAC. The successive approximation Logic control module SAR Logic can comprise a reset unit and an indication unit. The reset unit is used for receiving a reset signal RST, and the reset signal RST resets the SAR ADC to an initial state before the SAR ADC does not start working. The indicating unit is used for outputting an end signal Term, and the end signal Term indicates that the SAR ADC once analog-to-digital conversion process is ended when the end signal Term is changed from low level to high level.

The oscillator OSC may generate a clock signal CK, so that the successive approximation Logic control module SAR Logic outputs digital signals D9 to D0 (10-bit digital signals) according to a comparison result Comp output by an output terminal of the comparator Comp. The digital-to-analog converter DAC converts the digital signals D9-D0 into analog signals, i.e., the output signal DACO. The comparator Comp compares the Input signal Input with the output signal DACO of the digital-to-analog converter DAC and outputs the comparison result. The comparator Comp is manufactured with mismatch offset, i.e. the two inputs of the comparator Comp are not completely symmetrical, which means that the two inputs of the comparator Comp are different, resulting in inaccurate comparison function. The input mismatch voltage can be generally employed to identify this mismatch offset.

To eliminate or reduce the mismatch effect, one approach is to store the mismatch voltage and then cancel it out when compared. This scheme is described in detail below with reference to fig. 2.

Fig. 2 is a schematic circuit diagram of another successive approximation type analog-to-digital converter. The difference from the solution shown in fig. 1 is that in fig. 2, a switch S1 is coupled between the voltage Input terminal Input and the positive Input terminal of the comparator Comp, a switch S2 is coupled between the output terminal of the digital-to-analog converter DAC (from which the output signal DACO is output) and the positive Input terminal of the comparator Comp, the negative Input terminal of the comparator Comp is coupled to one terminal of a capacitor C1, the other terminal of the capacitor C1 is grounded, and a switch S3 is coupled between the negative Input terminal of the comparator Comp and the output terminal of the comparator Comp.

With continued reference to fig. 2, the oscillator OSC may generate a clock signal CK1, a clock signal CK2, and a clock signal CK 3. The clock signal CK1 is used to cause the successive approximation Logic control module SAR Logic to generate multi-bit digital signals D9-D0. The clock signal CK2 is used to control the on and off of the switch S1. The clock signal CK3 is used to control the on and off of the switch S2 and the switch S3.

The following description will be made by taking an example in which the switch is turned off at a high level and turned on at a low level. It will be appreciated that it is also possible to set the high level to turn the switch on and the low level to turn the switch off.

When the clock signal CK2 is at a high level and the clock signal CK3 is at a low level, the switch S2 and the switch S3 are turned on, and the switch S1 is turned off. At this time, the comparator Comp (the comparator is implemented by an operational amplifier inside) operates in a buffer manner, the voltage of the output signal DACO of the digital-to-analog converter DAC and the mismatch voltage are stored on the capacitor C1, and the voltage VC1 stored on the capacitor is equal to VDACO-Vos, assuming that the positive input terminal of the comparator Comp is higher Vos than the negative input terminal, where VDACO is the voltage value of DACO and Vos is the mismatch voltage.

When the clock signal CK3 is at high level and the clock signal CK2 is at low level, the switch S1 is turned on, the switch S2 and the switch S3 are turned off, and the comparator Comp compares the voltage Input from the voltage Input terminal with the voltage on the capacitor C1, and due to Vos, the actual comparison result is to compare VInput-Vos with the voltage of VC1, i.e., VDACO-Vos. Where VInput is the voltage value of Input and Vos is the mismatch voltage. Assuming that Vos is unchanged in the two processes, the VINput voltage and the voltage of VDACO are equivalently compared, so that the effect of offsetting the mismatch voltage Vos is realized.

The scheme in fig. 2, however, has a limit on the input range of VInput. Specifically, in order to ensure that the loop gain is high, the stored voltage has high accuracy and cannot be distorted, and further ensure that the analog-to-digital converter can keep high conversion precision, when the comparator is used as a buffer to use the stored voltage, the output end of the buffer needs to work in a saturation region, and when the comparator works in the saturation region, the output voltage of the output end of the buffer needs to be at least higher than the saturation voltage Vdsat and smaller than the difference value between the power supply voltage and the saturation voltage Vdsat.

Since in the scheme of fig. 2, the output voltage Comp of the comparator Comp in the buffer mode is close to the Input voltage VInput of the voltage Input terminal (because the output voltage Comp of the comparator Comp in the buffer mode is VDACO-Vos, where Vos is small, Comp ≈ VDACO, and VDACO successively approaches VInput, they are close to each other) and varies with the variation of the Input voltage VInput, when the Input voltage is lower than the saturation voltage Vdsat, the output voltage may be lower than the saturation voltage Vdsat, and the loop gain thereof may decrease, resulting in distortion, i.e. the stored voltage is inaccurate, and similarly, when the Input voltage VInput is close to the power supply voltage, the loop gain of the buffer may also decrease, resulting in the stored voltage being inaccurate. Therefore, the input range of the analog-to-digital converter is affected, that is, when the input voltage is too low or too high, the output of the analog-to-digital converter is biased, resulting in the reduction of the conversion accuracy.

That is to say, in the scheme in fig. 2, if it is to be ensured that the successive approximation type analog-to-digital converter can maintain higher conversion accuracy, the input range of the analog-to-digital converter needs to be smaller than the difference between the power voltage V and the saturation voltage Vdsat and larger than the saturation voltage Vdsat, that is, located between the interval [ Vdsat, V-Vdsat ], so as to ensure that the output stage of the buffer is operated in the saturation region. Thus, the scheme of FIG. 2 may have limitations on the input range of VINput. If the output voltage at the output terminal is lower than the saturation voltage Vdsat and is greater than the difference between the power supply voltage and the saturation voltage (or close to the power supply voltage), the loop gain will decrease, the stored voltage will be inaccurate, and distortion will be caused, so that the output of the analog-to-digital converter including the comparator will have deviation, and the conversion precision will decrease. Therefore, for applications requiring a large input range, the solution of fig. 2 has a problem of accuracy degradation.

In view of this, the embodiments of the present application provide a successive approximation type analog-to-digital converter and an electronic device, so that the voltage at the output end of a comparator can be approximately a fixed reference voltage, and by reasonably setting the value of the fixed reference voltage, the voltage at the output end of the comparator can be greater than the saturation voltage of the output end when the comparator is used as a buffer and smaller than the difference between the power voltage and the saturation voltage, so as to achieve the purpose that the voltage at the output end does not change along with the change of the analog input voltage, so that when the analog input voltage is smaller than the saturation voltage or close to the power voltage, it can be ensured that the output voltage at the output end of the buffer is not smaller than the saturation voltage or close to the power voltage, that is, the output end of the buffer can work in a saturation region, thereby avoiding the problem that the loop gain is reduced, which causes the storage voltage to be inaccurate and reduces the conversion accuracy of the analog-to-digital converter, and thus under the condition that the analog-to-digital converter can maintain higher conversion accuracy, the input range of the analog input voltage received by the voltage input terminal is expanded.

Fig. 3 is a schematic circuit structure diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application. As shown in fig. 3, the successive approximation type analog-to-digital converter/SAR ADC includes a voltage Input terminal Input, a comparator Comp, a capacitor C1, and a successive approximation device. The voltage Input terminal Input is used for receiving an analog Input voltage. A first input terminal of the comparator Comp is coupled to one terminal of the capacitor C1, and a second input terminal of the comparator Comp is coupled to the fixed reference voltage VREF. The fixed reference voltage VREF may be half of the power supply voltage or other voltages, for example, any voltage value of the common mode input range of the comparator operating in the buffer mode may be selected, i.e., the selected VREF voltage value satisfies the normal operation of the buffer.

The successive approximation device can comprise a digital-to-analog converter (DAC) and a successive approximation Logic control module (SAR Logic). The digital-to-analog converter DAC may be a capacitive array type digital-to-analog converter or a resistive array type digital-to-analog converter. The first Input terminal of the successive approximation device, i.e. the Input terminal of the SAR Logic, is coupled to the output terminal of the comparator Comp, the first output terminal of the successive approximation device, i.e. the output terminal of the DAC, is used for successively approximating the output analog voltage, i.e. the output signal DACO, and is alternately coupled to the other terminal of the capacitor C1 with the voltage Input terminal Input, and when the first output terminal of the successive approximation device, i.e. the output terminal of the DAC, is coupled to the capacitor C1, the first Input terminal of the comparator Comp is connected to the output terminal of the comparator Comp, and the second output terminal of the successive approximation device, i.e. the output terminal of the SAR Logic, is used for outputting the multi-bit digital signals D9-D0.

Specifically, when the first output terminal of the successive approximation apparatus, i.e., the output terminal of the DAC, is coupled to the capacitor C1, the first input terminal of the comparator Comp is communicated with the output terminal of the comparator Comp, which is in the buffer mode; when the voltage Input is coupled to the capacitor C1, the first Input of the comparator Comp is disconnected from the output of the comparator Comp, which is in comparator mode.

The input end of the successive approximation Logic control module SAR Logic receives multiple comparison results output by the output end of the comparator Comp, and outputs a multi-bit digital signal D9-D0 through the output end during successive approximation to perform successive approximation control on the digital-to-analog converter DAC. The digital-to-analog converter DAC is used for converting the multi-bit digital signal into an analog voltage and then outputting DACO through an output end of the digital-to-analog converter DAC. And after the successive approximation control is completed, the second output end of the successive approximation device, namely the output end of the SAR Logic, can output the multi-bit digital signals D9-D0. In this embodiment, the output terminal of the SAR Logic outputs 10-bit digital signals D9-D0, and in other embodiments, the output terminal of the SAR Logic may output 3, 4, 7, 12, etc. bit digital signals.

In the above scheme, the second Input terminal of the comparator Comp is coupled to the fixed reference voltage VREF, and when the voltage Input terminal is coupled to the other terminal of the capacitor C1, the comparator Comp operates in a comparator Comp mode and can output a comparison result; when the first output terminal of the successive approximation device is coupled to the capacitor C1 and the first input terminal of the comparator Comp is connected to the output terminal of the comparator Comp, the comparator Comp operates in a register mode, so that the first voltage at the output terminal/first input terminal of the comparator Comp is the difference between the fixed reference voltage VREF and the mismatch voltage; since the mismatch voltage is generally small, the voltage at the output of the comparator Comp can be about the fixed reference voltage VREF. Therefore, by reasonably setting the value of the fixed reference voltage VREF, the voltage of the output end of the comparator Comp can be larger than the saturation voltage of the output end when the comparator Comp is used as a buffer and smaller than the difference value of the power supply voltage and the saturation voltage, the purpose that the output end voltage can not change along with the change of the analog input voltage is realized, when the analog input voltage is smaller than the saturation voltage or close to the power supply voltage, the output voltage of the output end of the buffer can also be ensured not to be smaller than the saturation voltage or close to the power supply voltage, the problem that the storage voltage is inaccurate and the conversion precision of the analog-to-digital converter is reduced is avoided, and the input range of the analog input voltage received by the voltage input end is expanded under the condition that the analog-to-digital converter can keep higher conversion precision.

The working principle of the successive approximation type analog-to-digital converter according to the embodiment of the present application is further described below. The first input terminal of the comparator Comp may be a negative input terminal, and the second input terminal of the comparator Comp may be a positive input terminal. The voltage at the positive input terminal higher than the negative input terminal is the mismatch voltage Vos of the comparator Comp. At this time, the negative input terminal of the comparator Comp is coupled to one terminal of the capacitor C1, and the positive output terminal of the comparator Comp is coupled to the fixed reference voltage VREF. The output terminal and the voltage Input terminal of the digital-to-analog converter DAC are alternately coupled to the other terminal of the capacitor C1, and when the first output terminal of the digital-to-analog converter DAC is coupled to the capacitor C1, the negative Input terminal of the comparator Comp is connected to the output terminal of the comparator Comp.

The first output terminal of the successive approximation device, i.e. the output terminal of the DAC, and the voltage Input terminal are alternately coupled to the other end of the capacitor C1, so that the successive approximation device can successively approximate and output an analog voltage through the first output terminal according to multiple comparison results output by the output terminal of the comparator Comp, and the second output terminal of the successive approximation device, i.e. the output terminal of the SAR Logic, is used for outputting corresponding multi-bit digital signals D9-D0 (10-bit digital signals) according to the multiple comparison results.

When the first output terminal of the successive approximation apparatus is coupled to the capacitor C1, the first input terminal of the comparator Comp is connected to the output terminal of the comparator Comp, the comparator Comp operates in a buffer mode, and can latch and output the first voltage VREF-Vos at the negative input terminal to the output terminal of the comparator Comp, and the voltage stored at the two ends of the capacitor C1 is the difference VREF-Vos-VDACO between the first voltage at the negative input terminal and the analog voltage VDACO.

When the voltage Input terminal Input is coupled to the other terminal of the capacitor C1, the comparator Comp operates in a comparator mode, the second voltage at the negative Input terminal is the sum VInput + VREF-Vos-VDACO of the analog Input voltage VInput and the voltage stored across the capacitor C1, the comparator Comp compares the sum VInput + VREF-VDACO of the second voltage and the mismatch voltage with the fixed reference voltage VREF, and outputs the comparison result through the output terminal of the comparator Comp. Namely, the equivalent comparison of the sizes of VINput-VDACO and 0 can also be equivalently regarded as the comparison of the sizes of VINput and VDACO, and the influence of Vos is eliminated.

It should be noted that it can be defined that the voltage on the right side of the circuit is higher than the voltage on the left side, so the first voltage on the negative input terminal is VREF-Vos; the voltage stored at the two ends of the capacitor C1 is the difference between the first voltage VREF-Vos at the negative input end and the analog voltage VDACO, i.e., VREF-Vos-VDACO.

The successive approximation Logic control module SAR Logic is used for generating a multi-bit digital signal in the successive approximation process according to multiple comparison results so as to perform successive approximation control on the digital-to-analog converter DAC. The dac DACDAC is configured to convert the multi-bit digital signal into an analog voltage, and output the analog voltage through a first output terminal, so that the output terminal of the comparator Comp sequentially outputs a comparison result, and the successive approximation Logic control module SAR Logic outputs a corresponding multi-bit digital signal through a second output terminal according to multiple comparison results after the successive approximation control is completed.

With continued reference to fig. 3, the successive approximation analog to digital converter may also include switch S1, switch S2, and switch S3. The switch S1 is coupled between the voltage Input and the other end of the capacitor C1. The switch S2 is coupled between the first output terminal of the successive approximation device (from which the output signal DACO is output) and the other terminal of the capacitor C1. The switch S3 is coupled between the negative input terminal of the comparator Comp and the output terminal of the comparator Comp. When the switch S1 is turned on, the switch S2 and the switch S3 are turned off, and when the switch S2 and the switch S3 are turned on, the switch S1 is turned off. In one example, the closing and conducting of the switch S1 may be controlled using the clock signal CK2, and the closing and conducting of the switch S2 and the switch S3 may both be controlled using the clock signal CK 3.

The successive approximation analog to digital converter may further comprise an oscillator OSC. The oscillator OSC may provide a clock signal CK1, a clock signal CK2, and a clock signal CK 3. Clock signal CK1 may be used for successive approximation Logic control module SAR Logic to generate a multi-bit digital signal. The clock signal CK2 may be used to control the closing and conduction of the switch S1. The clock signal CK3 can be used to control the closing and conduction of the switches S2 and S3.

When the clock CK3 is at a high level (the clock CK2 is at a low level, and the clock CK2 and the clock CK3 are non-overlapped clocks), the switch S2 and the switch S3 are turned on, the switch S1 is turned off, and at this time, the comparator operates in a buffer mode, assuming that the mismatch voltage at the input end of the comparator is Vos (the positive input end is higher than the negative input end by Vos), the voltage at the negative input end of the buffer is VREF-Vos, the voltage VC1 stored at the two ends of the capacitor C1 is VREF-Vos-VDACO, where VDACO is the voltage value of DACO, Vos is the mismatch voltage, and VREF is the voltage value of the node VREF. When the clock CK2 is at a high level (the clock CK3 is at a low level, and the clocks CK2 and CK3 are non-overlapped clocks), the switch S2 and the switch S3 are turned off, the switch S1 is turned on, the negative input voltage of the comparator becomes VC1+ VInput ═ VREF-Vos-VDACO + VInput, and the actual comparison effect of the comparator is to compare the voltage magnitudes of VREF-Vos-VDACO + VInput and VREF-Vos due to the mismatch voltage Vos. Vos can be added to the comparison voltage quantity respectively, and the voltage magnitudes of VREF-VDACO + VINput and VREF are equivalently compared, so that the influence of Vos is eliminated.

Therefore, fig. 3 realizes the similar comparison effect as fig. 2, and therefore can realize the similar analog-to-digital conversion function, but the difference is that a direct constant VREF is provided at the positive input terminal of the comparator in fig. 3, when the comparator operates in the buffer mode, the output voltage of the buffer is equal to VREF-Vos, and Vos is generally less than 30mV, so that the voltage is close to VREF, and the reasonable designed VREF satisfies the requirement of being greater than Vsat voltage, which is smaller than VDD-Vsat voltage (where VDD is the power supply voltage and Vsat is the saturation voltage of the output stage of the buffer), so as to avoid the problem of abnormal operation of the buffer.

In addition, as shown in fig. 3, the successive approximation Logic control module SAR Logic may further include a reset unit and an indication unit. The reset unit is used for receiving a reset signal RST to reset the successive approximation type analog-to-digital converter/SAR ADC to an initial state. The indicating unit is used for outputting an end signal Term to indicate that one analog-to-digital conversion process of the successive approximation type analog-to-digital converter/SAR ADC is ended.

An embodiment of the present application further provides an electronic device, which includes the above successive approximation type analog-to-digital converter. Wherein the electronic device may further comprise an electronic component coupled to the successive approximation analog to digital converter. The electronic component may be any electronic component such as a discrete device, an integrated circuit, etc. For example, the electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, and any intermediate product including the semiconductor device.

In order to eliminate or reduce the mismatch effect, in the existing scheme of storing the mismatch voltage as shown in fig. 2, when the comparator is used as a buffer, when the analog input voltage is too low, e.g. lower than the saturation voltage Vdsat, the output voltage is also lower; when the analog input voltage is too high, such as close to the power supply voltage, the output voltage is also high, i.e., the output voltage is close to the analog input voltage and changes along with the change of the analog input voltage. Since the conversion accuracy of the mode converter is not degraded in order to make the storage voltage accurate when the comparator is used as a buffer, the output terminal of the buffer operates in the saturation region and has a limit to the range of the output voltage. Therefore, the conventional scheme also has a limitation on the input range of the analog input voltage, or influences the input range of the analog input voltage.

The purpose of the scheme of the application is to improve the input range of the analog-digital converter. Specifically, the voltage at the output terminal of the comparator can be about the fixed reference voltage according to the scheme of the embodiment of the present application. Thus, by reasonably setting the value of the fixed reference voltage, for example, half of the power supply voltage or other voltages: any voltage value of the common mode input range of the comparator working in the buffer mode can be selected, namely the selected VREF voltage value meets the requirement that the buffer normally works, the voltage of the output end of the comparator is larger than the saturation voltage of the output end when the comparator is used as a buffer and smaller than the difference value between the power supply voltage and the saturation voltage, thereby realizing the purpose that the voltage of the output end cannot change along with the change of the analog input voltage, so that when the analog input voltage is lower than the saturation voltage or close to the power supply voltage, the output voltage of the output end of the buffer can be ensured not to be lower than the saturation voltage or close to the power supply voltage, thereby avoiding the occurrence of inaccurate storage voltage caused by the reduction of loop gain, and the conversion precision of the analog-to-digital converter is reduced, so that the input range of the analog input voltage received by the voltage input end is expanded under the condition that the analog-to-digital converter can keep higher conversion precision.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A successive approximation analog-to-digital converter, comprising:

a voltage input for receiving an analog input voltage;

the first input end of the comparator is coupled with one end of the capacitor, and the second input end of the comparator is coupled with a fixed reference voltage;

and a successive approximation device, a first input end of which is coupled to an output end of the comparator, a first output end of which is used for successive approximation to output an analog voltage and is alternately coupled to the voltage input end, and when the first output end of which is coupled to the capacitor, the first input end of the comparator is communicated with the output end of the comparator, and a second output end of which is used for outputting a multi-bit digital signal.

2. The successive approximation analog-to-digital converter of claim 1, wherein:

when the first output end of the successive approximation device is coupled with the capacitor, the first input end of the comparator is communicated with the output end of the comparator, and the comparator is in a buffer mode;

when the voltage input is coupled to the capacitor, the first input of the comparator is disconnected from the output of the comparator, the comparator being in comparator mode.

3. The successive approximation analog-to-digital converter according to claim 1, further comprising:

a first switch coupled between the voltage input terminal and the other end of the capacitor;

a second switch coupled between a first output terminal of the successive approximation device and the other terminal of the capacitor;

a third switch coupled between the first input terminal of the comparator and the output terminal of the comparator;

when the first switch is turned on, the second switch and the third switch are turned off, and when the second switch and the third switch are turned on, the first switch is turned off.

4. A successive approximation analog to digital converter according to claim 3, characterized in that:

the closing and the conducting of the first switch are controlled by a first clock signal; the closing and the conducting of the second switch and the third switch are controlled by a second clock signal; and/or the presence of a gas in the gas,

the successive approximation type analog-to-digital converter further comprises an oscillator, wherein the oscillator is used for providing a first clock signal so as to control the closing and the conduction of the first switch; the oscillator is used for providing a second clock signal to control the second switch and the third switch to be closed and conducted.

5. A successive approximation analog-to-digital converter according to any of claims 1-4, characterized in that the successive approximation means comprise a successive approximation logic control module and a digital-to-analog converter, wherein:

the successive approximation logic control module is used for receiving multiple comparison results output by the output end of the comparator through the first input end and outputting the multi-bit digital signal through the second output end in the successive approximation process so as to perform successive approximation control on the digital-to-analog converter;

the digital-to-analog converter is used for converting the multi-bit digital signal into the analog voltage and then outputting the analog voltage through the first output end.

6. The successive approximation analog-to-digital converter according to claim 5, wherein the digital-to-analog converter is a capacitive array type digital-to-analog converter or a resistive array type digital-to-analog converter.

7. The successive approximation analog-to-digital converter according to claim 5, wherein the successive approximation logic control module comprises:

the resetting unit is used for resetting the successive approximation type analog-to-digital converter to an initial state; and/or the presence of a gas in the gas,

and the indicating unit is used for indicating the end of one analog-to-digital conversion process of the successive approximation type analog-to-digital converter.

8. A successive approximation analog-to-digital converter, comprising:

a voltage input for receiving an analog input voltage;

the first input end of the comparator is coupled with one end of the capacitor, the second input end of the comparator is coupled with a fixed reference voltage, and the voltage higher than the first input end of the comparator is the mismatch voltage of the comparator;

a successive approximation device, a first output end of which and the voltage input end are alternately coupled to the other end of the capacitor, so that the successive approximation device can successively approximate and output an analog voltage through the first output end according to a plurality of comparison results output by the output end of the comparator, and a second output end of the successive approximation device is used for outputting a corresponding multi-bit digital signal according to the plurality of comparison results; wherein:

when the first output end of the successive approximation device is coupled with the capacitor, the first input end of the comparator is communicated with the output end of the comparator, the comparator works in a buffer mode, a first voltage at the first input end of the comparator can be latched and output to the output end of the comparator, and the voltage stored at two ends of the capacitor is the difference between the first voltage and the analog voltage;

when the voltage input end is coupled with the other end of the capacitor, the comparator works in a comparator mode, a second voltage of a first input end of the comparator is the sum of the analog input voltage and the voltage stored at the two ends of the capacitor, and the comparator compares the sum of the second voltage and the mismatch voltage with the fixed reference voltage and outputs the comparison result through an output end of the comparator.

9. The successive approximation analog-to-digital converter of claim 8, wherein the successive approximation means comprises a digital-to-analog converter and a successive approximation logic control module, wherein:

the output end of the successive approximation logic control module is a second output end of the successive approximation device, and the successive approximation logic control module is used for generating a multi-bit digital signal in the successive approximation process according to the multiple comparison results so as to perform successive approximation control on the digital-to-analog converter;

the output end of the digital-to-analog converter is a first output end of the successive approximation device, and the digital-to-analog converter is used for converting the multi-bit digital signal into the analog voltage and outputting the analog voltage through the first output end of the successive approximation device, so that the output end of the comparator sequentially outputs the comparison result, and the successive approximation logic control module outputs the corresponding multi-bit digital signal through a second output end of the successive approximation device according to the multiple comparison results after the successive approximation control is completed.

10. An electronic device comprising a successive approximation analog-to-digital converter according to any of claims 1-9.

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