CN114220866A - Memory based on charge injection mechanism and preparation method thereof - Google Patents

Memory based on charge injection mechanism and preparation method thereof Download PDF

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Publication number
CN114220866A
CN114220866A CN202111390930.9A CN202111390930A CN114220866A CN 114220866 A CN114220866 A CN 114220866A CN 202111390930 A CN202111390930 A CN 202111390930A CN 114220866 A CN114220866 A CN 114220866A
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layer
control gate
substrate
charge storage
electrode
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Chinese (zh)
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陈旭东
鲁统部
张志成
李媛
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Tianjin University of Technology
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Tianjin University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7882—Programmable transistors with only two possible levels of programmation charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction

Abstract

The invention discloses a memory based on a charge injection mechanism and a preparation method thereof, which can be applied to the technical field of memories. The memory of the present invention comprises: a substrate; the control gate layer comprises tungsten selenide and is positioned on the substrate, and a gate electrode is arranged on the first end of the control gate layer and is used for connecting an external applied voltage; a threshold switching layer comprising a graphite oxide alkyne having a threshold switching characteristic, a first end of which is located above the substrate and a second end of which is located above a first end of the control gate layer; a charge storage layer comprising molybdenum sulfide located above the threshold switching layer; a blocking layer over the charge storage layer; and the channel layer is positioned on the barrier layer, a source electrode is arranged on the first end of the channel layer, and a drain electrode is arranged on the second end of the channel layer. The invention can realize ultra-fast write or erase operation.

Description

Memory based on charge injection mechanism and preparation method thereof
Technical Field
The invention relates to the technical field of memories, in particular to a memory based on a charge injection mechanism and a preparation method thereof.
Background
In the related art, the rapid development of the information age has been promoted by the continuous innovation of memory technologies including Random Access Memory (RAM) and Flash memory (Flash). With the development of the big data era, data shows exponential explosion increase. The current commercial mainstream silicon-based memory has the defects of low running speed, low storage capacity, complex structure, high energy consumption and the like, so that the requirement of large data access cannot be met.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a memory based on a charge injection mechanism and a preparation method thereof, which can realize ultra-fast injection and achieve the function of high-speed low-power-consumption nonvolatile memory.
In one aspect, an embodiment of the present invention provides a memory based on a charge injection mechanism, including:
a substrate;
the control gate layer comprises tungsten selenide, the control gate layer is positioned on the substrate, and a gate electrode is arranged on the first end of the control gate layer and is used for connecting an external applied voltage;
a threshold switching layer comprising oxidized graphdine having a threshold switching characteristic, a first end of the threshold switching layer being positioned over the substrate, a second end of the threshold switching layer being positioned over a first end of the control gate layer;
a charge storage layer comprising molybdenum sulfide, the charge storage layer being located above the threshold switching layer;
a blocking layer over the charge storage layer;
the channel layer is located on the barrier layer, a source electrode is arranged on the first end of the channel layer, and a drain electrode is arranged on the second end of the channel layer.
The memory based on the charge injection mechanism provided by the embodiment has the following beneficial effects:
in the embodiment, a control gate layer, a threshold switch layer, a charge storage layer, a barrier layer and a channel layer are sequentially stacked on a substrate, a first end of the threshold switch layer is positioned on the substrate, a second end of the threshold switch layer is positioned on the first end of the control gate layer, a gate electrode for connecting an external applied voltage is arranged on the first end of the control gate layer, and a source electrode and a drain electrode are arranged on the channel layer, so that the control gate and the charge storage layer are connected through graphite oxide alkyne with threshold conversion characteristics, low-voltage ultra-fast nonvolatile storage is realized, and the characteristic of directly injecting charges into the charge storage layer is realized, thereby realizing ultra-fast writing or erasing operation.
In some embodiments, the channel layer comprises molybdenum sulfide.
In some embodiments, the substrate comprises a silicon substrate.
In some embodiments, the barrier layer comprises boron nitride.
In some embodiments, the gate electrode, the source electrode, and the drain electrode comprise chromium and gold material.
On the other hand, the embodiment of the invention provides a preparation method of a memory based on a charge injection mechanism, which comprises the following steps:
treating the graphite alkyne film by ozone to obtain graphite alkyne oxide as a threshold switch layer;
preparing a charge storage layer, a channel layer, a barrier layer and a control gate layer containing tungsten selenide by adopting a mechanical stripping mode;
stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer on a substrate in sequence;
preparing a gate electrode on the control gate layer and respectively preparing a source electrode and a drain electrode on the channel layer by adopting a photoetching mode and a thermal evaporation mode;
wherein the control gate layer and the charge storage layer are connected by a graphite oxide alkyne having threshold switching characteristics.
In some embodiments, said sequentially stacking said control gate layer, said threshold switch layer, said charge storage layer, said blocking layer, and said channel layer on a substrate comprises:
and sequentially stacking the control gate layer, the threshold switch layer, the charge storage layer, the barrier layer and the channel layer on the substrate in a Van der Waals stacking mode.
In some embodiments, the fabricating a gate electrode on the control gate layer and a source electrode and a drain electrode on the channel layer respectively by using a photolithography method and a thermal evaporation method includes:
and preparing an electrode consisting of chromium and a gold material on the control gate layer as a gate electrode and preparing electrodes consisting of chromium and a gold material on the channel layer as a source electrode and a drain electrode respectively by adopting a photoetching mode and a thermal evaporation mode.
In some embodiments, the channel layer comprises molybdenum sulfide.
In some embodiments, the barrier layer comprises boron nitride.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The invention is further described with reference to the following figures and examples, in which:
FIG. 1 is a schematic structural diagram of a memory based on a charge injection mechanism according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for fabricating a memory based on a charge injection mechanism according to an embodiment of the present invention;
FIG. 3 is a flow-voltage graph of the positive voltage segment 2a according to an embodiment of the present invention;
FIG. 4 is a flow-voltage graph for the negative voltage segment 2b according to an embodiment of the present invention;
FIG. 5 is a graph illustrating a test of the writing and erasing capabilities of an embodiment of the present invention;
FIG. 6 is a test chart of the read speed according to the embodiment of the present invention;
FIG. 7 is a durability test chart of an embodiment of the present invention;
FIG. 8 is a graph of stability testing according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of the mechanism of applying nanosecond level negative pulse voltage to the control gate terminal according to the embodiment of the invention;
FIG. 10 is a schematic diagram of the mechanism after the negative voltage pulse is removed according to the embodiment of the present invention;
FIG. 11 is a schematic diagram of the mechanism of applying a symmetrical nanosecond positive voltage on the control gate in accordance with an embodiment of the invention;
FIG. 12 is a schematic diagram illustrating the mechanism of the present invention after the positive voltage pulse is removed;
FIG. 13 is a graph of the robust characteristics of an embodiment of the present invention over a range of temperatures;
FIG. 14 is a graph of robust features over a range of days of placement for an embodiment of the present invention;
FIG. 15 is a multi-bit storage capability test chart according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and the above, below, exceeding, etc. are understood as excluding the present numbers, and the above, below, within, etc. are understood as including the present numbers. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
In the description of the present invention, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
At present, commercial mainstream silicon-based memories have the defects of low running speed, low storage capacity, complex structure, high energy consumption and the like, and are not beneficial to the development of novel low-energy-consumption chips in the late molarity, so that a processor and a memory which integrate ultra-fast response, ultra-low voltage, ultra-long retention, ultra-high capacity and ultra-low energy consumption are urgently needed to meet the increasing data requirements.
In the related art, resistive switching memories based on two-dimensional materials have been widely studied by researchers. The resistive random access memory based on threshold conversion is widely applied to the fields of volatile storage and short-time-range plasticity artificial synapse due to the excellent characteristics of fast switching, high switching ratio and the like. The memory based on threshold conversion works by the following mechanism: under the action of the electric field, ions are driven to form a conductive path in the threshold characteristic material, and the threshold characteristic material quickly returns to an initial state after the power supply is cut off, so that the process of quick switching can be realized. Therefore, selection of a material that is prone to oxygen vacancies and defect vacancies facilitates formation of the conductive filament, thereby facilitating threshold switching.
Van der Waals stacking provides great convenience for constructing multifunctional heterojunction, and also provides a strategy for developing novel ultra-fast low-power-consumption memories. The floating gate memory based on the Van der Waals stack can realize ultra-fast nonvolatile storage, and due to the sharp interface of atoms between layers, the ultra-fast tunneling based on a Fowler-Nordheim tunneling mechanism can be realized, so that the limitation of a storage wall is broken. However, conventional floating gate memories tend to require higher operating voltages (tens of volts), which causes the Fowler-Nordheim tunneling mechanism based memory devices to consume more power while limiting their application in Complementary Metal Oxide Semiconductors (CMOS). In order to break through the limitation of the Fowler-Nordheim tunneling mechanism, a novel device structure is urgently needed to be designed to realize ultra-fast injection of charges at low voltage.
In this regard, referring to fig. 1, an embodiment of the present invention provides a memory based on a charge injection mechanism, including a substrate 110, a control gate layer 120, a threshold switching layer 130, a charge storage layer 140, a blocking layer 150, and a channel layer 160. Specifically, the substrate 110 may be a silicon substrate. The control gate layer 120 comprises tungsten selenide WSe2WSe of tungsten selenide2 A gate electrode 170 disposed on the substrate 110, wherein the first end of the control gate layer 120 is connected to an externally applied voltage; the threshold switching layer 130 includes a graphite oxide, acetylene GDYO, having a threshold switching characteristic, as a material having a known threshold characteristic, having a first end located on the substrate 110 and a second end located on the first end of the control gate layer 120; the control gate layer 120 and the charge storage layer 140 are connected through the oxidized graphite alkyne with threshold switching characteristics, so that ultra-fast writing or erasing operation of directly injecting charges into the charge storage layer 140 is realized, and low-voltage ultra-fast nonvolatile storage is realized. The charge storage layer 140 comprises molybdenum sulphide MoS2Above the threshold switching layer 130; a blocking layer 150 is located over charge storage layer 140; the channel layer 160 is disposed on the barrier layer 150, wherein a first end of the channel layer 160 is provided with a source electrode 180 thereon, and a second end of the channel layer 160 is provided with a drain electrode 190 thereon. The gate electrode 170, the source electrode 180, and the drain electrode 190 are each made of chromium and gold material. Wherein, the chromium Cr is 5nm chromium, and the gold Au is 50nm gold.
In this embodiment, the channel layer also includes sulfurMolybdenum MoS2The barrier layer comprises boron nitride hBN. Bottom molybdenum sulfide MoS2A charge storage layer formed on the threshold switch layer for storing WSe from tungsten selenide2The constituent control gates inject charge. A barrier layer composed of boron nitride hBN is positioned between the charge storage layer and the channel layer and used for blocking the charge on the charge storage layer from being injected into the top molybdenum sulfide MoS2A channel layer is formed. Top molybdenum sulphide MoS2The channel layer formed is located on the boron nitride hBN and is subjected to the bottom molybdenum sulfide MoS2Exhibit different electrical conductivity states.
The memory of the embodiment utilizes the threshold switch layer RS to connect a control gate and a charge storage layer to realize low-voltage ultra-fast nonvolatile storage. The threshold switch layer allows the control grid layer to directly inject charges into the charge storage layer so as to carry out ultra-fast writing/erasing operation, and the writing/erasing operation can be completed within about 20 ns; the injected charge is confined in the charge storage layer, which can also be understood as being confined in the floating gate, and can be retained for a long period of time, which can be about 10 years. In particular, compared with the conventional floating gate memory, the memory of the present embodiment can be driven with a low voltage (about 2V), and can achieve ultra-low power consumption of 10 fJ. Furthermore, the on/off ratio is high (10)7) And the nanosecond operation speed enables the memory to realize 3-bit storage under a few nanoseconds writing pulse, and the requirements on ultra high speed, ultra long retention, ultra high capacity and ultra low energy consumption are met.
In the embodiment, the graphyne has rich pi electrons and inherent defects, can be used as a novel threshold conversion characteristic material, can increase the concentration of oxygen vacancies on the surface of the graphyne by means of ozone treatment, and can form a conductive path of oxygen vacancies and defect vacancies by electric induction, thereby realizing threshold type switching.
Based on this, as shown in fig. 2, an embodiment of the present invention provides a method for manufacturing a memory based on a charge injection mechanism, including the following steps:
s210, treating the graphite alkyne film by adopting ozone to obtain oxidized graphite alkyne serving as a threshold switch layer;
s220, preparing a charge storage layer, a channel layer, a barrier layer and a control gate layer containing tungsten selenide by adopting a mechanical stripping mode;
and S230, sequentially stacking a control gate layer, a threshold switch layer, a charge storage layer, a barrier layer and a channel layer on the substrate, wherein the control gate layer and the charge storage layer are connected through oxidized graphite alkyne with threshold conversion characteristics. Specifically, the control gate layer, the threshold switching layer, the charge storage layer, the blocking layer, and the channel layer may be sequentially stacked on the substrate using a van der waals stacking method. The charge storage layer and the channel layer each comprise molybdenum sulfide and the barrier layer comprises boron nitride.
S240, preparing a grid electrode on the control grid layer and preparing a source electrode and a drain electrode on the channel layer respectively by adopting a photoetching mode and a thermal evaporation mode. Specifically, the gate electrode, the source electrode, and the drain electrode are each composed of chromium and a gold material. Wherein, the chromium Cr is 5nm chromium, and the gold Au is 50nm gold.
In this embodiment, because the current Fowler-Nordheim tunneling mechanism memory adopts the band-tilt tunneling mechanism, the required operating voltage is relatively large. Compared with the existing memory adopting a tunneling mechanism, the memory adopting the direct charge injection mechanism has the advantages of low operating voltage, low energy consumption and the like.
For the memory prepared in fig. 3, the present example was tested in the following manner:
the read speed of the device is measured by applying a voltage pulse of-2V (20ns)/2V (20ns) on the control gate, namely inputting 2V of 20ns after inputting-2V of 20ns, so as to study the write/erase capability of the device, and simultaneously detecting the delay time between the input pulse and the output pulse.
The cyclic durability of the device is researched by cyclically applying voltage pulses of-2V (20ns) and 2V (20ns) on the control gate, namely cyclically inputting voltage pulses of-2V and 2V for 20ns, and the stability of the device is researched by inputting voltage pulses of-2V/2V (20ns) on the control gate and adopting source drain voltage of 0.1V to read out the current state of the device.
The stability of the device to temperature dependence is researched by changing the ambient temperature of the device and detecting the source-drain current state change of the device, and the multi-bit storage capability of the device is researched by changing the input voltage of the control gate.
By researching the relation between the thickness of the threshold switch layer and the writing and erasing performance of the device, the thickness of the threshold switch layer is controlled to be about 10nm, so that the device presents the best performance; the ambient temperature is set in the range of 220K-350K to explore the temperature stability of the device; and the patterned threshold conversion characteristic material layer is adopted, so that the interference of a large-area threshold switch layer on the electrical performance of the device is reduced.
In general, the high-speed nonvolatile memory based on the direct charge injection mechanism provided by the present embodiment has the following advantages compared with the existing floating gate memory:
the first, conventional floating gate memory uses the F-N tunneling mechanism, which results in large energy consumption due to the large voltage required for the process of implementing the band-tilt charge injection. The direct injection mechanism based on the charges is adopted in the embodiment, so that the used voltage is small, and the energy consumption can be obviously reduced;
the tunneling dielectric layer of the second, conventional floating gate memory is often made of a material with a high dielectric constant, which results in a large barrier for charge injection. The invention adopts a conductive path formed by oxygen vacancies and defect vacancies in the threshold switch layer, thereby having high switching speed and strong response capability.
In other embodiments, the memory provided by the present embodiment is subjected to performance testing in multiple aspects by:
fig. 3 and 4 are current-voltage curves of the tungsten selenide/graphite oxide alkyne/molybdenum disulfide threshold resistance change switch of the memory of the embodiment. From the current-voltage (I-V) scan of the positive voltage segment 2a in fig. 3 and the negative voltage segment 2b in fig. 4, the device of the present embodiment has the threshold switching characteristic, and the steep I-V curve surface device at ± 1V has the extremely fast switching speed.
FIG. 5 is a diagram illustrating a test of the write/erase capability of the memory according to the present embodiment. As can be seen from fig. 5, the memory of this embodiment can be switched to the off state and the on state by applying voltage pulses of-2V (20ns) and 2V (20ns) to the control gate, respectively, indicating that the memory has nanosecond write and erase capability.
FIG. 6 is a test chart of the read speed of the memory according to the present embodiment. As can be seen from fig. 6, this embodiment applies a pulse group of a pulse width of 20ns and a pulse interval of 200ns by cycles, and detects an input pulse and an output pulse at the same time. As can be taken from fig. 6, the input signal and output signal delays are very short, indicating that the device has a very fast response speed.
FIG. 7 is a diagram illustrating endurance tests of the memory according to the present embodiment. This example monitors the change in electrical flow regime by cycling the application of-2V (20ns) and 2V (20ns)1000 times. As can be seen from fig. 7, there is little change in the switch-state current, indicating that the device has good endurance.
Fig. 8 is a stability test of the memory according to the embodiment. In the present embodiment, the current change is monitored at a source-drain voltage of 0.1V after a voltage pulse of-2V/2V (20ns) is applied. As can be seen from fig. 8, there is no significant change in the switch-state current, indicating that the device has good stability.
Fig. 9, fig. 10, fig. 11, and fig. 12 are mechanism explanations of the memory of this embodiment. When nanosecond negative pulse voltage is applied to the control gate end, the graphite alkyne oxide of the threshold switch layer is converted into a conducting state, and electrons are injected into molybdenum sulfide at the bottom through tungsten selenide, as shown in fig. 9; after the voltage pulse is removed, the graphite alkyne oxide of the threshold switch layer is switched to an off state, electrons entering the bottom molybdenum disulfide are stored in the graphite alkyne, the molybdenum disulfide channel at the top is exhausted, and the device is in the off state (writing process) at this time, as shown in fig. 10; on the contrary, when a symmetrical nanosecond positive voltage is applied to the control gate, electrons stored in the molybdenum disulfide at the bottom return to the tungsten selenide through the threshold switch layer to complete the erasing process, as shown in fig. 11; after the voltage pulse was removed, the molybdenum disulfide channel returned to the initial state, as shown in figure 12.
Fig. 13 and 14 show the robust characteristics of the memory of the present embodiment. The device has better robustness as seen by the on and off states of the test device shown in fig. 13 over the temperature range of 220K-350K, and the on and off states of the test device shown in fig. 14 when left for 0-60 days.
FIG. 15 is a multi-bit storage capability test of the memory of this embodiment. As can be seen from fig. 15, by applying different pulse voltages on the control gate, 8 different current levels are present, indicating its multi-bit storage capability.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Furthermore, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.

Claims (10)

1. A memory based on a charge injection mechanism, comprising:
a substrate;
the control gate layer comprises tungsten selenide, the control gate layer is positioned on the substrate, and a gate electrode is arranged on the first end of the control gate layer and is used for connecting an external applied voltage;
a threshold switching layer comprising oxidized graphdine having a threshold switching characteristic, a first end of the threshold switching layer being positioned over the substrate, a second end of the threshold switching layer being positioned over a first end of the control gate layer;
a charge storage layer comprising molybdenum sulfide, the charge storage layer being located above the threshold switching layer;
a blocking layer over the charge storage layer;
the channel layer is located on the barrier layer, a source electrode is arranged on the first end of the channel layer, and a drain electrode is arranged on the second end of the channel layer.
2. A charge injection mechanism based memory according to claim 1, wherein said channel layer comprises molybdenum sulfide.
3. The memory according to claim 1, wherein the substrate comprises a silicon substrate.
4. The memory of claim 1, wherein the blocking layer comprises boron nitride.
5. The memory of claim 1 wherein said gate electrode, said source electrode and said drain electrode comprise chromium and gold material.
6. A preparation method of a memory based on a charge injection mechanism is characterized by comprising the following steps:
treating the graphite alkyne film by ozone to obtain graphite alkyne oxide as a threshold switch layer;
preparing a charge storage layer, a channel layer, a barrier layer and a control gate layer containing tungsten selenide by adopting a mechanical stripping mode;
stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer on a substrate in sequence;
preparing a gate electrode on the control gate layer and respectively preparing a source electrode and a drain electrode on the channel layer by adopting a photoetching mode and a thermal evaporation mode;
wherein the control gate layer and the charge storage layer are connected by a graphite oxide alkyne having threshold switching characteristics.
7. The method according to claim 6, wherein the stacking the control gate layer, the threshold switch layer, the charge storage layer, the blocking layer and the channel layer on the substrate in this order comprises:
and sequentially stacking the control gate layer, the threshold switch layer, the charge storage layer, the barrier layer and the channel layer on the substrate in a Van der Waals stacking mode.
8. The method as claimed in claim 6, wherein the steps of forming a gate electrode on the control gate layer and forming a source electrode and a drain electrode on the channel layer by photolithography and thermal evaporation respectively comprise:
and preparing an electrode consisting of chromium and a gold material on the control gate layer as a gate electrode and preparing electrodes consisting of chromium and a gold material on the channel layer as a source electrode and a drain electrode respectively by adopting a photoetching mode and a thermal evaporation mode.
9. The method as claimed in claim 6, wherein the channel layer comprises molybdenum sulfide.
10. The method of claim 6, wherein the blocking layer comprises boron nitride.
CN202111390930.9A 2021-11-23 2021-11-23 Memory based on charge injection mechanism and preparation method thereof Pending CN114220866A (en)

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